JPH04304191A - Brushless motor driving circuit - Google Patents

Abstract

PURPOSE:To suppress noise and torque ripple by resetting a high frequency counter upon matching of outputs from two counters, respectively, counting high and low frequency clock signals in synchronism with the rotation of motor and employing the matched result as an internal clock signal. CONSTITUTION:Position signals S1-S3 are fed from three Hall elements HE1-HE3 to comparing circuits 2-4 respectively in order to obtain rectangular wave signals S5-S7 having phase difference of 120 deg.. The signals S5-S7 are stored 12 and subsequently subjected to exclusive-OR operation 6 thus obtaining an ORed output signal S11 which varies at all varying points of the signals S5-S7. A high frequency clock signal is created 40 from the signal S11 and fed through a counter 11 to the memory 12. When the count of the signals S5-S7 matches with the count of the counter 11, the counter 11 is reset and thus matched count is employed as an internal clock signal. According to the invention, noise and torque ripple are suppressed.

Description

[Detailed description of the invention]

0001

[Table of Contents] The present invention will be explained in the following order. Industrial application field Conventional technology (FIGS. 4 and 5) Problems to be solved by the invention (FIGS. 4 and 5) Means for solving the problems (FIGS. 2 and 3) Effects (FIGS. 2 and 3)
) Example (Figures 1 to 3) Effects of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a brushless motor drive circuit, and is suitable for application to a brushless motor drive circuit configured to drive a coil based on data stored in a predetermined storage means.

0003

[Prior Art] Conventionally, in brushless motor drive circuits, for the purpose of reducing drive noise, torque ripple, etc., supply current or voltage to a coil is applied based on data stored in a predetermined memory. something is proposed.

This method requires position information with higher precision than the magnetic position information detected by a rotation detection element such as a Hall element, so the frequency of the detection signal obtained from the Hall element is several tens of times higher. It generates a clock and interpolates the position information from the Hall element.

In other words, FIG. 4 shows three-phase bidirectional (full wave) 12
A brushless motor drive circuit of 0° energization type is shown, and the magnet can be activated by inputting magnet position detection signals S1, S2, and S3 obtained from Hall elements HE1, HE2, and HE3, respectively, to comparison circuits 2, 3, and 4, respectively. Rectangular wave signals S5, S6, and S7 (FIGS. 5(A), (B), and (C)) that vary depending on the position are obtained.

These rectangular wave signals S5, S6, and S7 are each input as an address designation signal to the address input terminal of the memory circuit 12, and are also input to the exclusive OR circuit 6.

The exclusive OR circuit 6 performs an exclusive OR operation on the input rectangular wave signals S5, S6, and S7, thereby generating a rectangular wave signal S as shown in FIG. 5(D).
5. All times t1, t2, t when S6 and S7 change
3, t4, t5, t6, t7, . . . , a logical operation output signal S11 that changes is obtained and sent to the edge extraction circuit 9 as well as to the phase comparison circuit 21 of the clock generation circuit section 8.

The clock generation circuit 8 is a voltage controlled oscillator (
VCO) 23, frequency dividing circuit 24, phase comparator circuit 21 and integrating circuit
oop) circuit, and divides the internal clock signal S12 output from the VCO 23 by 2N in the frequency divider circuit 24 to obtain a frequency-divided signal S13 as shown in FIG. The logical operation output signal S11 and the frequency-divided signal S13 are compared in the phase comparator circuit 21.

The phase comparison circuit 21 integrates the logic operation output signal S11 obtained based on the comparison result and the error component S14 of the frequency-divided signal S13 in the integration circuit 22, and feeds back the integration result S15 to the VCO 23. 5(
As shown in E), an internal clock signal S12 having a frequency 2N times that of the logical operation output signal S11 is output from the VCO 23.

Here, the internal clock signal S12 is input to the clock input terminal of the counter 11 having an N-ary counter configuration.

The edge extraction circuit 9 also outputs a calculation output signal S1.
Edge extraction signal S that rises for a short time at the change point of 1
17 (FIG. 5(F)) is obtained and supplied to the reset input terminal of the counter circuit 11.

Therefore, in the counter 11, by using the internal clock signal S12 as the clock for the N-ary counter and by performing a reset operation using the edge extraction signal S17, each change in the rise and fall of the logic operation output signal S11 is controlled. Points t1, t2, t3, t4, t5
, t6, t7, ..., and at the same time (
That is, the count value becomes 0), and the counting operation is started again, and N counts are made until the next reset point.

[0013] Thus, the counter 11 counts from time t1 to t2.
, t2-t3, t3-t4, t4-t5, t5-t6,
A count output signal S1 representing a count value from 0 to N in each count period from t6 to t7, ...
8 (FIG. 5(H)) is inputted to the address input terminal of the memory circuit 12 as an address designation signal.

In the memory circuit 12, rectangular wave signals S5, S6, and S7 are input to the address input terminal.
An address number ADN1 as shown in FIG. 5(I) is specified from each state.

Therefore, this address number ADN1 has a value corresponding to the magnet position information obtained based on the three Hall elements HE1, HE2, and HE3.

Further, the count values 0 to N of the count output signal S18 inputted to the address input terminal of the memory circuit 12 are at times t1 to t2, t2 to t3, t3 to t4, and t4 to t.
5, t5 to t6, t6 to t7, ... are each made into one unit, and the address number ADN1 (Fig. 5 (I)) is further
The divided address number ADN2 becomes address number A.
By detecting the position of the magnet by combining DN1 and ADN2, the position of the magnet can be detected with higher precision than when detecting the position of the magnet using only address number ADN1.

[0017] Therefore, address numbers ADN1 and ADN2
For addresses consisting of a combination of
Drive signal waveform data D1, D2, and D3 corresponding to the magnet position specified by N1 and ADN2 are stored, and the waveform data D1, D2, and D3 are outputted by address numbers ADN1 and ADN2. ,
It is converted into an analog signal via the following digital-to-analog conversion circuits 13, 14 and 15, and further an amplifier circuit 16,
After being amplified to a predetermined level via 17 and 18, it is output to drive coils LU, LV, and LW.

[0018] Therefore, the drive coils LU, LV and LW
The drive current (or voltage) waveforms SU, SV, and SW that are energized are a combination of drive signal waveforms that are subdivided according to the position of the magnet as shown in Figures 5 (J), (K), and (L). The brushless motor drive circuit 1 is designed to generate a drive signal waveform depending on the position of the magnet.

[0019]

However, when attempting to drive a brushless motor using such a method, the clock generating circuit 8 having a PLL circuit configuration using the integrating circuit 22 generates a signal that is 2N times the logical operation output signal S11. By generating the internal clock signal S12 with the frequency of the calculation output signal S1, the frequency of the internal clock signal S12 is
If the frequency is far from the frequency 2N times the frequency of 1, several tens of cycles of the logical operation output signal S11 are required before the PLL circuit locks in.

Therefore, when the brushless motor rotates at high speed and at a constant rotational speed, it is possible to generate a drive signal waveform within a practically sufficient range, but when the brushless motor is started, the rotational speed suddenly changes. In this case, the internal clock signal S
12 and the logical operation output signal S11, there is a problem that the memory circuit 12 cannot output an accurate drive signal waveform according to the position of the magnet, and the drive signal waveform is distorted. Ta.

[0021] Therefore, it becomes difficult to drive the brushless motor with low noise and low torque ripple.

Furthermore, since circuit elements such as capacitors are required to configure the VCO 23 and the integrating circuit 22, these circuit elements must be externally attached when integrated into an IC. There was a problem that made it impossible to downsize the .

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a brushless motor drive circuit that can output a drive signal waveform with better responsiveness to changes in the rotation of a brushless motor.

[0024]

[Means for Solving the Problems] In order to solve the problems, in the present invention, rotational position detection obtained from a predetermined internal clock signal S40 synchronized with the rotation of the brushless motor and predetermined rotation detection means HE1, HE2, HE3 is provided. In the brushless motor drive circuit 30 that drives the brushless motor based on the signals S1, S2, and S3, a first count is performed based on the low frequency clock signal S33, and is reset in synchronization with the number of rotations of the brushless motor.
a second counter 48 that counts based on a high frequency clock signal S32 and is reset in synchronization with the number of rotations of the brushless motor, and a holding means for holding the count value of the first counter 45. 46 and
Comparing means 47 for comparing the count value held in the holding means 46 and the count value of the second counter 48,
Every time the comparison result in the comparing means 47 matches, the second counter 48 is reset and the matching result is used as the internal clock signal S40.

[0025]

[Operation] Clock signals S33 and S with different frequencies
Among the first and second counters 45 and 48, which perform counting operations based on clock signal S32 and are reset in synchronization with the rotation speed of the brushless motor, the first counter performs counting operations based on clock signal S33, which has a lower frequency. The count value of 45 is held in a predetermined register 46, and the count value held in the register 46 is compared with the count value of a second counter 48 that performs counting operation based on the high frequency clock signal S32, and the comparison result is calculated. By resetting the second counter 48 every time the numbers match and using the matching detection signal as the internal clock signal S40, it is possible to obtain an internal clock signal that responds immediately when the number of rotations of the brushless motor changes. a drive signal SU that tracks the rotational state of the brushless motor with high precision by outputting drive signals SU, SV, and SW of the brushless motor based on the internal clock signal;
SV and SW can be obtained.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG.
is input to the clock generation circuit 40.

As shown in FIG. 2, this clock generation circuit 40 inputs the logic operation output signal S11 to the edge extraction circuit 41, thereby determining the change point t1 of the operation output signal S11.
, t2, t3, . . . , an edge extraction signal S31 (FIG. 3(B)) that rises for a short time is inputted to the reset input terminals of the 1/N frequency divider 43, counter 45, and counter 48, and 46 clock input terminal.

The 1/N frequency dividing circuit 43 receives the edge extraction signal S3.
The clock signal S32 (FIG. 3(F)) output from the oscillator 42 is divided by 1/N to obtain the clock signal S33 shown in FIG. 3(C). input to the clock input terminal.

The counter circuit 45 receives the edge extraction signal S31.
(t1) and the clock signal S
By performing a counting operation based on 33, the count value (m) up to the next reset operation (t2) is calculated as shown in FIG. 3 (D
) is sent to the register 46 as a count output signal S34.

By inputting the edge extraction signal S31 to the clock input terminal at time t2, the register 46 receives the edge extraction signal S31.
The count value m of the counter 45 immediately before the edge extraction signal S31 rises (that is, immediately before the counter 45 is reset) is taken in (FIG. 3(E)).

Here, the count value m is a value proportional to the time T1 corresponding to a half period of the logical operation output signal S11.

Further, the counter 48 inputs the clock signal S32 to the clock input terminal and also inputs the edge extraction signal S31 to the reset input terminal, so that after being reset by the edge extraction signal S31, the counter 45 starts counting operation. The counting operation starts at the same time as the start.

Further, the counter 48 inputs a clock signal S32 having a frequency N times that of the clock signal S33 inputted to the counter 45, thereby reducing the time (T1) of the time taken by the counter 45 to count the count value m by 1/N. The count value m is counted in the time of , and the count result is sent to the count output signal S36 (Figure
(G)) to the comparison circuit 47.

The comparison circuit 47 outputs a register output signal S35 obtained from the register 46 (FIG. 3(E)) and a counter output signal S36 obtained from the counter 48 (FIG. 3(G)).
), and when they match, the match detection signal S37 (FIG. 3(H)) is inputted to the first input terminal of the subsequent AND circuit AND1, and the second input terminal of the counter 48 is inputted.
It is fed back to the reset input terminal of the

Therefore, the counter 48 receives the register output signal S35 (FIG. 3(E)) obtained from the register 46 and the counter output signal S36 obtained from the counter 48 (FIG. 3(E)).
G)) is reset when they match.

Here, when the count value reaches m at time t2A in FIG. 3, the count value m of the counter 45 during the period T1 has already been input to the register 46, so the counter 48 is reset and becomes 0 again. The counting operation is started from , and when the count value reaches m again, it is reset, and thereafter this is repeated until the state of the register 46 changes.

In this state, the coincidence detection signal S37 of the comparator circuit 47 is output at a period of time T2A, which is 1/N of T1, so that T1 becomes N times T2, and N times in a half period of the logical operation output signal S11. It is possible to obtain the coincidence detection signal S37 (that is, the frequency is 2N times that of the logical operation output signal S11).

Here, the AND circuit AND1 inputs the clock signal S32 to its second input terminal, performs an AND operation on the coincidence detection signal S37 and the clock signal S32, and extracts a narrow width called a glitch from the coincidence detection signal S37. It is designed to remove pulse noise components before outputting.

In this way, the output signal of the AND circuit AND1 is used as the internal clock signal S40 and the counter circuit 11 of FIG.
input to the clock input terminal.

By generating the internal clock signal S40 in this manner, the half period T1 of the calculation output signal S11 is
The period of the calculation output signal S11 is set to the clock signal S34.
By using the measured value m to generate an accurate internal clock signal S40 in the subsequent half cycle, the internal clock signal S40 is more responsive to the frequency change of the logical operation output signal S11. can be obtained.

In the above configuration, the brushless motor drive circuit 30 detects the cycle of the logical operation output signal S11 outputted from the exclusive OR circuit 6 at time t2 when a half period of the logical operation output signal S11 has elapsed, and detects the period of the logical operation output signal S11. By being able to immediately output the internal clock signal S40 in accordance with
40 can be output.

Therefore, since the number of internal clock signals S40 with respect to the period of the logic operation output signal S11 can always be kept constant, even when the number of rotations of the brushless motor changes rapidly, the position of the magnet can be determined from the memory circuit 12. Accurate drive signal waveform SU, SV according to
and SW can be obtained.

According to the above configuration, the responsiveness of the internal clock signal S40 synchronized with the rotation of the brushless motor can be greatly improved, so that the drive signal waveform SU, which is always accurate regardless of the rotational state of the brushless motor, can be obtained. SV and SW
The brushless motor can always be driven with low noise and low torque ripple.

Incidentally, compared to the conventional PLL circuit configuration, since circuit elements such as capacitors are not used, the IC
In this case, the brushless motor drive circuit 30 can be further downsized.

[0046]

As described above, according to the present invention, the first and second counters execute counting operations based on clock signals having different frequencies and are reset in synchronization with the rotation speed of the brushless motor. A count value of a first counter that performs a counting operation based on a clock signal with a low frequency is held in a predetermined register, and a second counter that performs a counting operation based on the value held in the register and a clock signal with a high frequency. The count values of the brushless motor are compared, and each time the comparison results match, the second counter is reset and the matching detection signal is used as the internal clock signal. This makes it possible to create an internal clock with good responsiveness to the rotational speed of the brushless motor. By being able to obtain the signal and driving the brushless motor based on the internal clock signal, it is possible to realize a brushless motor drive circuit that can drive the brushless motor with even lower noise and lower torque ripple.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a brushless motor drive circuit according to the present invention.

FIG. 2 is a block diagram showing the configuration of a clock signal generation circuit according to the present invention.

FIG. 3 is a signal waveform diagram for explaining clock signal generation according to the present invention.

FIG. 4 is a block diagram showing a conventional brushless motor drive circuit.

FIG. 5 is a signal waveform diagram for explaining the operation of a conventional brushless motor drive circuit.

[Explanation of symbols]

1, 30... Brushless motor drive circuit, 6... Exclusive OR circuit, 9, 41... Edge extraction circuit, 11, 45
, 48... Counter, 12... Memory circuit, 40... Clock generation circuit, 42... Oscillator, 43... 1/N frequency divider circuit, 46... Register, 47... Comparison circuit, AND
1...Logic product circuit, LU, LV, LW...drive coil.

Claims (1)

[Claims] 1. In a brushless motor drive circuit that drives the brushless motor based on a predetermined internal clock signal synchronized with the rotation of the brushless motor and a rotational position detection signal obtained from a predetermined rotation detection means, a low frequency clock signal is used. a first counter that counts based on the clock signal and is reset in synchronization with the rotation speed of the brushless motor; and a first counter that counts based on the high frequency clock signal and is reset in synchronization with the rotation speed of the brushless motor. a second counter, a holding means for holding the count value of the first counter, and a comparison means for comparing the count value held in the holding means and the count value of the second counter, A brushless motor drive circuit characterized in that the second counter is reset each time the comparison result in the comparison means matches, and the match result is used as the internal clock signal.