JPH04304532A - Computer provided with debugging function for rom program - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a processing speed by unnecessitating a complicated circuit or an access program for always attaching a ROM and a RAM to the same address, and performing an access to both of them. CONSTITUTION:Either a debugging operation or a normal operation is selected by an operation selecting switch 1, the value is latched to a latch circuit 3 by a reset pulse by a reset switch 2, and outputted as an operation selecting signal. A CPU 4 outputs an address A1 as a start address after the reset. An address decode circuit assigns a ROM 6, and doesn't assign a RAM 7 to the address A1 in the case of the normal operation, based on the operation selecting signal. The address decode circuit assigns one part of the RAM 7, and doesn't assign the ROM 6 to the address A1 in the case of the debugging operation. The program is written in the RAM of the address different from the address of the ROM in the case of the normal operation, the ROM is not used at the time of the debuggding, the address of the RAM is switched to the address of the ROM in order to operate the debugging, so that it is not necessary to change a command using the absolute address in the program.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer with a function for debugging a program stored in a ROM, and more particularly to a computer that debugs a program stored in a ROM on a RAM.

0002

[Prior Art] In a conventional computer, a program is written to a RAM at a different address from the ROM address for debugging, or a ROM is written at the same address.
and RAM, and executes the program written in RAM during debugging and ROM during normal operation.
Execute the program written in the RO
I removed M and installed RAM in its place for debugging.

0003

[Problem to be Solved by the Invention] In this conventional computer, the RAM has an address different from that of the ROM.
If you write a program and debug it, the address will be different from the address actually used, so if there is an instruction in the program that uses an absolute address, the address will need to be changed, making complete debugging impossible. There was a point.

Furthermore, when using RAM mounted at the same address as the ROM address, the problem of address changes during programming can be avoided, but during normal operation, the RAM
becomes unnecessary. Furthermore, if an attempt is made to use RAM that is no longer needed as a data area, there is a problem in that the circuit configuration for accessing the RAM becomes complicated, and an access program is required, resulting in a reduction in processing speed.

[0005] Furthermore, in the method of replacing ROM with RAM, computers that require initial settings using a program, such as one-chip microcomputers, cannot be initialized when the power is turned on, so this method is limited to computers that can be used. There was a problem that

[0006]

[Means for Solving the Problems] A computer with a debugging function for a ROMized program of the present invention has an operation selection switch for selecting whether to perform debugging operation or normal operation, and a reset pulse generated by a reset switch. The device includes a latch circuit that latches the value of the operation selection switch and sends it out as an operation selection signal, and an address decode circuit that changes the memory map of ROM and RAM based on the operation selection signal from the latch circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a functional block diagram of an embodiment of the present invention. Select whether to perform debug operation or normal operation with operation selection switch 1, and reset switch 2.
By latching the value of the operation selection switch 1 with the reset pulse generated by the latch circuit 3, an operation selection signal S1 is created which determines which operation is to be performed at the time of reset. CPU4 operated by program
The ROM 6 stores a program for initializing the computer during debug operation, stores a program that has been debugged during normal operation, and stores the program and data being debugged during debug operation.
During normal operation, a RAM 7 for storing data is connected via a CPU bus 10. In addition, the ROM 6 or RAM 7 can be directly connected to the input/output device 9 without going through the operation of the CPU 4.
A DMA circuit 8 for access is also connected to the CPU bus 10. A signal from the CPU bus 10 causes R
The address decode circuit 5 which outputs the OM selection signal S2 or the RAM selection signal S3 switches the memory map between debug operation and normal operation depending on the value of the operation selection signal S1 from the latch circuit 3.

Next, the operation will be explained.

FIG. 2 shows a memory map during debug operation.
FIG. 3 is a memory map during normal operation. First, DM
The A circuit 8 becomes operational, and the ROM is
6 or RAM 7 can be accessed, and the operation selection switch 1 is set to normal operation and reset. The CPU 4 outputs address A1, which is the start address after reset,
The address decode circuit 5 outputs a ROM selection signal S2, executes the program in the ROM 6, and enables the DMA circuit 8. Next, the program to be debugged is transferred from the input/output device 9 to the RAM 7c. At this time, the transfer start address becomes address A3, but there is no need to change the address of the program to be debugged.

Next, when the operation selection switch 1 is set to debug operation and reset is applied, the address decode circuit 5
A RAM selection signal S3 for accessing RAM 7c as RAM 7a is output, and the program being debugged written from address A3 in normal operation is executed from address A1, which is the start address after CPU 4 is reset.

At this time, access to the ROM 6 is prohibited. The addresses of the RAM 7b at addresses greater than or equal to address A2 and less than address A3 remain unchanged in both debug and normal operations. Further, the RAM 7c at address A3 or above can be used as a data area after debugging is completed.

In the above embodiment, the initial setting program for the computer is written in the ROM 6, but if a computer that does not require initial settings is used, the ROM 6 may not be present during debugging. Furthermore, in the above embodiment,
Although DMA circuit 8 was used, the program being debugged was
The method of writing to AM7c is not limited to this.

[0014]

As explained above, the present invention switches the memory map during debugging operation and normal operation at reset, so that the program can be written to a RAM address different from the ROM address for debugging. It eliminates the need to change instructions that use absolute addresses, and also eliminates the need for complex circuits to always attach ROM and RAM to the same address and access them.
No access program is required, and processing speed does not decrease. It also has the advantage that it can be used on computers that require initial settings using a program.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a memory map during debugging operation.

FIG. 3 is a diagram showing a memory map during normal operation.

[Explanation of symbols]

1 Operation selection switch 2 Reset switch 3 Latch circuit 4 CPU 5 Address decoding circuit 6 ROM 7 RAM 8 DMA circuit 9 Input/output device 10 CPU bus

Claims (1)

[Claims] 1. An operation selection switch that selects whether to perform a debug operation or a normal operation, and a latch circuit that latches the value of the operation selection switch using a reset pulse generated by a reset switch and sends it as an operation selection signal. A computer with a debugging function for a ROMized program, comprising: an address decoding circuit that changes a memory map between a ROM and a RAM based on the operation selection signal from the latch circuit.