JPH04304577A - Image processor - Google Patents

Abstract

PURPOSE:To surely process an image even in the speed unbalance of an input processing and the image processing and to enhance the usage efficiency of a memory device in an image processor which gives image data from an image scanner to an image processing part through a FIFO memory. CONSTITUTION:The FIFO memory is constituted by a FIFO controller 9 and a multi-port memory 8 and the multi-port memory 8 sequentially executes the writing and reading of image data from the image scanner 1 by the FIFO controller 9 and the writing and the reading of data from a system side so that the multi-port memory 8 is used as the FIFO memory device and also utilized as the memory for extending the main memory at the system side.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing input image data from an image scanner.

0002

2. Description of the Related Art Some apparatuses for processing images read by an image scanner have the configuration shown in FIG. 2 or 3. Figure 2
, an image scanner 1 reads figures, characters, etc. of drawings and documents as images as continuous dot data by raster scanning, and an input processing unit 2 converts the dot data into digital data by binarizing, multi-value, etc. , the image memories 31 to 3n store input-processed dot data on a screen-by-screen basis, and the image processing section 4 stores the input-processed dot data in screen units.
Image processing such as feature extraction and contour enhancement is performed from the image data stored in .about.3n. The CPU 5 and main memory 6 store processing results in the main memory 6 or transfer them to other devices (CAD, etc.) via the system bus, and also control each section.

The image processing apparatus having this configuration stores image data read by the image scanner 1 in an image memory 31.
~3n, and image processing such as data conversion is performed by the image processing unit 4 or CPU 5.

The configuration shown in FIG. 3 stores processing data of the input processing section 2 in a FIFO (First In First Out)
) The image memories 31 to 3n of the configuration shown in FIG.
make it unnecessary.

In this configuration, the FIFO memory 7 has a buffer function that absorbs an imbalance between image reading speed and image processing speed, and is not particularly necessary if there is no speed imbalance.

[0006]

In a conventional image processing apparatus, when an A0 size drawing is input with an accuracy of 16 dots/mm, the amount of information becomes 32 megabytes. In order to perform image processing on such a large amount of data, the method shown in FIG. Alternatively, three pages are required, which requires a huge memory capacity.

Furthermore, processing such a large amount of information requires a high-speed image processing means, requires a special memory structure suitable for image processing, and is less versatile.

Furthermore, since the input-processed image data is temporarily stored in the image memories 31 to 3n, image processing cannot be executed until the storage is completed, resulting in poor processing efficiency.

On the other hand, in the system shown in FIG. 3, input processing and image processing are performed in parallel, making the image memories 31 to 3n unnecessary. However, since the image processing unit 4 performs pipeline processing using line memory for several lines of image data in order to extract image features, etc., the image processing speed is improved compared to the system shown in FIG. becomes difficult.

For this reason, if the average input speed of images exceeds the average processing speed of the image processing section 4 due to differences in the performance of the image scanner, or if the data is temporarily held in the FIFO memory 7 due to speed imbalance. If the maximum amount of data becomes large, the FIFO memory 7 needs to have a large capacity. In an extreme case, a FIFO memory equivalent to 32 megabytes is required to eliminate the speed imbalance between input processing and image processing, but providing it only for eliminating the imbalance reduces memory utilization efficiency.

[0011] FIFO memory is a multi-stage shift register, or a memory device and a FIFO memory.
However, if the shift register method is used, the circuit scale would be enormous and it would be almost impossible to apply it as the FIFO memory 7 mentioned above, and it would be difficult to use it as a memory device. Even if a combination of a controller and a controller is adopted, a large capacity memory device is required, and the same problem as in the case of FIG. 2 in which an image memory is provided remains.

[0012] An object of the present invention is to provide an image processing apparatus that ensures reliable image processing even when there is a speed imbalance between input processing and image processing in a FIFO memory system using a memory device and its controller, and that also improves the utilization efficiency of the memory device. It is about providing.

[0013]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an image scanner that reads images by raster scanning, and a FIFO memory that sequentially writes and sequentially reads digitized image data from the image scanner into a memory device. , an image processing unit that sequentially processes the image data read from this memory, and a CP that takes in the processing results of this image processing unit via the system bus.
An image processing device including a U and a main memory,
The FIFO memory has a FIFO controller and a multi-port memory, and image data is sequentially written/read from the image scanner under the control of the controller and data is transferred through the system bus under the control of the CPU. It is characterized in that it has a configuration for writing/reading.

[0014]

[Operation] According to the present invention configured as described above, the multiport memory is used as a FIFO memory required during image processing, and after the image processing is completed, it has the same memory function as the main memory when viewed from the system bus side. The memory can be used as an expansion memory for the main memory.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention. The difference between this figure and FIG. 3 is that a multiport memory 8 and a FIFO controller 9 are provided in place of the FIFO memory 7.

Multiport memory 8 has a first port connected to the system bus and a second port connected to the FIFO controller. The FIFO controller 9 sequentially writes image data from the input processing section 2 into the multiport memory 8 and controls sequential readout from the memory 8, and transfers the read image data to the image processing section 4.

On the other hand, the CPU 5 controls writing and reading data to the multiport memory 8 through the system bus, and transfers the multiport memory 8 to the main memory 6.
Used as memory for capacity expansion. For example, the multiport memory 8 is used as a program memory or data memory for the CPU 5.

In the above configuration, for image processing, the multiport memory 8 and the FIFO controller 9 use data to absorb the imbalance between the image reading speed of the image scanner 1 and the image data processing speed of the image processing unit 4. As a buffer, it controls the sequential writing and sequential reading of image data.

In this image processing, for image processing of A0 size drawings, as mentioned above, a FIFO memory of 32 megabytes is required in the worst case due to speed imbalance, and the multiport memory 8 is configured to have that capacity. . Here, when the image processing is completed, the FIFO processing becomes unnecessary and the multiport memory 8 is used as an extension memory of the main memory 6 or the like.

For example, after image processing is completed, the CPU 5
uses large-capacity analysis programs to perform processing such as deciphering shapes and recognizing characters using image data.
By writing this program into the multiport memory 8, the required capacity of the main memory 6 is reduced.

Further, after the image processing is completed, the original image data read by the image scanner 1 is written in the multiport memory 8, and this image data is read out from the multiport memory 8 to the CPU side and sent to other systems. It is used for character recognition, etc. along with data provision and image processing result data.

Furthermore, when the size of the drawing to be image processed is small or when image processing is performed with low precision (dots/mm), there is a surplus capacity in the multiport memory 8 even during image processing, and this surplus capacity is used to store the capacity of the main memory 6. Use it as an extension.

[0023]

[Effects of the Invention] As described above, according to the present invention, FIF
In an image processing device using the O memory method, the FIFO memory is configured with a multiport memory and a FIFO controller, and the multiport memory is configured so that data can be written/read from the system bus side. By designing the necessary capacity in the worst case where there is a speed imbalance between processing and input processing or a large difference in image processing speed, image processing can be ensured.
Moreover, by using the multiport memory for expanding the main memory on the system side, memory usage efficiency can be improved. Furthermore, since input image data remains in the multiport memory after image processing, this data can be used for processing on the system side.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a conventional configuration diagram.

FIG. 3 is a conventional configuration diagram.

[Explanation of symbols]

1... Image scanner, 2... Input processing unit, 4... Image processing unit, 5... CPU, 6... Main memory, 8... Multiport memory, 9... FIFO controller.

Claims (1)

[Claims] 1. An image scanner that reads an image by raster scanning, a FIFO memory that sequentially writes and sequentially reads digitized image data from the image scanner into a memory device, and an image that sequentially performs image processing on the image data read from this memory. In an image processing device including a processing unit, a CPU and a main memory that take in processing results of the image processing unit via a system bus, the FIFO memory includes a FIFO controller and a multiport memory, and the FIFO memory includes a FIFO controller and a multiport memory. An image processing apparatus characterized in that the image processing apparatus is configured to sequentially write/read image data from the image scanner under the control of the controller and write/read data through a system bus under the control of the CPU.