JPH0430457A - Monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To keep a monolithic integrated circuit high in yield and low in cost and to protect a semi-insulator board against cracks and warpage by a method wherein the semiconductor board is divided into two pieces, a first semi-insulator board provided with an active circuit element and a part of a passive circuit element and a second semi-insulator board provided with only a passive circuit element. CONSTITUTION:A direct voltage is applied to a first gate bias applying terminal 18, a second gate bias applying terminal 20, and a drain bias applying terminal 21 to enable a first semiconductor element 22, a second semiconductor element 23, and a third semiconductor 24 to start operating. At this point, inductors 25, 26, and 27 and a capacitor 28 function to prevent signals from penetrating into the terminals 18-21. An active circuit including the semiconductor elements 22-24 located at a first semi-insulator board 1 and a passive circuit including the inductors 25-27 and the capacitor 28 are connected together with gold wires 11-14 through the intermediary of bonding pads 3-6 and 7-10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to amplifiers, phase shifters, switches, mixers, etc. in satellite communications, mobile communications, radar, etc.

It relates to monolithic integrated circuits used in multipliers and the like.

[Conventional technology]

Figure 2 shows, for example, "Broadband High Power Camolithic Amplifier Using Split FET with Built-in Feedback Resistor" by Nao Takagi et al., IEICE Spring National Conference, C-724, P2-533.1.
989 is an equivalent circuit diagram showing the conventional monolithic integrated circuit, and FIG. 3 is a block diagram showing the specific structure of the monolithic microwave integrated circuit. Output terminal, 18 is a first gate bias application terminal, 19 is a second gate bias application terminal, 20 is a third gate bias application terminal, 21 is a drain bias application terminal, 22 is a first stage semiconductor element,
23 is a second stage semiconductor element, 24 is a third stage semiconductor element, 2
5 is the first inductor, 26 is the second inductor, 27
is a third inductor, and 28 is a capacitor, which are formed on a single insulator substrate 29 using semiconductor process technology. Further, each of the semiconductor elements 22 to 24 constitutes an active circuit element, and each of the inductors 25 to 27 and the capacitor 2
8 and the like constitute passive circuit elements.

Next, the operation will be explained.

First gate bias application terminal 18. Second gate bias application terminal 19. Third gate bias application terminal 20
A DC voltage for operating the first-stage semiconductor device 22, second-stage semiconductor device 23, and third-stage semiconductor device 24 is applied to the drain bias application terminal 21. At this time, the first inductor 25. second inductor 26
．． The third inductor 27 and capacitor 28 serve as matching circuit elements and prevent signals from leaking into each of the bias application terminals 18 to 21.

Further, the signal input from the input terminal 16 is transmitted to the first stage semiconductor element 22, the second stage semiconductor element 23, and the third stage semiconductor element 2.
4 and output from the output terminal 17.

[Problem to be solved by the invention]

Since the conventional monolithic integrated circuit is configured as described above, each semiconductor element 22 to 24 and each inductor 25
~27. As the number of passive circuit elements such as capacitors 28 increases, the size of the single insulator substrate 29 increases, resulting in lower yields, higher costs, and problems such as the semiconductor substrate 29 cracking or warping. there were.

This invention was made to solve the above-mentioned problems, and aims to provide a monolithic integrated circuit that can maintain a high yield, reduce costs, and prevent cracking and warping of semiconductor substrates. purpose.

[Means to solve the problem]

A monolithic integrated circuit according to the present invention includes a first single insulator substrate having an active circuit element, a part of the passive circuit element, and a first bonding pad connected to the active circuit element, and a first single insulator substrate having only the passive circuit element and a part of the passive circuit element connected to the first bonding pad. and a second single insulator substrate having a second bonding pad, and the first bonding pad and the second bonding pad are connected by a connecting means.

[Effect]

The monolithic integrated circuit in this invention is divided into a first single insulator substrate having active circuit elements and a portion of passive circuit elements, and a second single insulator substrate having only passive circuit elements. To improve yield by reducing the size of the body substrate and preventing cracking and warping. Further, since the second single insulator substrate has only passive circuit elements, it is possible to significantly improve yield by reducing the number of masks required for semiconductor processing. This improves the yield of monolithic microwave integrated circuits made up of the first and second single insulator substrates, making it possible to significantly reduce costs.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a FET and a diode.

A first single insulator substrate having active circuit elements 22 to 24 such as transistors and a part of passive circuit elements, 2 is a passive circuit element such as a spiral inductor, a loop inductor, a multilayer capacitor, an interdigital capacitor, a bent line, a resistor, etc. a second single insulator substrate having only 25-28; 3, 4, 5°6; first bonding pads connected to active circuit elements 22-25, respectively; 7, 8.9.1;
0 are the second terminals connected to the passive circuit elements 22 to 24, respectively.
The bonding pads 11, 12, 13 and 14 are respectively connected to the corresponding first bonding pads. Connecting means such as gold wire or gold ribbon connects the second bonding pads, and 15 is a source resistor. In addition, the first bonding pads 3 to 6
are formed on a first single insulator substrate 1, and second bonding pads 7-10 are formed on a second single insulator substrate 2. Note that the source resistor 15 is produced on the second single insulator substrate 2 as a Yupi resistor, an ion implanted resistor, or the like.

Next, the operation will be explained.

The microwave integrated circuit of the present invention has a two-part structure as described above, but basically realizes the same circuit as shown in FIG. 2, and performs the same operation as the conventional one. That is, the first gate bias application terminal 18. Second gate bias application terminal 19. The third gate bias application terminal 20 and the drain bias application terminal 21 have 1
A DC voltage is applied to operate the semiconductor element 22, the semiconductor element 23 of the second stage, and the semiconductor element 24 of the third stage. At this time, the first inductor 25 degrees, the second inductor 26 degrees. Third inductor 27 and capacitor 28
serves as a matching circuit element and also prevents signals from leaking into each bias application terminal 18-21. Further, a signal input from the input terminal 16 is amplified by the first-stage semiconductor element 22 , the second-stage semiconductor element 23 , and the third-stage semiconductor element 24 , and is output from the output terminal 17 .

Further, the semiconductor elements 22 to 24 on the first single insulator substrate 1 side
and each inductor 25 to 27 on the second single insulator substrate 2 side. The passive circuit including the capacitor 28 etc. is the first bonding pad 3 to 6 and the second bonding pad 28 as described above.
each gold wire 11 via the bonding pads 7 to 10 of
.about.14, and the signal flow between these two circuits is performed with high efficiency as in the conventional case. Also, especially
By providing only passive circuits on the second single insulator substrate 2, it is possible to expect a significant increase in yield by reducing the number of masks required for semiconductor processing, which will ultimately contribute to improving the overall yield of monolithic integrated circuits. I will do it.

Furthermore, when a resistor is provided on the second single insulator substrate 2, a Yupi resistor or an ion-implanted resistor can be used, so the resistance value is lower than when a thin film resistor is provided on a dielectric substrate. Expands the selection range.

In addition, since the same single insulator substrates 1 and 2 are used as the first and second substrates, the effect of discontinuity at the joints of each board is small, and the deterioration of reflection characteristics at the joints is reduced. . The yield improvement effect becomes more pronounced as the number of semiconductor elements used increases and as the scale of the circuit increases.

In the above embodiment, the case where three semiconductor elements 22 to 24 are included is shown, but the number may be any number.

Further, in the above embodiment, the input terminal 16 and the output terminal 17
Although shown is a case where both are provided on the first single insulator substrate 1, both may be provided on the second single insulator substrate 2, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a first single insulator substrate having an active circuit element, a part of a passive circuit element, and a first bonding pad connected thereto; A second single insulator substrate having a connected second bonding pad is configured to connect the first bonding pad and the second bonding pad, so each single insulator substrate can be miniaturized. This has the effect of improving yield and reducing cost, preventing cracking and warping of the single insulator substrate, and providing a highly reliable monolithic integrated circuit.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a monolithic integrated circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional monolithic integrated circuit, and Fig. 3 is a circuit diagram showing a conventional monolithic integrated circuit. FIG. 1 is a configuration diagram showing a monolithic integrated circuit. 1 is a first single insulator substrate, 2 is a second single insulator substrate, 3
, 4, 5.6 are the first bonding pads, 7, 8, 9
, 10 are second bonding pads, 11, 12, 13
．． 14 is a connecting means (gold wire); 22, 23, 24 are active circuit elements (semiconductor elements); 25, 26, 27 are passive circuit elements (inductors); and 28 are passive circuit elements (capacitors). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 others)

Claims (1)

[Claims] a first single insulator substrate having only the active circuit elements and a portion of the passive circuit elements and a first bonding pad connected thereto; a second single insulator substrate having only the passive circuit elements and a second bonding pad connected thereto; 1. A monolithic integrated circuit comprising: two single insulator substrates; and connection means for connecting said first bonding pad and said second bonding pad.