JPH0430466A - Semiconductor electrode - Google Patents
Semiconductor electrodeInfo
- Publication number
- JPH0430466A JPH0430466A JP2135721A JP13572190A JPH0430466A JP H0430466 A JPH0430466 A JP H0430466A JP 2135721 A JP2135721 A JP 2135721A JP 13572190 A JP13572190 A JP 13572190A JP H0430466 A JPH0430466 A JP H0430466A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- film
- oxide film
- word line
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体のキャパシタ等の電極に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to electrodes for semiconductor capacitors and the like.
従来、キャパシタ等に用いる導電体より成る電極の上に
おいては通常、酸化膜のみを用いるのが一般的であった
。Conventionally, it has been common to use only an oxide film on an electrode made of a conductor used in a capacitor or the like.
例として、ダイナミック型ランダムアクセスメモリ(以
下DRAMと呼ぷ)のメモリセルを構成するキャパシタ
の場合について説明する。第2図に示す様にしゃもじ型
をした。半導体基板中に不純物を注入させたフィールド
活性領域(1)と、その上に酸化膜や窒化膜より成る絶
縁膜(2)を介し、化学的に堆積させたポリシリコンに
よるセルプレート用の電極(3)とでエフのメモリセル
は構成すれる。As an example, the case of a capacitor forming a memory cell of a dynamic random access memory (hereinafter referred to as DRAM) will be described. It was shaped like a rice scoop as shown in Figure 2. A field active region (1) in which impurities are implanted into a semiconductor substrate, and an electrode for a cell plate made of chemically deposited polysilicon (2) on which an insulating film (2) made of an oxide film or a nitride film is interposed. 3) constitutes the memory cell of F.
フィールド活性領域(1)が電気的な情報を蓄積するノ
ードであり、ポリシリコンの電極(2)は一定の電位に
固定され、酸化膜や窒化膜により両者は絶縁され、キャ
パシタとして機能する。The field active region (1) is a node that stores electrical information, and the polysilicon electrode (2) is fixed at a constant potential and is insulated by an oxide film or a nitride film, functioning as a capacitor.
半導体電極の製造方法としては、P型半導体基板(4)
において、まず第2図中のしゃもじ型のフィールド活性
領域(1)以外を素子分離のため厚(酸化し、キャパシ
タ部となるポリシリコンの下KN型の拡散層(1)とな
る様、砒素等の不純物をイオン注入により形成する。As a method for manufacturing a semiconductor electrode, a P-type semiconductor substrate (4)
First, areas other than the rice scoop-shaped field active region (1) in FIG. 2 are oxidized to form a KN-type diffusion layer (1) under the polysilicon that will become the capacitor part. Impurities are formed by ion implantation.
その後、キャパシタ絶縁膜であるシリコン酸化膜(Si
02)+31を化学的に堆積させ、セルプレートとなる
第1ポリシリコン(2)を堆積させる。After that, a silicon oxide film (Si
02) Chemically deposit +31 to deposit the first polysilicon (2) which will become the cell plate.
さらにセル選択用のトランジスタとするため。Furthermore, it is used as a transistor for cell selection.
酸化膜(3)を形成した後にN20ポリシリコンヲ作成
シ、トランジスタのシース。ドレインとなるN型子鈍物
を注入し、読み出し/書き込みの情報伝達用のビットI
I(5)を、トランジスタのソースと電気的に接続する
為のコンタクトホール(6)全開ケタ後に、タングステ
ンシリサイド等の高融点金属のシリコン酸化物で形成す
る。After forming the oxide film (3), N20 polysilicon is made to form the sheath of the transistor. Inject an N-type obtuse material to become the drain, and bit I for reading/writing information transmission.
I (5) is formed of silicon oxide of a high melting point metal such as tungsten silicide after the contact hole (6) for electrical connection with the source of the transistor is fully opened.
N3図はそのメモリセル部の断面図を示している0
点線で示すように、セルプレートの上には隣のセルの選
択用のワード線(6)が走る事になる。この為、このワ
ード線(6)の下のセルプレートである第1ポリシリコ
ンは%第2ポリシリコンのデボや拡散層の不純物注入後
の熱処理で、ワード繰下以外の場所はさらに酸化されて
、グレインが成長して大きくなるにも拘わらず1元の小
さいグレインサイズのまま残る事になる。Figure N3 shows a cross-sectional view of the memory cell portion. As shown by the dotted line, a word line (6) for selecting an adjacent cell runs above the cell plate. For this reason, the first polysilicon, which is the cell plate below this word line (6), is further oxidized in areas other than the word line due to the heat treatment after the second polysilicon is devoted and the impurity implanted into the diffusion layer. , even though the grains grow and become larger, the grain size remains as small as 1 element.
その状態を第4図に示す。The state is shown in FIG.
従来の半導体電極は以上のように構成されていたので、
ワード線である第2ポリシリコンの下では、セルグレー
トである第1ポリシリコンが、さまざまな熱処理がある
Kも拘わらず酸化されずに小さいグレインサイズのま才
残る。Conventional semiconductor electrodes were constructed as described above, so
Under the second polysilicon, which is a word line, the first polysilicon, which is a cell rate, is not oxidized and remains with a small grain size despite various heat treatments.
この時、@1ポリシリコン膜で生じる応力に、小さいグ
レインサイズと大きいグレインサイズとの境界で不均衡
が生じ易くなる事が考えられる。At this time, it is considered that the stress generated in the @1 polysilicon film tends to become unbalanced at the boundary between the small grain size and the large grain size.
不均衡が生じると、キャパシタ絶縁用の極めて薄い酸化
膜Kかかるストレスにも同様に不均衡か生じ、この酸化
膜にかかるストレスに不均衡があると絶縁用の酸化膜の
信頼性に大きt影響を与え。If an imbalance occurs, the stress applied to the extremely thin oxide film for capacitor insulation will also be unbalanced, and if there is an imbalance in the stress applied to this oxide film, it will greatly affect the reliability of the insulation oxide film. give.
例えば製品となってからの連続使用中に発生するビット
不良を加速する要因とtったり、さらにはその製品の寿
命を縮めるなどの問題点があった。For example, there have been problems such as accelerating bit defects that occur during continuous use after the product has been manufactured, and further shortening the life of the product.
この発明は上記のような問題点を解消する為になされた
もので、簡単な工程の追加でW、lポリシリコンのグレ
インサイズを揃えることができ、また酸化膜にかかるス
トレスを均一にして信頼性の高い半導体電極を得る事を
目的とする。This invention was made to solve the above-mentioned problems. It is possible to make the grain size of W and l polysilicon uniform by adding a simple process, and it also makes the stress on the oxide film uniform, improving reliability. The aim is to obtain semiconductor electrodes with high properties.
この発明に係る半導体電極は、従来のポリシリコンの上
に保護膜を生成し、ポリシリコンのグレインサイズを均
一に揃えて、下の酸化膜Kかかるストレスを均一になる
ようにしたものである。In the semiconductor electrode according to the present invention, a protective film is formed on conventional polysilicon, and the grain size of the polysilicon is made uniform, so that the stress applied to the underlying oxide film K is made uniform.
この発明における半導体電極は、薄い保護膜により覆わ
れている為、後の熱処理で酸化されてグレインか成長す
ることがなく、またワード線の上下によらずキャパシタ
用の酸化膜に接する面は、常にグレインの大きさか揃う
為に応力の不均衡か生じる事かない。Since the semiconductor electrode in this invention is covered with a thin protective film, it will not be oxidized and grow grains during subsequent heat treatment, and the surface in contact with the capacitor oxide film, regardless of whether it is above or below the word line, Because the grain sizes are always the same, there is no stress imbalance.
従ってキャパシタ用酸化膜Kかかるストレスはどこでも
均一となり、高い信頼性を確保する事が可能である。Therefore, the stress applied to the capacitor oxide film K is uniform everywhere, making it possible to ensure high reliability.
以下、この発明の一実施例を図について説明するO
第1図はこの発明の一実施例であるメモリセルのワード
線部分の拡大断面図である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an enlarged sectional view of a word line portion of a memory cell according to an embodiment of the present invention.
図において、(1)は拡散層、(2)はセルプレート用
ポリシリコン、(3)は酸化膜、(4)は基板、(6)
はワード線、(7)は窒化膜である。In the figure, (1) is a diffusion layer, (2) is a cell plate polysilicon, (3) is an oxide film, (4) is a substrate, and (6) is a
(7) is a word line, and (7) is a nitride film.
第1図において、斜線で示すワード線(6)の下に位置
するセルプレート用ポリシリコン(2)は薄い窒化膜(
7)により保護されている。In FIG. 1, the cell plate polysilicon (2) located below the hatched word line (6) is covered with a thin nitride film (
7).
その結果、セルプレート用ポリシリコン(2)が。As a result, cell plate polysilicon (2) was produced.
熱処理でも酸化されずに小さいグレインサイズのまま残
っている。Even after heat treatment, the grain size remains small without being oxidized.
半導体電極の製造方法としては従来の工程と同様に、基
板(4)上にフィールド活性領域(1)を作成した後、
キャパシタ用の酸化絶縁膜(3)を作成し、第1ポリシ
リコン(2)をまず堆積する。その後、窒化膜(’7)
を堆積した後に、酸化膜(3)を堆積する。The method for manufacturing a semiconductor electrode is similar to the conventional process, after creating a field active region (1) on a substrate (4),
An oxide insulating film (3) for the capacitor is created, and first polysilicon (2) is deposited. After that, nitride film ('7)
After that, an oxide film (3) is deposited.
その後のワード線(6)、ビット41)(5)の作成に
関しては前記従来のものと全く同一方法で、何等問題は
ない。The subsequent creation of the word line (6) and bits 41 and 5 is performed in exactly the same manner as the conventional method, and there is no problem.
以上のようにこの発明によれば、簡単な工程の追加だけ
で、信頼性が従来に比べ格段に向上した半導体に用いる
キャパシタ用の電極を得る事がで會る〇As described above, according to the present invention, it is possible to obtain electrodes for capacitors used in semiconductors with significantly improved reliability compared to conventional methods by simply adding a simple process.
第1図はこの発明の一実施例である半導体電極をDRA
Mのメモリセル部に適用した拡大断面図、第2図は従来
のDRAMにおけるメモリセル部の平面図、第3図は従
来のDRAMにおけるメモリセル部の断面図、第4図は
第3図の一部分の拡大断面図である。
図において、(1)は拡散層、(2)はセルプレート用
ポリシリコン、(3)は酸化膜、(4)は基板、(6)
はワード線、(7)は窒化膜を示す。
なお、図中、同一符号は同一 または相当部分を示す。FIG. 1 shows a semiconductor electrode according to an embodiment of the present invention.
2 is a plan view of the memory cell portion of a conventional DRAM, FIG. 3 is a sectional view of the memory cell portion of a conventional DRAM, and FIG. 4 is a cross-sectional view of the memory cell portion of the conventional DRAM. FIG. 3 is an enlarged cross-sectional view of a portion. In the figure, (1) is a diffusion layer, (2) is a cell plate polysilicon, (3) is an oxide film, (4) is a substrate, and (6) is a
indicates a word line, and (7) indicates a nitride film. In addition, the same symbols in the figures indicate the same or equivalent parts.
Claims (1)
おいて、前記半導体基板を1方の電極とし、薄い酸化膜
を挾んでその上に形成するポリシリコン等の導体より成
る他方の電極の上に、窒化膜等の電気的に絶縁された保
護膜をのせたことを特徴とする半導体電極。In a capacitor formed on a P-type or N-type semiconductor substrate, the semiconductor substrate is used as one electrode, and a thin oxide film is sandwiched between the capacitors and the other electrode made of a conductor such as polysilicon formed thereon. A semiconductor electrode characterized in that it is coated with an electrically insulating protective film such as a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2135721A JPH0430466A (en) | 1990-05-25 | 1990-05-25 | Semiconductor electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2135721A JPH0430466A (en) | 1990-05-25 | 1990-05-25 | Semiconductor electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0430466A true JPH0430466A (en) | 1992-02-03 |
Family
ID=15158331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2135721A Pending JPH0430466A (en) | 1990-05-25 | 1990-05-25 | Semiconductor electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430466A (en) |
-
1990
- 1990-05-25 JP JP2135721A patent/JPH0430466A/en active Pending
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