JPH0430475A - Thin film transistor array substrate - Google Patents

Abstract

PURPOSE:To lessen a gate wiring in resistance by a method wherein the gate wiring is formed into a two-layered structure. CONSTITUTION:First, a gate wiring 3 is patterned on a transparent substrate, and an insulating film 7 is formed thereon. Then, two contact holes serving as contacts 11 are provided to the insulating film 7 formed on the gate wiring 3. Then, an Al layer is formed as thick as prescribed so as to penetrate in the contacts 11, which is patterned into a source wiring 5, a drain electrode 6, and a gate wiring 10 at the same time. By this setup, as the gate wiring 10 of Al or the like low in resistance is provided besides the gate wiring 3, a gate wiring can be lessened in resistance without increasing patterning processes in number and decreasing insulation resistance between a gate and a source.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a thin film transistor array substrate used, for example, in a liquid crystal display.

(Prior Art) Conventional thin film transistor array substrates are used in, for example, panel-type liquid crystal displays.

For example, Figure N4 is a plan view of one pixel of a thin film transistor array substrate using conventional inverted staggered thin film transistors disclosed in Japanese Patent Application Laid-Open No. 1-138124, and Figure 5 is a plan view taken along the line V-V in Figure 4. FIG.

In the figure, (1) is a transparent insulating substrate such as glass, (2 is
) is a transparent pixel electrode, and ITO is generally used.

(3) is the gate wiring, which is generally a high melting point metal (Cr).
, M,, T+) are used, and (3a) is the gate electrode. (4) is a semiconductor layer, (5) is a source wiring,
(5a) is a source electrode. (6) is a train electrode, and (5) and (6) are both aluminum (AJ
2) is used. (7) is an insulating film, which serves both as an insulating film between the eyebrows and as a gate insulating film.

(8) is a material such as silicon nitride (SIN). (9) is a thin film transistor.

Next, the operation will be explained. As shown in Figure 4,
When a voltage is applied to the gate electrode (3a) through the gate wiring (3), carriers are induced in the semiconductor layer (4), the source electrode (5a) and the drain electrode (6) are electrically connected, and the thin film transistor (9) is activated. The state becomes θN.

Also, gate electric ti! 1 (3a), the thin film transistor (9) is in an OFF state.

In this way, the gate wiring (3) that controls the ON-OFF operation of the thin film transistor is thinly formed on the transparent insulating substrate (1), as shown in FIG.

(Problems to be Solved by the Invention) As described above, in the conventional thin film transistor array substrate, since a high melting point metal is used for the gate wiring (3), the resistance value of the gate wiring becomes high, and the rise of the gate signal increases. This caused a delay in time (switching speed).

For this reason, in the past, AJZ was used for the gate wiring (3) and a process was added to form two layers. However, with this conventional method, the number of patterning steps for the gate wiring increases, and the step coverage of the insulating film on the gate wiring deteriorates, reducing the gate-source breakdown voltage and increasing the film thickness. There were problems such as not being able to form a thick layer, and hillocks of (1) A1 occurring, resulting in a drop in breakdown voltage due to poor coverage of the insulating film.

This invention was made to solve the above problems, and its purpose is to significantly reduce the resistance of the gate wiring, eliminate the increase in the number of patterning steps, and reduce the breakdown voltage between the gate and source. An object of the present invention is to provide a thin film transistor array substrate in which this phenomenon is unlikely to occur.

(Means for Solving the Problems) In order to achieve the above object, a thin film transistor array substrate of the present invention includes a plurality of pixel electrodes provided on an insulating substrate, and a source wiring for manually transmitting signals to the pixel electrodes. and,
A thin film transistor array substrate having a thin film transistor for switching a signal to the pixel electrode, and a first gate wiring disposed on the insulating substrate for manually applying a signal for scanning a pixel to the thin film transistor. '! was formed simultaneously with the source wiring on the insulating film of the first gate wiring except for the intersection between the first gate wiring and the source wiring. J2 gate wiring and a contact portion formed on the insulating film to connect the first gate wiring and the second gate wiring, and the gate wiring is connected to the second gate wiring.
Characterized by stratification.

[Effect]

In the thin film transistor array substrate of the present invention, gate wiring resistance can be reduced by having two layers of gate wiring, and since the second gate wiring is formed at the same time as the source wiring, there is no need to increase the number of patterning steps. <Can be implemented.

(Embodiments) Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

FIG. 1 is a plan view showing one embodiment of the present invention, FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a plan view showing another embodiment of the present invention. be.

In the figure, reference numerals (1) to (9) are the same as those in the conventional example shown in FIGS. 4 and 5, and therefore redundant explanation will be omitted.

However, hydrogenated amorphous silicon is used here for the first gate wiring (3) and the semiconductor layer (4), and (
10) is a second gate wiring, and (11) is a contact portion that makes contact between the first gate wiring (3) and the second gate wiring (10).

As shown in FIG. 2, first, a first gate wiring (3) is patterned on a transparent insulating substrate (1), and then an insulating film (7) is formed. Next, as shown in FIGS. 1 and 2, two contact holes (11) are opened in the insulating film (7) on the first gate wiring (3) by etching.

Then, after forming an A42 layer, which is a low-resistance wiring material, to a predetermined thickness so as to penetrate into this contact portion (11), patterning is performed to form a source wiring (5) and a drain electrode (6) as shown in FIG. ) and the second gate wiring (10) are formed at the same time. Note that here, the semiconductor layer (
Forming steps such as 4) are omitted.

In the thin film transistor array substrate of this example configured in this way, in addition to the conventional first gate wiring (3), a second gate wiring (lO) made of low resistance A1 or the like is formed. This made it possible to significantly reduce gate wiring resistance. This speeds up the rise time (switching speed) of the gate signal, making it possible to shorten the frame rate.

Furthermore, since the gate-source structure of this embodiment shown in FIG. 1 is the same as the conventional one shown in FIG. 4, the film thickness of the second gate wiring (10) is Even if it is formed thicker than before, it does not affect the breakdown voltage between the gate and source.

Furthermore, since the second gate wiring (10) is formed simultaneously with the source wiring (5) and the like as described above, there is an advantage that the gate wiring can be made into two layers without increasing the number of patterning steps.

Next, FIG. 3 shows another embodiment.

In the previous embodiment, the contact between the first gate wiring (3) and the second gate wiring (lO) was made using two contact holes, but in this example, the contact between the first gate wiring (3) and the second gate wiring (lO) was made using two contact holes. In this way, the insulating film on the first gate wiring (3) may be removed linearly except for the intersection with the source wiring (5) to establish contact.

Further, in the above embodiment, the second gate wiring (10)
may be formed with a two-layer structure of All/C, for example.

Even in the case of such an embodiment, favorable effects similar to those described above can be achieved.

〔Effect of the invention〕

As described above, according to the thin film transistor array substrate of the present invention, the gate wiring is made into two layers, and the second gate wiring is formed simultaneously with the formation of the source wiring, so that the resistance of the thin film transistor is reduced by lowering the resistance of the gate wiring. Characteristics (switching speed) are improved, performance is improved, and voltage resistance between the gate and source is less likely to occur.
The number of patterning steps is the same as in the conventional method, so the cost is the same.

[Brief explanation of drawings]

Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing an embodiment of the present invention.
3 is a plan view showing another embodiment of the present invention, FIG. 4 is a plan view showing a conventional example, and FIG. 5 is a sectional view taken along line V-V in FIG. 4. It is. (1) is a transparent insulating substrate, (2) is a transparent pixel electrode, (3)
is the first gate wiring, (4) is the semiconductor layer, (5) is the source wiring, (6) is the drain electrode, (7) is the insulating film, (8) is the
) is a protective film, (9) is a thin film transistor, (10) is a second gate wiring, and (11) is a contact portion. Note that the same reference numerals in the figures indicate the same or corresponding parts. D

Claims (1)

[Claims] A plurality of pixel electrodes provided on an insulating substrate, a source wiring for inputting signals to the pixel electrodes, a thin film transistor for switching signals to the pixel electrodes, and a thin film transistor for transmitting signals for scanning the pixels. a first gate wiring disposed on the insulating substrate, which is input to the thin film transistor array substrate;
a second gate wiring formed on the insulating film of the first gate wiring excluding the intersection between the gate wiring and the source wiring at the same time as the source wiring; 1. A thin film transistor array substrate comprising a contact portion for connecting a wiring and a second gate wiring, and having a two-layer gate wiring.