JPH0430643A - Buffer control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a buffer control method used in information processing devices and the like.

[Prior Art] Conventionally, in data transfer between two points, when a data buffer is inserted in the middle of the transfer path in order to increase data bus usage efficiency, the data buffer circuit is a line such as a FIFO with asynchronous input and output. It was composed of two buffers, and data was output in the order in which it was input to the two data buffers.

In this case, when the data reception processing speed of the transfer destination is slow, data accumulates in the data buffer, and if an event occurs that requires urgent data transfer to the transfer destination,
The following methods were used.

(1) Wait until all the data in the buffer has been sent, and then transfer the data you want to transfer urgently.

(2) Clear all data in the buffer and then transfer the data you want to transfer urgently.

[Problem to be Solved by the Invention 1] However, in the above conventional example, either the urgency of data transfer is sacrificed or the data transfer that has already been transferred is sacrificed, and as a result, the efficiency of the system is not improved in either method. The disadvantage was that it significantly degraded the performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer control method that can efficiently transfer data even when data transfer requests with various degrees of urgency compete with each other.

[Means for Solving the Problems] The present invention has a plurality of data buffers for temporarily storing data during a data transfer route, sets a plurality of priorities for data transfer, and saves data already existing in one data buffer. If a data transfer with a higher priority than that data transfer occurs while outputting to the transfer destination.

The present invention is characterized in that the low priority data transfer is interrupted and the high priority data transfer is performed first using another data buffer.

[Function] In the present invention, priority is set for data transfer, and the order of transfer by multiple data buffers is switched based on the priority. Therefore, highly urgent data transfer can be performed without waiting time, and moreover, the buffer This can be done without discarding the data inside.

[Embodiment] FIG. 1 is a block diagram showing a buffer control circuit according to an embodiment of the present invention.

In this embodiment, the data width handled is 8 bits, and the buffer width is 256 bytes.

Output game) 1 is signal line 1 when signal [139 is “H”
Output the data of 02 as it is to the signal line 101 and set it to “L”
It is a three-state buffer that outputs a high impedance state when

The ring buffer 2 is composed of a plurality of latches and buffers, and latches and outputs data asynchronously. That is, at the falling edge of the signal line 109, the address indicated by the signal line 10g is latched at the 8th edge of the signal line 103.
The bit data is latched, and the 8-bit data latched in the latch at the address indicated by the signal line 107 is output to the signal line 102 when the signal line 106 is at "H".

Input gate 3 drives data on signal line 104.

The remaining amount counter 4 is a counter that indicates the remaining amount of data in the ring buffer z, and performs a decrement operation using a pulse on a signal line 111 and an increment operation using a pulse signal on a signal line 112, and transmits the contents to the signal line. Output to 105.

The output address counter 5 is a counter that indicates the output address of the ring buffer γ2, and performs an increment operation based on the pulse of the signal line 110, and transmits the contents to the signal line 1.
Output to 07.

The input address counter 6 is a counter that indicates the input address of the ring buffer 2, and performs an increment operation based on pulses on the signal line 113, and transfers the contents to the signal line 1.
Output to 08.

The arithmetic unit 7 determines whether the data on the @ line 105 is greater than 0 or
Alternatively, it is determined whether the data on the signal line 115 is greater than 0, and the result is output to the signal line 114.

The selector 8 transmits the state of the @ line 129 to the signal line 120.

Like the ring buffer 2, the ring buffer 9 is composed of a plurality of latches and buffers, and latches and outputs data asynchronously. That is, at the falling edge of the signal line 119, the address indicated by the signal line 118 is latched. signal l
The 8-bit data of lAlO3 is latched, and when the signal line 116 is at "H", the 8-bit data latched in the latch at the address indicated by the signal line 117 is output to the signal line 102.

The remaining amount counter 10 is similar to the remaining amount counter 4.

A counter indicating the remaining amount of data in the ring buffer 9 performs a decrement operation using a pulse on a signal line 121 and an increment operation using a pulse signal on a signal line 123, and outputs the contents to a signal line 115.

The output address counter 11 is the output address counter 5.
Similarly, it is an output carter indicating the output address of the ring buffer 9, performs an increment operation by the pulse of the 2nd signal line 122, and outputs the contents to the signal line 117.

Input address counter 12 is input address counter 6
Similarly, a counter indicating the input address of the ring buffer 9 performs an increment operation based on the pulse on the signal line 124, and outputs the contents to the signal line 118.

The output side control circuit 13 outputs the signal line 125 in response to a request (transfer request signal: LREQ) on the signal line 128 from the transfer destination.
A transfer permission signal (LACIC) is generated, and at the same time, data is output using the signal line 130 and either the signal line 106 or the signal line 118. Thereafter, each counter is incremented and decremented to control the output side.

A signal line 101 is a signal line of an 8-bit data bus connected to a transfer destination device.

Signal lines 125 and 126 are timing signal lines for DMA data transfer with the transfer destination.

Signal lines 127 and 128 are timing signal lines for DMA data transfer with the transfer source.

A signal line 129 is a signal line indicating the priority of data being transferred.

FIG. 2 is a block diagram showing the inside of the ring rose 2a2. Note that the ring buffers 2.9 have a common configuration, and only one ring buffer 2 will be described.

The latch circuit 21 is a collection of 8-bit data latches equipped with a select terminal and an enable terminal.
A 56-inch latch is used. In this latch circuit 21, the signal line 151 is set to "L", one latch is selected, and data is latched at the timing of the signal line 109.

The buffer circuit 22 is a collection of 256 8-bit three-state buffers, and outputs one latch data via a signal line 152.

The input address decoder 23 has an 8-bit signal line 108.
This is a decoder which sets one of the 256 signal lines 151 to "L".

The output address decoder 24 has an 8-bit signal line 107.
This is a decoder which sets one of the 256 signal lines 152 to "L".

FIG. 3 is a block diagram showing the system configuration of this embodiment. Note that this block diagram only shows data lines and DMA control among various signal lines for the sake of simplicity.

The laser beam printer 31 is a device that outputs the sent bit image onto paper.

The printer #J 11 H path 32 outputs horizontal and vertical synchronizing signals to the printer 31, and in synchronization with this, outputs data read from the memory 33 as a bit image.

The memory 33 is composed of a video memory and an image memory, and here a dual port memory is used to input and output data asynchronously.

The display 35 displays the video image data sent as is on a bitmap display.

The display control circuit 36 outputs horizontal and vertical synchronizing signals and display image data synchronized therewith to the display 35.

The keyboard 37 is an input device from the user of the system.

The buffer control circuit 38 is the circuit shown in FIG.
The PU 39 controls the entire system according to a program stored in the memory 41.

The hard disk 40 stores various data such as programs for operating the system, input data necessary for the system, and data created by the system.

The memory 41 is composed of a ROM that stores programs for controlling this system, and a RAM that is used to store programs and data and as a work area.

The DMA controller 42 is a controller that acquires bus control authority from the CPU 39 and controls the DMA II control signal when performing DMA data transfer.

FIG. 4 is a flowchart showing the operation on the input side of the buffer control circuit 38, and FIG. 5 is a flowchart showing the operation on the output side. The control operations shown in FIGS. 4 and 5 are simultaneously processed in parallel. Furthermore, each signal will be explained using positive logic.

next, ! 1I4FI! The operation of buffer input control will be explained using i and the first vl.

Here, the bus side of the signal line 101 shown in FIG. 1 will be described as a local side, and the signal line 104 side as a global side.

First, initial settings such as resetting each counter 6.12 and clearing the ring buffer 2.9 are performed (51).

Next, the remaining amount counter 4. ! A value of 0 is checked, and a check is made to see if there is free space in the buffer and to check the timing (52).

If the input preparation is OK, the process advances to S3 and the global side transfer request signal (GREQ: signal line 128) is set to H''.

Then, a transfer permission signal (GACK: @
Wait for line 127) to become "H" (34), and check the priority order (35).

If the priority is 0, data is input to the ring buffer 9 (37). First, the data is latched at the address indicated by the input address counter 12 at the falling edge of the GACK signal.

Next, the value of the input address buffer 12 is incremented by one, and the value of the remaining capacity counter lO is incremented by one.

Further, if the priority is 1 in S5, the process advances to S6, and the data is latched in the ring buffer 2. This is first GACK
At the falling edge of the M signal, the data is latched at the address indicated by the input address counter 6.0 The value of the input address buffer 6 is incremented by one, and the value of the remaining amount counter 4 is incremented by one.

After latching the data into the buffer in this way, check whether you are ready to read the primary data in the same manner as in S2 (5B), and if it is ready,
The process advances to step 4 and waits for the transfer permission signal GACK to become "H".

If the input is not ready in S8, the transfer request signal (GREQ) is set to "L" and the process proceeds to S2, where it waits until the input is ready.

Data input to the buffer is controlled by repeating such operations.

Next, the operation of buffer output control will be explained using FIG. 5 and FIG. 1.

First, each counter 4.5, 10.11 is reset (521), and the local side transfer request signal (LREQ:
It waits for @line 126) to become "H" (S22).

When a transfer request comes, it is checked whether the value of the remaining capacity counter 10 of the buffer 9 containing data with a high transfer priority is 1 or more (323), and if this value is 1 or more, Output data from buffer 9 (33
0).

Furthermore, if the value of the remaining amount counter lO is 0 in S23,
Check whether the value of remaining amount counter 4 is 1 or more (S24
), and if this value is 1 or more, data is output from buffer 2 (525).

Note that if the value of the remaining amount counter 4 is 0, there is no data to be sent, so the process returns to 522.

Further, in the above 325, the latch data of the ring buffer 2 indicated by the address of the output address counter 5 is transferred to the signal line 1.
The signal is output onto the data line of the signal line 102 under the control of the signal line 06. Then, a transfer permission signal (LACK: @
Line 125) is set to "H" 526), output gate l is opened via signal line 130, and signal line 101
Output data onto the local data bus (327)
Then, it waits for timing (328), sets the transfer permission signal to "L", closes the output gate (1) via the signal line 130, and sets the data output of the ring buffer 2 to a high impedance state via the signal line 106.

Next, the value of the output address counter 5 is incremented by 1, and the value of the remaining capacity counter 4 is decremented by 1 (
S29).

Also, if the remaining amount counter lO is 1 or more in 523 above, 530
, the latch data of the ring buffer 9 indicated by the address of the output address counter 11 is transferred to the signal line 11.
8, the signal is output onto the data line of the signal line 102.

Then, set the transfer permission signal to the local side (LACK=signal line 125) to “H” (331), open the output gate via the signal line 130, and transfer the data onto the local data bus on the signal line 101. Output (S32).

Then, it waits for timing (S33), sets the transfer permission signal to "L", and outputs the output gate l via the signal line 130.
is closed, and the data output of the ring buffer 9 is brought into a high impedance state via the signal line 116.

Next, the value of the output address counter 11 is incremented by one, and the value of the remaining amount counter 10 is decremented by one.

By repeating such operations, the data output of the buffer is controlled.

FIG. 6 is a timing chart showing the patterns of each of the above signals.

The above operation will be explained in detail using this figure.

First, in data input, a transfer request signal G is sent to the global side.
Output REQ and wait for transfer permission signal GACK to be output. When GACK@4 becomes “H”, signal line 129
determines the priority of the buffer and selects a buffer to latch the data.

In this case, since the priority is 1, data is latched in ring buffer 2 by signal line 109, and data is latched by signal line 112, 11.
3, the values of the remaining amount counter 4 and the input counter 6 are incremented.

Also, when the priority is 0, data is latched in the ring buffer 9 by the signal line 119, and the data is latched by the signal line 123.124.
Then, the values of the remaining amount counter lO and the input counter 12 are incremented.

In addition, for data output, a transfer request signal L is sent from the local side.
When REQ is received, the value of the remaining amount counter 1O14 is checked and the data is output. In this case, since there is no data in the buffer 9 at first, the data is output from the buffer 2 through the signal line 106, and the output address counter 5 is incremented.
Decrement remaining amount counter 4.

At the next timing, the value of the remaining amount counter 4.10 is checked again, and since there is data in the buffer 9, the data in the buffer 9 is outputted via the signal line 116.

Then, the output address counter 11 is incremented, and the remaining amount counter IO is decremented. In this way, Z outputs data one after another.

Moreover, inside the ring buffer 2, in FIG.
One latch is selected by the decoder 23 from the address indicated by the input address counter 6, and data is latched at the falling signal of the signal line 109. Also, the decoder 24 outputs 1 from the address indicated by the output address counter 5.
By selecting two latches and controlling the three-state buffer 22, data is output onto the data bus 102 when the signal line 106 is in the "H" state.

Note that the internal operation of the ring buffer 9 is performed in the same manner.

FIG. 7 is a flowchart showing the operation of the system configuration shown in FIG.

This embodiment is an example in which the display on the display 35 and the printing on the printer 31 are performed using the CRTC 34.

First, determine whether it is necessary to rewrite the display on the CRT 31 (351), and if it is necessary to rewrite the CRT 31,
(: The PU 39 creates a command for the CHTC 34 for rewriting the display (S52).

Then, write this command to the memory 41 (S53
), it is confirmed that all display rewriting commands have been created and written to the memory (S54).

Next, set the data transfer priority to 0, which is the higher priority, and set it to 555.
), after setting the transfer data length, transfer source start address, and transfer destination device in each register of the DMA controller 42 (S56), the DMA controller 42 is enabled for DMA transfer (S57).
).

Then, data is actually transferred between the buffer control circuit 38 and the memory 41 (35g).

If it is determined in S51 that the CRT is not rewritten, the first step is to determine whether work such as document creation or editing has occurred (S59), and whether work such as document creation or editing has occurred. If so, each process is performed in 560 and the process returns to S51.

In addition, when document printing processing occurs (S61), the data transfer priority is set to 1 (562), and the DMA
Transfer data length to each register of the controller 42,
The transfer source start address and the transfer destination device are respectively set (S63), and the DMA transfer of the DMA controller 42 is enabled (364), and the expansion command for the document data actually created in the memory 41 is sent to the buffer control circuit. Transfer data to 38 (S65)
.

By repeating this process, the print command data is pooled in the buffer, and the print document is stored in the memory 3.
2, the CRT 31 can be controlled according to the priority order.

Further, FIG. 8 is a block diagram showing a buffer control circuit according to another embodiment of the present invention.

In the figure, in the latch circuit 15, a signal line 131 is a signal line indicating the end of transfer from the global side, and a signal line 133 is a data latch timing signal line,
Furthermore, the signal line 132 is a signal line that outputs the latched value to the input side control circuit.

In this embodiment, a priority is written in the first data of the data transfer, and this data is latched by the latch circuit 15 and held as the priority during the transfer cycle, that is, until the transfer end signal arrives.

FIG. 189 is a timing chart showing patterns of each signal in this embodiment.

First, the first input data (signal line 104) is transferred to the signal line 13.
3 is used to hold it as a priority in the latch circuit 15, and data is input with the same priority until a transfer end signal is received on the signal line 131. Note that the priority is set to 1 here. In this way, the priority during the transfer cycle is indicated by the first data, and the content thereof is indicated by the signal line 132.

Thereafter, by operating in the same manner as in the embodiment described above, data buffer control is performed to output data transfer with a higher priority first.

[Effects of the Invention] As explained above, according to the present invention, priority is set for data transfer, and the order of transfer by a plurality of data buffers is switched based on the priority.
Even if data is already accumulated in the buffer, it is possible to transfer highly urgent data without waiting time and without discarding the data in the buffer.
System efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a buffer control circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing the inside of the ring buffer in the same embodiment. FIG. 3 is a block diagram showing the system configuration in the same embodiment. FIG. 4 is a flowchart showing the operation on the input side of the buffer control circuit in the same embodiment. 5th rgJ is a flowchart showing the operation on the output side of the buffer control circuit in the same embodiment. FIG. 6 is a timing chart showing patterns of each signal in the same embodiment. FIG. 7 is a flowchart showing the operation of the system configuration shown in FIG. FIG. 8 is a block diagram showing a buffer control circuit according to another embodiment of the present invention. FIG. 9 is a timing chart showing patterns of each signal in this embodiment. 1...Output gate, 2.9...Ring buffer. 3... Input gate, 4.10... Remaining amount counter, 5.11... Output address counter, 6.12...
Input address counter. 7... Player, 8... Selector, 13... Output side control circuit, 14... Input side control circuit, 15.21... Latch circuit, 22... Buffer circuit. 23... Input address decoder, 24... Output address decoder'.

Claims (4)

[Claims] (1) It has multiple data buffers that temporarily store data during the data transfer route, sets multiple priorities for data transfer, and outputs the data that already exists in one data buffer to the transfer destination. Sometimes, if a data transfer with a higher priority than that data transfer occurs, the lower priority data transfer is interrupted and the higher priority data transfer is performed first using another data buffer. buffer control method. (2) A buffer control method according to claim (1), characterized in that the priority order is indicated by the state of a signal line. (3) A buffer control method according to claim (1), characterized in that the priority order is indicated in the first data portion of data transfer. (4) A buffer control method according to claim (1), characterized in that the priority order is indicated by a part of the transfer data.