JPH0430751B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a solid-state imaging device, and particularly relates to a gate storage type static induction transistor (hereinafter abbreviated as SIT) type related to a simplified self-aligned planar process. The present invention relates to a method of manufacturing an image sensor.

[Description of Prior Art] Conventionally, there are CCD type and MOS type solid-state imaging devices that have been put into practical use. Recently, there is a SIT type image sensor proposed by the present inventor (IEEE
Trans on Electron Devices Vol.ED−26, No.12
(Dec.1979) PP.1970-1977).

The present inventors have also made various basic applications in matrix operation as applications in conjunction with the proposal of the basic structure. Regarding the specific manufacturing method, please refer to Japanese Patent Application No. 57-218589 and Japanese Patent Application No. 57-218589.
The invention is disclosed in No. 218590 and Japanese Patent Application No. 57-218591. The above-mentioned Japanese Patent Application No. 57-218589 relates to a method for manufacturing a SIT image sensor having the simplest planar structure, and FIG. 2 shows the main parts of the manufacturing process. The prior art will be explained below based on the drawings. In Fig. 2, (A) After forming an n ⁺ buried layer 2 on an n ⁺ substrate or a p ^- substrate 1, high resistance n ^- epitaxial growth 3 (this can be any of n ^- , p ^- , i). good)
Then, boron B is deposited and driven into the field oxide film 7 and control gate 6 portions by ion implantation or diffusion.

(B) A window is opened in a predetermined portion of the source 5 through a mask alignment process, and phosphorus or As-doped polysilicon 8 or non-doped polysilicon 8 is coated with CVD (Chemical Vapor
Phosphorus P deposited using
Or do a drive-in with arsenic doping.

(C) After etching the polysilicon 8 in the source electrode portion and wiring portion by mask alignment, a PSG (Phospho-Silicate Glass) film 9 is formed by CVD.

(D) After etching and removing the field oxide film 7 and PSG film 9 above the control gate 6 portion by mask alignment, the nitride film 10 is removed.
Performs CVD and transparent electrode SnO ₂ film 11 and stores MIS in the control gate 6 part.
(Metal Insulator Semiconductor structure)
form a capacitor.

(E) Control gate 6 section and wiring section
Only the SnO ₂ film 11 is left by the mask alignment and etching process, and a contact hole is opened to the shielding gate 4 portion. Finally Al
Perform vapor deposition and etching for wiring. The Al electrode 12 is in contact with the electrode SnO ₂ film 11 . The Al electrode 13 is an Al electrode for contact with the shielding gate 4.

As is clear from the above explanation, the patent application
The manufacturing method disclosed in No. 218589 requires seven masks excluding passivation, and also requires 5 masks for n ⁺ source and 4 for p ⁺ gate.
The six portions are each formed using separate masks in a mask alignment process. For this manufacturing method, the present inventors use a single mask to define the n ⁺ source 5 portion and the p ⁺ source 4 and 6 portions.
We proposed a self-alignment process for SIT image sensors and disclosed it in Japanese Patent Application No. 1983-218590. The final cross-sectional structure is shown in FIG.

Next, the manufacturing process of the device shown in FIG. 3 will be briefly described. After forming an n ⁺ buried layer 2 on an n ⁺ substrate or a p ^- substrate 1, after n ^- high resistance epitaxial growth 3 (this can be any of n ^- , p ^- , i), LOCOS (LOCaliged Oxidation
of Silicon) technology to simultaneously define the regions that will become the source 5 portion and the gates 4 and 6 portions of the SIT. That is, the source 5 portion of SIT, the gate 4,
The area other than the area that should become part 6 is covered with a thick field oxide film 7 made of LOCOS. After the mask alignment process, the Si ₃ N ₄ film on the regions to become the gates 4 and 6 is removed, and the gates 4 and 6 of the SIT are formed by boron B ion implantation and heat treatment.

Next, after a mask alignment process, the Si ₃ N ₄ film and SiO ₂ film on the region that is to become the source 5 portion are removed, n ⁺ doped polysilicon 8 is formed on the entire surface by CVD technology, and n + doped polysilicon 8 is formed by a heat treatment process. ⁺ source 5
Form a diffusion region. The n ⁺ doped polysilicon 8 is etched to form a wiring portion. next,
After growing the PSG film 9 by CVD, the SiO ₂ film on the control gate 6 region is removed by a mask alignment process. After Si ₃ N ₄ 10 of a desired thickness is formed on the entire surface by CVD technology, a SnO ₂ film 11 is further grown by CVD. An MIS structure is formed on the control gate 6 using the SnO ₂ 11/Si ₃ N ₄ 10/Si(p ⁺ )6 structure. After etching the SiO ₂ film 11, a contact hole is opened to the shielding gate 4 portion, and Al vapor deposition and sintering is performed. Excluding passivation, seven masks are required up to the Al electrode wirings 12 and 13.

In the manufacturing process of the SIT image sensor pixel having the structure shown in FIG. 3, the positions of the source 5 and gates 4 and 6 are defined by the first mask, so that
Compared to the manufacturing method shown in FIG. 2, variations between the source and gate can be suppressed. However, the second
In the method shown in the figure and the method shown in Fig. 3, the number of required masks is 7. In the method shown in Fig. 3, the positions of the gates 4, 6 and source 5 of the SIT are defined by the first mask. However, gate 4,
This is because the diffusion steps of 6 and the source 5 are performed using separate masks, and the same mask is used later when etching the SnO ₂ film 11 on the control gate 6, so the total number of masks is 7. It has become one piece. In this case, since the formation of the gates 4 and 6 and the formation of the source 5 are performed in separate processing steps, there is a drawback that the structure is susceptible to variations in characteristics.

The present inventors have further disclosed another method for manufacturing an SIT image sensor in Japanese Patent Application No. 57-218591. The cross-sectional shape of the final device is shown in FIGS. 4A and 4B. The feature of the manufacturing method shown in this figure is that the shielding gate 4 portion is formed deeply.
LOCOS or plasma etching + LOCOS
Figure 4A shows an example in which p ⁺ gates 4 and 6 are deeply diffused into the shielding gate 4 and control gate 6 parts using LOCOS technology, and the n ⁺ source 5 The location of the region is determined by mask alignment. That is,
It is not self-aligned. In the structure shown in FIG. 4B, the shielding gate 4 portion is plasma etched and
The p ⁺ gate 4 diffusion is formed deeply using LOCOS technology, and the positioning of the p ⁺ control gate 6 diffusion and the positioning of the n ⁺ source 5 portion diffusion are performed by mask alignment using separate masks.

In FIG. 4A, the total number of masks is seven, excluding passivation, and in FIG. 4B, it is seven to eight.

As explained above, there are four methods of manufacturing SIT image sensors that have been disclosed and proposed by the present inventors. In the manufacturing method shown in Figure 2, the gate diffusion and source diffusion of the SIT are positioned through a mask alignment process using separate masks, so when arranging a large number of cells in a matrix, the sensitivity characteristics between pixels There are drawbacks that greatly affect variation. However, the final structure of the device is planarized, which is advantageous in terms of increasing light reception efficiency.

In the manufacturing method explained in FIG. 3, the positions of the gate and source of the SIT are defined by the first mask, so dimensional variations are much suppressed compared to the method shown in FIG. ,
A thick oxide film created by the LOCOS process exists between the gate and source of the SIT, resulting in poor light transmission to the SIT channel. In addition, the device surface has an uneven shape due to the effect of the oxide film caused by LOCOS, and light is scattered due to the uneven shape, resulting in a structure that makes it difficult to effectively introduce light into the device. Furthermore, since gate diffusion and source diffusion are ultimately performed using separate mask alignment, the total number of masks is 7, which is the same as in the case of FIG. 2.

In the manufacturing method explained in FIG. 4A,
At the same time as the oxidation of LOCOS technology, p ⁺ gate diffusion is performed under the thick oxide film of LOCOS, so the light-receiving surface is uneven.At the same time, the source region is positioned by mask alignment, and the source diffusion region The variations in the positions of the elements greatly affect the variations in the characteristics of the final arrayed devices.

Furthermore, in the SIT image sensor manufacturing method explained in FIG. 4B, since the control gate diffusion and source diffusion positioning is performed by a mask alignment process, variations in the channel width dimension and the dimension between the source and the gate can occur. If a plurality of cells are arranged in a matrix, the characteristics of each pixel will vary greatly.

As explained above, in the prior art method shown in FIGS. 2 and 4A and B previously disclosed by the present inventors, the gate and source positions are determined separately in the mask alignment process, so there are multiple When individual cells were integrated, there was a problem in that the characteristics of each pixel varied.

Further, in the method shown in FIG. 3, the device surface becomes uneven and source diffusion and gate diffusion are performed separately, resulting in variations and poor light absorption efficiency.

Furthermore, when considering the total number of masks, the preceding examples of FIGS. 2, 3, and 4 A and B are all 7 to 8 masks, and depending on the combination with the scanning circuit, this number may vary depending on the combination with the scanning circuit. It was inevitable that the number would be higher than this.

In addition, devices realized using conventional manufacturing methods have uneven surfaces due to LOCOS,
Because it is not a self-aligning process, variations in the sensitivity characteristics of each pixel tend to occur, making it unsuitable for large-capacity image sensors (up to 500 x 700 pixels), where uniformity is particularly important. .

[Object of the invention] The present invention has the following features except for the above-mentioned disadvantages.
It is an object of the present invention to provide a novel method for manufacturing an image sensor that has uniform sensitivity characteristics of each element and has good light absorption efficiency.

[Summary of the Invention] Therefore, the present invention includes the steps of forming a buried layer in each transistor formation region on a semiconductor substrate, performing high resistance epitaxial growth, and then forming a field oxide film; A mask alignment process is used to open a window in a portion that separates each transistor region, and an impurity is implanted or diffused. A second mask alignment process is used to open a window in each of the regions where each transistor is to be formed. After drying, a dry thermal oxide film is formed on the entire surface, and then a doped polysilicon layer doped with impurities is formed on the entire surface, and a third mask alignment step is performed to form the gate region of the scanning circuit transistor and its wiring. After removing the other doped polysilicon layers while leaving the doped polysilicon layer that is to become a part, the dry thermal oxide film is removed using the remaining doped polysilicon layer as a mask, and then the polymer material is applied to the entire surface. Through the film coating step and the fourth mask alignment step, the polymer material film on the intended source region of the electrostatic induction transistor is left and the other polymer material film is removed to form the shielding gate and control layer. a step of doping impurities into the intended gate region and the intended source and drain regions of the scanning circuit transistor, and then forming a nitride film over the entire surface; and a polymeric material film in the intended source region of the static induction transistor. is removed and doped with impurities to form a doped polysilicon layer, and in a fifth mask alignment step, an insulating film is formed over the entire surface except for the polysilicon layer in the source region and control gate region of the static induction transistor. and a sixth mask alignment step to open contact holes to the shielding region and the source and drain regions of the scanning circuit transistor, and then form electrodes. It is characterized by the fact that it is made to do so.

[Embodiment of the Invention] FIGS. 1A to 1F show each manufacturing process of an image sensor manufacturing method according to an embodiment of the invention. below,
Each manufacturing process A to F will be explained in order.

(A) Both (111) and (100) plane orientations of the substrate are good.
A common buried layer 2 is formed on the p ^- substrate by diffusion or ion implantation of As or Sb, etc. in a region to become the sensor area of the SIT image sensor and a region to constitute the peripheral scanning circuit. In the buried layer 2, a common electrode is provided around the sensor area or at a predetermined portion. Although this electrode portion is not shown in FIG. 1A, it becomes a common drain region of multiple matrices of the SIT image sensor. The reason why such a buried layer 2 is formed is that the driving and scanning circuit for the matrix of the pixel portion of the SIT image sensor is to be formed on the same substrate.

Next, the high resistance epitaxial growth layer 3 is
Grow about 3 μm to 10 μm. The conductivity type of this epitaxial growth layer 3 may be either n ^- or p ^- . Further, it may be an i-layer. Next, all over
Perform wet oxidation. The thickness of this field oxide film 7 is approximately 5000 Å to 8000 Å. After that, in the first mask alignment process, etching is performed to open a window for forming a junction isolation to separate the SIT image sensor pixel part and the scanning circuit part on the surface, and As or P ions are implanted or diffused into the entire surface. This forms a junction isolation region 14.

(B) Through the second mask alignment process, windows are simultaneously opened in the shielding gate 4 portion, control gate 6 portion, source 5 portion, and scanning circuit transistor portion of the SIT image sensor, which will be formed in FIG. 1D described later. Let's do it. Next, an oxide film 19 is formed over the entire surface by dry oxidation. The thickness of the oxide film 19 is approximately 300 Å to 800 Å. Furthermore, a boron doped polysilicon layer 2 is formed on the entire surface.
3 is formed by CVD etc. The thickness of this polysilicon layer 23 is approximately 3000 Å to 4000 Å.

(C) In a third mask alignment step, the doped polysilicon layer 23 is removed by etching, leaving the doped polysilicon layer 23 on the gate region of the scanning circuit transistor. Furthermore,
Using this remaining doped polysilicon layer 23 as a mask, the dry oxide film 8 is removed by etching to remove the control gate 6 portion and shielding gate 4 of the SIT image sensor.
The Si surface where each region is to be formed is exposed: the source 5 portion, the source 21 portion, and the drain 22 portion of the scanning circuit transistor.

(D) Next, the entire surface is made of polymeric material (polymide, etc.)
The film 16 is applied, and a fourth mask alignment step is performed to leave the polymer material film 16 in the source 5 portion of the SIT image sensor and to remove the other polymer material film 16.
is removed by etching. Thereafter, boron ion implantation is performed over the entire surface to deposit the shielding gate 4 and control gate 6 regions of the SIT image sensor and the source 21 and drain 22 regions of the scanning circuit transistor. Further, a nitride film 10 is formed on the entire surface by plasma CVD or the like. The surface concentration of boron deposited is approximately 5×10 ¹⁹ cm ⁻³ . The applied thickness of the polymer material film 16 is approximately 1.2 μm to 1.8 μm. Furthermore, the thickness of the nitride film 10 formed by plasma CVD is
It is about 500 Å to 1000 Å.

Here, the polymeric material film 16 is used because it can be easily formed, that is, it can function sufficiently as a mask for ion implantation just by applying it and heating it to 300°C to 400°C, and is comparatively more effective than a resist film. It can withstand temperatures of, for example, 400°C to 500°C. Therefore, by subsequently forming the nitride film 10 using plasma CVD technology or the like, it is possible to easily provide a structure that enables the lift-off method.

(E) Next, the polymer material film 16 is removed by etching, and the nitride film 10 formed thereon is simultaneously removed by a lift-off method to expose the Si surface of the source 5 portion of the SIT image sensor. . Thereafter, the boron ion implantation heat treatment is performed to form the shielding gate 4 region and control gate 6 region of the SIT image sensor, as well as the source 21 region and drain 22 region of the scanning circuit transistor. Furthermore, a doped polysilicon layer 20 of As or P is formed on the entire surface.
is formed by CVD or the like, and the polysilicon layer 20 is formed by a fifth mask alignment process, leaving the polysilicon layer 20 on the source 5 region and control gate 6 region of the SIT image sensor.
is removed by etching. Thereafter, a PSG film 15 is further formed on the entire surface using a technique such as CVD.
SIT image sensor shielding gate 4
The surface concentration of boron in the control gate 6 region, the source 21 region, and the drain 22 region of the scanning circuit transistor is about 1×10 ¹⁹ cm. Also, each of these 4, 6, 21, 22
The diffusion depth of the region is approximately 1.5 μm to 2.5 μm. The thickness of the doped polysilicon layer 20 is 3000 Å ~
It is about 4000Å. The thickness of PSG film 15 is 3000
It is about Å. The doped polysilicon layer 20 left on the control gate 6 region of the SIT image sensor may be left at about 1/3 of the area above the control gate region in order to improve the efficiency of light use.

(F) Next, in a sixth mask alignment step, contact holes are opened to the shielding gate 4 region and the source 21 region and drain 22 region of the scanning circuit transistor. Furthermore, an Al electrode is formed on the entire surface by vapor deposition, leaving an Al wiring portion 17 for contact with a predetermined shielding gate 4 and an Al wiring portion 18 for contacting with the source 21 and drain 22 of the scanning circuit transistor. Etching is performed (seventh mask alignment step). Furthermore, after sintering, a final passivation process such as CVD growth of a Si ₃ N ₄ film is performed.

The SIT image sensor of this example is manufactured through the above-mentioned steps, and its operation is similar to that of the conventional example.
- The video signal is read out using the Y address method.

According to the image sensor manufacturing method described above, the positions of the source 5 region and the gate 4 and 6 regions of each pixel of the SIT image sensor are simultaneously determined by the second mask alignment step, and E
As shown in FIG. 3, the gate diffusion regions 4 and 6 are formed by only one heat treatment step among all the steps. Therefore, the dimensions of the channel of the SIT part that constitute each pixel and the distance between the gate 4 region and the source 5 region are all made uniform, and the variation in output characteristics with respect to the received light intensity between each pixel can be almost ignored. It can be suppressed. In addition, since the formation of the source 5 region is performed simultaneously with the formation of the doped polysilicon layer 20, the diffusion depth of the source 5 region can be made extremely shallow, and since the diffusion depth is approximately 0.1 μm, the diffusion depth of the gate 4 and 6 regions is It can also be formed to remain longer than before. Therefore, an improvement in short wavelength sensitivity can be obtained compared to the conventional one.

Furthermore, if we consider forming the source 5 region with a short key electrode such as Pt instead of the doped polysilicon layer 20 shown in FIG. The number of sheets can be reduced by one, and a simpler device process becomes possible.

In addition, the Si surfaces of the gate 4 and 6 diffusion regions and the source 5 diffusion region of each pixel are on the same plane and are flattened, which reduces scattering due to unevenness on the semiconductor surface when receiving light compared to conventional manufacturing methods. The light absorption rate decreases and the light absorption rate improves.

In addition, in the above embodiment, the shielding gate 4
Although a gate accumulation method for an SIT image sensor having a control gate 6 and a divided gate has been established, an insulator separation may be used instead of the shielding gate 4. In that case, only the control gate 6 region becomes the gate region of the SIT, so the SIT structure is a conventional SIT structure in which the source 5 region is surrounded by the control gate 6 region. However, it is clear that the same manufacturing process as the present invention can be applied, and the positioning of the source 5 diffusion region and the gate 6 diffusion region is performed using the same mask.
This makes it possible to provide an image sensor with suppressed variations in characteristics.

In addition, in the above embodiment, a P channel transistor was used as the scanning circuit transistor, but
It is clear that an n-channel or even CMOS configuration is possible by simply adding one well process. Furthermore, it goes without saying that the conductivity types of each part shown in FIG. 1 may be completely opposite.

[Effects of the Invention] As described above, according to the present invention, when the distance between the gate portion and the source portion of the image sensor cell and the dimension of the channel are determined by the same mask, and a plurality of image sensor cells are arranged in a line or matrix, To,
An image sensor with uniform sensitivity characteristics of each pixel is obtained, and since the device is flattened after manufacturing, it has good light absorption efficiency, making it an ideal image sensor especially for manufacturing large-capacity area sensors. A manufacturing method is obtained.

[Brief explanation of drawings]

Figures 1A to 1F are explanatory diagrams of the SIT image sensor manufacturing process according to an embodiment of the present invention, and Figure 2A
~E is an explanatory diagram of the manufacturing process as a conventional example of a gate accumulation type SIT image sensor, and Figures 3 and 4 A and B both use a manufacturing process as another conventional example of a gate accumulation type SIT image sensor. FIG. 2 is a cross-sectional view of the device structure. 1... p ^-substrate , 2... n ⁺ buried layer, 3... high resistance epitaxial growth layer, 4... shielding gate, 5, 21... source, 6... control gate, 7... field oxide film, 10... nitride film, 14
...Junction isolation region, 15...PSG film, 16...Polymer material film, 17, 18...Al contact electrode, 19
...Dry oxide film, 20, 23...Doped polysilicon layer, 22...Drain.

Claims (1)

[Claims] 1. In a method for manufacturing a solid-state imaging device in which a plurality of electrostatic induction transistors for photoelectric conversion and transistors for a scanning circuit are formed on a semiconductor substrate, a buried layer is formed in a region where each transistor is to be formed on the substrate, and a high resistance After epitaxial growth, a step of forming a field oxide film and a first step are performed.
A second mask alignment step is used to open a window in a portion separating each transistor region and doping with an impurity, and a second mask alignment step is used to open a window in each region where each transistor is to be formed. Afterwards, a dry thermal oxide film is formed on the entire surface,
Thereafter, a step of forming a doped polysilicon layer doped with impurities over the entire surface and a third mask alignment step leave the doped polysilicon layer that will become the gate region of the scanning circuit transistor and its wiring portion, and After removing the doped polysilicon layer, using the remaining doped polysilicon layer as a mask, the dry thermal oxide film is removed, and a polymer material film is further applied on the entire surface, and a fourth mask alignment step. by leaving a polymer material film on the intended source region of the electrostatic induction transistor,
a step of removing another polymeric material film, doping impurities into portions intended for shielding gate and control gate regions and portions intended for source and drain regions of the scanning circuit transistor, and then forming a nitride film over the entire surface; A doped polysilicon layer doped with impurities is formed by removing a polymer material film in a portion where the source region of the static induction transistor is to be formed, and a fifth mask alignment step is performed to form a doped polysilicon layer doped with impurities, and a fifth mask alignment step is performed to form a source region and a control region of the static induction transistor. A step of forming an insulating film on the entire surface except for the polysyncon layer in the gate region, and a sixth step.
A method for manufacturing a solid-state imaging device, comprising: opening contact holes in a shielding region and source and drain regions of a scanning circuit transistor through a mask alignment step, and then forming electrodes. .