JPH0430754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit composed of a floating gate nonvolatile semiconductor memory having a MOS structure.

FIG. 1 shows a cross-sectional view of a general conventional nonvolatile semiconductor memory having a selection gate electrode and a floating gate electrode.

An N ⁺ type source region 2 and a drain region 3 are provided at intervals on the surface of a P-type semiconductor substrate 1, and a selection gate electrode 5 and an insulating film 6 are formed with an insulating film 4 interposed therebetween.
A floating gate electrode 7 is formed through the gate electrode. The selection gate electrode 5 and the floating gate electrode 7 are connected via an insulating film 8. The control gate electrode 9 is strongly capacitively coupled to the floating gate electrode 7 via the insulating film 10, and controls the potential of the floating gate electrode 7.

Memory writing (electron injection into the floating gate electrode 7) can be performed as follows. The first channel L 1 under the selection gate electrode ₄ and the second channel L ₂ under the insulating film 8 are inverted to the extent that current flows between the source and drain regions, and the second channel L 1 under the floating gate electrode 7 is inverted to the extent that current flows between the source and drain regions. If the third channel _L3 is strongly inverted, a surface potential gap with a magnitude equal to the drain voltage is formed between the second channel _L2 and the third channel _L3 . Therefore, if the size of the potential gap is larger than the potential barrier between the substrate 1 and the insulating film 6, some of the electrons flowing out from the source region 2 can enter the floating gate electrode 7. When electrons enter the floating gate electrode 7, a second channel
Since the channel conductance of L ₂ or the third channel L ₃ is low, this memorial can be read out.

In the case of a memory cell as shown in FIG. 1, since the threshold voltage of the second channel region _L2 is the highest,
The surface potential has a shape as shown in Figure 2. That is, the second channel _L2 limits the drain current. Therefore, this drain current ID is
is a function of the surface potential difference ΔφS between the channel L ₁ and the second channel L ₂ .

ID=f(△φS) (1) △φS is influenced by the voltage _VSG of the selection gate electrode 5 and the voltage _VF of the floating gate electrode 7, so it can be written as follows.

ID=f(V _SG , V _F ) ...(2) Since the voltage V _F of the floating gate electrode 7 is a function of the voltage V _CG of the control gate electrode 9 and the charge density Q _F entering the floating gate electrode 7. , equation (2) can be rewritten as equation (3).

ID=f(V _SG , V _CG , Q _F ) (3) FIG. 3 shows a write/read circuit used in the memory cell shown in FIG. 1. In FIG. 3, a power supply voltage V _DD is applied to the selection gate electrode 5 during writing and reading. Therefore, as the power supply voltage fluctuates, the channel conductance of the memory cell fluctuates due to equation (3), making stable reading and writing difficult.

The present invention has been made to overcome the above-mentioned conventional drawbacks, and provides a semiconductor integrated circuit that enables stable writing and reading.

FIG. 4 shows a semiconductor integrated circuit according to an embodiment of the present invention.

A constant voltage circuit 11 is provided within the semiconductor integrated circuit, and its output is connected to a selection gate electrode. In other words, a constant voltage is maintained regardless of fluctuations in the power supply voltage _VDD .
Since Vref ₁ is applied to the common gate electrode, stable writing and reading are possible. If another voltage Vref ₂ can be applied to the control gate electrode, the memory cell will be able to write and read more stably.

FIG. 5 is a diagram of a constant voltage circuit used in the semiconductor integrated circuit of the present invention. A constant current source is connected in series to a MOS transistor whose gate electrodes are a selection gate electrode and a floating gate electrode. Although the MOS transistor in this constant voltage circuit has a structure similar to that of a memory cell, the second gate electrode relative to the floating gate electrode has a structure that allows a voltage V _G to be applied directly from the outside. By connecting the first gate electrode corresponding to the selection gate electrode and the drain region, a constant voltage output can be taken out from the drain region. V _G applied to the second gate electrode may be a power supply voltage or another constant voltage.

FIG. 6 is a graph showing the operating principle of the constant voltage circuit shown in FIG. Curve A shows the current/voltage characteristics of a MOS transistor, and curves B and C show the characteristics of a constant current source. The current flowing through the MOS transistor and the constant current source is equal. Therefore, the voltage at which each curve intersects becomes a constant voltage output. That is, when this constant voltage is applied to the selection gate electrode of the memory cell, a current approximately equal to that of the constant current source flows through the memory cell. For example, when the current value of the constant current source is Vref ₁ , the constant voltage output is Vref ₁ (the intersection of curve A and curve B). Even if the power supply voltage V _DD fluctuates, the current value Iref ₁ of the constant current source remains constant, so the constant voltage output Vref ₁ is also kept constant. The voltage V _G applied to the second gate of the MOS transistor is selected depending on the operating state of the memory cell. That is, if the floating gate electrode is negatively charged,
Make it the same potential as the source region of the MOS transistor,
On the other hand, if it is positively charged, it is better to make it the same potential as V _DD .

As explained above, according to the semiconductor integrated circuit of the present invention, since a constant voltage is applied to the selection gate electrode, it is possible to stably read information from a memory cell and stably write information to a memory cell. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional general nonvolatile semiconductor memory, and FIG. 2 is a surface potential diagram of the nonvolatile semiconductor memory cell of FIG. 1. FIG. 3 is a read/write circuit diagram of the general memory cell used in FIG. 1. FIG. 4 is a read/write circuit diagram of the memory cell of the present invention, and FIG. 5 is a constant voltage circuit diagram used in the semiconductor integrated circuit of the present invention. FIG. 6 is a characteristic diagram showing the operating principle of the constant voltage circuit of FIG. 5. 1... Semiconductor region, 2... Source region, 3...
Drain region, 4, 6, 8, 10... Insulating film, 5
...Selection gate electrode, 7...Floating gate electrode, 9
...Control gate electrode.

Claims (1)

[Claims] 1. A memory cell comprising at least a nonvolatile semiconductor memory cell in which a selection gate electrode and a floating gate electrode are formed on a channel region between source and drain regions via an insulating film, and a constant voltage circuit. and a constant voltage output of the constant voltage circuit is applied to the selection gate electrode when reading or writing information in the nonvolatile semiconductor memory. 2. When writing information into the non-volatile semiconductor memory, part of the charge flowing out from the source region is injected from a vicinity between the selection gate electrode and the floating gate electrode. The semiconductor integrated circuit according to item 1. 3. A MOS transistor in which the constant voltage is connected in series with a first gate electrode corresponding to the selection gate electrode and a second gate electrode corresponding to the floating gate electrode via the insulating film;
and a constant current source connected in series to the drain region of the MOS transistor, and by connecting the first gate electrode and the drain region of the MOS transistor, the voltage of the first gate electrode is increased. The semiconductor integrated circuit according to claim 1 or 2, characterized in that the voltage is constant.