JPH0430773B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data conversion method used when data is recorded at high density on a recording medium or transmitted in a band-limited transmission system. Various modulation methods have been proposed and put into practical use for recording or transmitting data at high density on recording media such as magnetic tapes, magnetic disks, and even optical disks. These various modulation methods, especially those that can record at higher density than other methods, divide the data string into consecutive blocks of m bits each, and convert the m-bit binary code in each block into n-bit binary code. NRZI, which is the basic modulation method, converts data into codes and converts the binary code string obtained after data conversion into
(Non-Return to Zero Inverse) or in combination with NRZ modulation. Generally, a modulation method for high-density recording on a recording medium is required to satisfy the following conditions. () The minimum inversion interval (hereinafter referred to as T _nio ) of the write signal waveform to the recording medium obtained after modulation is long and the maximum inversion interval (hereinafter referred to as T _nax ) is short. When T _nio is long, interference between adjacent inversions becomes smaller, allowing for higher density.
A short T _nax facilitates self-synchronization. () The detection window width (hereinafter referred to as _TW ), which is the time that can be used to detect recorded bits from the signal reproduced from the recording medium, is wide. In magnetic recording, recorded bits are detected by detecting the peak of the reproduced signal waveform, and since T _W is the tolerance for deviation of the peak position, a wider T _W is suitable for high-density recording. In addition, in a recording/reproducing device using a laser beam, when the T _W is wide, the tolerance range for the deviation of the detection position becomes wide, and the amplitude at the detection point becomes large, so that the noise margin becomes large. When modulating the binary code string obtained after data conversion with NRZI, in which bit “1” corresponds to inversion and bit “0” corresponds to non-inversion, the values of T _nio , T _nax , and T _W are as shown in the following equations. Become. T _nio = (d+1)・T・m/n …(1) T _nax = (k+1)・T・m/n …(2) T _W =T・m/n …t(3) Here , d is the minimum value of the number of consecutive 0s, k is the maximum value of the number of consecutive 0s, T is the length of 1 bit before conversion, m/n is the ratio of the number of bits in 1 block before and after conversion, and ( (number of bits before conversion)/(number of bits after conversion). These T _nio , T _nax , T _W
The values of are in a contradictory relationship with each other, and if any one is improved, the others tend to deteriorate. However, in the future, with improvements in the time accuracy of recording devices or transmission devices and advances in data detection circuits, the requirement for a T _W value that is approximately equal to the jitter tolerance will be relaxed, and it will become important to improve the T _nio and T _nax values. It is expected that 3PM (Three Position Modulation) is known as a conventional modulation method aimed at high-density recording. In this data conversion in 3PM, 3 bits of the data series are treated as one block, and the 3-bit code in each block is converted into a 6-bit code consisting of P ₁ to P ₆ based on the conversion table shown in Table 1. Ru. Then, the fifth bit P ₅ counting from the first bit in each block after conversion
If the first bit P ₁ of the next block and the first bit P 1 of the next block are both 1, P ₅ of the previous block and P ₁ of the next block are both set to 0, and P ₆ of the previous block is set to 0.
is set to 1. In this 3PM, (d, k,
Since m, n) = (2, 11, 3, 6), T _nio ,
T _nax and T _W are respectively shown in the following equations. T _nio = 1.5T ……(4) T _nax = 6T ……(5) T _W = 0.5T ……(6) As shown in equation (4), the value of T _nio at 3PM is:
This is larger than T _nio , which is less than 1T in other conventional modulation methods such as MFM (Modified Frequency Modulation). However, as shown in equation (5), the value of T _nax at 3PM is 2T
The value of T _nax is larger than that of MFM, which makes self-synchronization relatively difficult. For this reason, adopting 3PM had the disadvantage that the configuration of the demodulator became complicated. Furthermore, in 3PM, 3
The modulation method used to record data in a data processing device such as a computer is often a power of 2, such as 8 bits or 16 bits, because the conversion process is performed with bits as one block. If 3PM is adopted as the modem, the configuration of the modem will be complicated. Therefore, an object of the present invention is to obtain a modulation signal with a larger T _nio and a smaller T _nax compared to 3PM, thereby making it possible to record and transmit high-density data and facilitate self-synchronization. Another object of the present invention is to provide a data conversion method that can simplify the configuration of a modulation/demodulation device for recording or transmitting data in a data processing device such as a computer. The data conversion method according to the present invention divides a data series represented by a binary code into consecutive 2-bit blocks, and after conversion, adjacent blocks are
2 in each of the blocks such that the number of 0s between and 1 is between 3 and 9.
The binary code of the bit is changed to the 3-bit binary code “000”,
It is characterized by converting into a 5-bit binary code obtained by adding a 2-bit binary code to each of ``001'', ``010'', and ``100''. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When it is desired to record continuous data on a recording medium such as a digital audio disk as shown in FIG. 1A, this data series is divided into consecutive blocks of 2 bits each. The first block is called the first, second, third...seventh block in order, and the blocks are formed by two bits of binary code in two adjacent blocks, such as the sixth and seventh blocks. The 2-bit binary codes in blocks other than the two blocks whose 4-bit code is "0111" are sequentially converted into 5-bit binary codes in accordance with the conversion table shown in Table 2. However, when the 4-bit code formed by the binary codes in two blocks adjacent to each other, such as the sixth and seventh blocks, is "0111", the two blocks are converted according to the conversion table shown in Table 3. Convert the 2-bit binary code in each to a 5-bit binary code. Then, a code string as shown in FIG. 1B is obtained. By modulating this code string with NRZI, a write signal to the recording medium as shown in C in the figure is obtained, and T _nio and T _nax become 1.6T and 4T, respectively. In addition, in Tables 2 and 3, X ₁ becomes "1" when the data after conversion of the immediately preceding block is "01000", and becomes "0" when the data is other than "01000". The symbol X ₂ indicates that
This symbol indicates that when the data before conversion of the next block is "00" or "01", it becomes "1", and when the data is "10" or "11", it becomes "0". FIG. 2 shows a conversion circuit that performs data conversion using the data conversion method according to the present invention. Second
In the figure, each bit forming a data sequence is sequentially input to a 6-bit shift register 1 by a clock a. Clock a is formed of pulses output at a predetermined repetition frequency from a conversion clock generation circuit (not shown). Here, each bit of the 2-bit binary code in four consecutive blocks is sequentially d ^-2 ₀ , d ^-2 ₁ , d ^-1 ₀ , d ^-1 ₁ , d ⁰ ₀ from the higher to the lower. , d ⁰ ₁ , d ¹ ₀ , d ¹ ₁
shall be. Signals corresponding to the states of these d ^-2 ₀ to d ¹ ₁ are supplied to the logic circuit 2. In the logic circuit 2, the 2-bit binary code consisting of d ⁰ ₀ and d ⁰ ₁ is converted into a 5-bit binary code according to Tables 2 and 3.
If each bit of this 5-bit binary code is set as b ₀ , b ₁ , b ₂ , b ₃ , b ₄ in order from the upper to the lower, the logic circuit 2 will mutually connect the bits so as to satisfy the following logical formula. It is made up of multiple connected logic gates. b ₀ = d ^-2 ₀・^-2 ₁・d ^-1 ₀・d ^-1 ₁・⁰ ₀・⁰ ₁ + ¹ ₀・
d ^-1 ₁・d ⁰ ₀・d ⁰ ₀ = {(d ^-2 ₀ + ^-2 ₁ ) d ^-1 ₀・⁰ ₀・⁰ ₁
+ ^-1 ₀・d ⁰ ₀・d ⁰ ₁ }・d ^-1 ₁
...(7) b ₁ = ^-1 ₀・^-1 ₁・d ⁰ ₀・d ⁰ ₁ = (d ^-1 ₀ + ^-1 ₁ ) d ⁰ ₀・d ⁰ ₁ ...(8) Or, b ₁ = d ⁰ ₀・d ⁰ ₁・b ₀ ...(9) b=d ⁰ ₀・d ⁰ ₁ ...(10) b ₃ = ⁰ ₀・d ⁰ ₁・¹ ₀・¹ ₁ = ⁰ ₀・d ⁰ ₁・( ¹ ₀ + ¹ ₁ ) ...(11) b ₄ = ⁰ ₀・⁰ ₁・¹ ₀ + ^-1 ₀・d ^-1 ₁・d ⁰ ₀・d ⁰ ₁・¹
₀ = ( ⁰ ₀ 〓・⁰ ₁ + ^-1 ₀・^-1 ₁・⁰ ₀・⁰ ₁ )
¹ ₀ ...(12) or b ₄ = ₁・₂・₃・¹ ₀ ...(13) The 5-bit binary code output from the logic circuit 2 is clocked by the conversion clock generation circuit (not shown). A clock b consisting of pulses output with a repetition frequency that is 1/2 of the repetition frequency of a.
is loaded into the 5-bit shift register 3 by. Thereafter, a 5-bit binary code is sequentially output bit by bit from the serial output terminal of the 5-bit shift register 3 by the clock c. clock c
is formed of pulses outputted from the conversion clock generation circuit (not shown) with a repetition frequency five times that of clock b. FIG. 3 shows an inverse conversion circuit that returns the data converted by the circuit of FIG. 2 to its original state. In FIG. 3, the converted data is sequentially input one bit at a time to a 10-bit shift register 4 by clock d. Clock d is output from a pulse generating circuit (not shown) configured to receive converted data and reproduce pulses having the same repetition frequency as clock c. Here, each bit forming three consecutive blocks of data after conversion is sequentially converted from high to low by b ^-1 ₀ , b ^-1 ₁ ,
_b ^-1 ₂ , b ^-1 ₃ , b ^-1 ₄ , b ⁰ ₀ , b 0 ₁ , b ⁰ ₂ , b ⁰ ₃ , b ^{0 4} , b ¹ ₀ , b ¹
₁ ,
Let b ¹ ₂ , b ¹ ₃ , b ¹ ₄ . Then, logic circuit 5 becomes 10
When b ^-1 ₁ , b ⁰ ₀ , b ⁰ ₁ , b ⁰ ₂ , b ⁰ ₃ and b ¹ ₀ of the bits in three consecutive blocks are input to the bit shift register 4, b ⁰ ₀ to b ⁰ ₄ is configured to output 2-bit codes d ₀ and d ₁ obtained by inverse transformation of the transformations shown in Tables 2 and 3 from the 5-bit binary code formed by There is. That is, the logic circuit 5 is formed of a plurality of logic gates connected to each other so as to satisfy, for example, the following logic formula. d ₀ = b ⁰ ₁ + b ⁰ ₂ + ^-1 ₁・b ⁰ ₀ ...(14) d ₁ = b ⁰ ₁ +b ⁰ ₃ + ^-1 ₁・b ⁰ ₀ +b ¹ ₀ ...(15) This logic circuit The 2-bit data output from 5 is transferred to 2-bit shift register 6 by clock e.
After being loaded into the 2-bit shift register 6, the data is sequentially output one bit at a time by the clock f. Clock e is output from a pulse generation circuit (not shown) that generates pulses with a repetition frequency of 1/5 of the repetition frequency of clock d, and clock f has a repetition frequency twice that of clock e. is output from a pulse generation circuit (not shown) that generates a pulse having . In the above embodiment, after dividing the data series into blocks of 2 bits each, the 2-bit code in each block is converted into a 5-bit code using the conversion tables shown in Tables 2 and 3, respectively. However, in principle, the 2-bit code in each block is converted using the conversion table shown in Table 4, but the 2-bit code in two adjacent blocks is
When the 4-bit code formed by the base code is ``1000'', the 2-bit code in each of the 2 blocks can be converted to a 5-bit code using the conversion table shown in Table 5. good. Furthermore, the 2-bit code in each block is basically converted according to Table 6 or Table 8, but the 4-bit code formed by the binary codes in two adjacent blocks is "0111". In this case, the 2-bit code in each of the two blocks may be converted into a 5-bit code using the conversion table shown in Table 7 or Table 9. still,
In Tables 4 and 5, both X ₁ and X ₂ are the second
These symbols indicate the same items as those in the table and Table 3. Also, in Tables 6 and 7, X ₃
The data after conversion of the previous block is "00100".
When , it becomes "1" and the relevant data is "00100"
A symbol indicating that it is "0" in other cases, X ₄
The data after conversion of the previous block is "X ₄ 0000"
Or, it is a symbol indicating that it is "1" when it is "01000" and "0" when the data is other than "X ₄ 0000" or "01000". Also, the 8th
In the table and Table 9, _X5 is a symbol indicating that when the converted data of the next block is "00100", it becomes "1" and when the data is other than "00100", it becomes "0". , X ₆ becomes "1" when the converted data of the next block is "0000X ₆ " or "00010", and becomes "0" when the data is other than "0000X ₆ " or "00010". This symbol indicates that Here, in the conversion table shown in Table 2, when the data series is divided into blocks of 2 bits each, four types of information that can be expressed by the 2 bits included in each block, namely the first and second codes, are shown. , 3rd
and fourth information, these first to fourth information
The information corresponds to the bit patterns "00", "01", "10", and "11" in the 2-bit code before conversion, and the bit patterns "X ₁ 000X ₂ ", " 00010”, “00100”, “01000”
It corresponds to On the other hand, in Table 4, the correspondence between the four types of information and the bit patterns in the 2-bit code before conversion is that each of the first to fourth information is "01", "10", "11", They are designed to correspond to "00" respectively. Similarly to Table 3, Table 5 shows a conversion method when two blocks adjacent to each other become a combination of "second information and fourth information". In this way, conversion may be performed using a conversion table obtained by changing the correspondence between the four types of information that can be expressed by 2 bits and the bit patterns in the 2-bit code before conversion. In addition, the 5-bit bit pattern in the conversion table in Table 2 is the 3-bit code "000", "001",
The bit pattern is obtained by adding one bit before and after each of "010" and "100". On the other hand, the 5-bit bit pattern in the conversion table in Table 6 has the 3-bit code "000",
The bit pattern is obtained by adding a 2-bit code in front of each of "001", "010", and "100", and the 5-bit bit pattern in the conversion table in Table 8 is The bit pattern is obtained by adding a 2-bit code after each bit code. These conversion tables in Table 6 or Table 8 also perform data conversion such that the values of T _nio , T _nax and T _W are the same as when using the conversion table in Table 2. In this way, as shown in the conversion tables in Tables 6 and 8, the 2-bit code in each block in the data string can be changed to 3-bit codes "000", "001", "010", and "100".
5 obtained by adding 2 bits of sign to each of
It is also possible to perform data conversion using other conversion tables, such as conversion to bit codes, so that the values of T _nio , T _nax and T _W are the same as when using the conversion table in Table 2. . Further, in the above embodiment, both the logic circuits 2 and 5 are formed of a plurality of logic gates, but the logic circuits 2 and 5 can also be formed using a ROM (read-only memory). Furthermore, in the above embodiment, the logic circuit 2 is configured to receive the supply of four blocks of bits and perform the conversion process using logic gates connected to each other so as to satisfy a predetermined logical formula. In order to reduce the number of bits in the shift register 1, the logic circuit 2 may also be configured to receive bits output from the shift register 3 and perform conversion processing. However, in this case, it is necessary to change the logical formula to be satisfied in the logic circuit 2 and to increase the number of flip-flops forming the shift register 3 so that the number of bits in the shift register 3 increases. Similarly, in the above embodiment, the logic circuit 5 is configured to receive 6 bits of data from the shift register 4 and perform a conversion process using logic gates connected to each other so as to satisfy a predetermined logical formula. However, in order to reduce the number of bits in the shift register 4, the logic circuit 5 may be configured to receive bits output from the register 6 and perform conversion processing. However, in this case as well, it is necessary to change the logical formula to be satisfied in the logic circuit 5 and to increase the number of flip-flops forming the shift register 6 so that the number of bits in the shift register 6 increases. As detailed above, in the data conversion method according to the present invention, (d, k, m, n) = (3, 9, 2,
5) Data conversion is performed so that
T _nio = 1.6T, T _nax = 4T, T _W = 0.4T and 3PM
Compared to , the value of T _nio is large and the value of T _nax is small. Therefore, according to the present invention, higher density recording or transmission is possible than in the case of conventional modulation methods such as 3PM, and the value of T _nax is significantly reduced, so that self-synchronization circuits are not required. This will simplify the configuration. Furthermore, the value of T _W is
Although it is 0.1T smaller than 3PM, it is thought that practical problems can be prevented by improving the time accuracy of future recording/reproducing devices or transmission devices and by advancing data detection circuits. Furthermore, since the data conversion method according to the present invention processes a data series every 2 bits, it is possible to easily configure a modulation/demodulation device in a data processing device such as a computer in which the number of bits representing a unit of processing is a power of 2. can do. Therefore, the data conversion method according to the present invention is useful for recording devices that record data on recording media such as magnetic disks, magnetic tapes, and optical recording disks in computers, and for converting video information or audio information.
It is suitable for use in any device that performs high-density recording or transmission of digital signals, such as a PCM recording/reproducing device or a data transmission device.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】 [Brief explanation of drawings]

FIG. 1 is a diagram showing an example of data conversion according to the present invention, FIG. 2 is a circuit diagram showing an example of a circuit of a converter that performs data conversion according to the present invention, and FIG.
FIG. 3 is a circuit diagram showing an example of a circuit of an inverse converter that restores data converted by the converter shown in the figure. Explanation of the symbols of the main parts, 1, 3, 4, 6...shift register, 2, 5...logic circuit.

Claims (1)

[Scope of Claims] 1. A data series represented by a binary code is divided into consecutive blocks of 2 bits each, and the first to fourth blocks represented by the 2-bit binary code in each of the blocks are The information is made to correspond to each of the 3-bit codes "000", "001", "010" and "100", and one bit is added before and after each of the 3-bit codes to create the 5-bit first to fourth bits. Obtain conversion codes “X ₁ 000X ₂ ”, “00010”, “00100” and “01000”, and make these conversion codes correspond to the first to fourth information represented by each block,
When the second and fourth information are consecutive, the second conversion code is "00000" and the fourth conversion code is "1000X ₂ " (However, when the previous conversion code is "01000", X ₁ is 1. Indicates 0 when the information is other than "01000"; X ₂ indicates 1 when the information immediately before conversion is the first information or the second information; 0 when the information is the third information or the fourth information.) In the later code, the number of 0s between adjacent "1" is 3
A data conversion method characterized by converting the data into any one of nine items. 2 Divide the data series represented by the binary code into consecutive blocks of 2 bits each, and convert the first to fourth information represented by the 2-bit binary code in each block into a 3-bit code. The code is made to correspond to each of "000", "001", "010" and "100", and 2 bits each are added in front of the 3-bit code to create the 5-bit first to fourth conversion codes "X ₄ X ₃ 000", "X ₄ 0001", "00010" and "00100", and make these conversion codes correspond to the first to fourth information represented by each block,
When the second and fourth information are consecutive, the second conversion code is "X ₄ 0000" and the fourth conversion code is "01000" (However, when the previous conversion code is "00100", X ₃ is 1. Indicates 0 when the code is other than ``00100'', 1 when <sub>the</sub> previous conversion code is ``X ₄ 0000'' or ``01000'', and 0 when the code is other than ``X ₄ 0000'' or ``01000''.) A data conversion method characterized in that the number of 0s between adjacent "1"s in the converted code is between 3 and 9. 3 Divide the data series represented by the binary code into consecutive blocks of 2 bits each, and convert the first to fourth information represented by the 2-bit binary code in each block into a 3-bit code. The code corresponds to each of "000", "001", "010" and "100", and 2 bits each are added after the 3-bit code to create the 5-bit first to fourth conversion codes "000X <sub>5</sub> X <sub>6</sub> ". ”, “00100”, “01000” and “1000X <sub>6</sub> ” (However, X <sub>5</sub> indicates 1 when the immediately preceding conversion code is “00100” and 0 when it is other than “00100”, and X <sub>6</sub> indicates the immediately following conversion code. 1 for "0000X <sub>6</sub> " or "00010" and 0 for anything other than "0000X <sub>6</sub> " or "00010"), and correspond the first to fourth information represented by each block to these conversion codes. and when the second and fourth information are consecutive, the second conversion code is "00010", the fourth conversion code is "0000X <sub>6</sub> ", and adjacent "1" and "1" in the converted code are A data conversion method characterized in that the number of 0s between `` and `` is set to be any one of 3 to 9.