JPH0473339B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital modulation method that is applied when transmitting binary codes using a magnetic recording/reproducing device, a rotating disk, or the like as a medium.

In this invention, the minimum interval Tmin between two inversions (transitions) is T (T is the time per 1 bit of input data), and the maximum interval Tmax is
2.5T, the unit Tw of the inversion interval of the modulated wave is 0.5T,
Moreover, it is a digital modulation method that does not have a spectrum of DC components.

Traditionally, the MFM method (Tmax = 2T) and the M ² FM method (Tmax = 2.5T) have been known as digital modulation methods for (Tmin = T, Tw = 0.5T), but these It had a spectrum of components.

According to this invention, since it does not have a spectrum of DC components, even when a rotary transformer is involved and it is difficult to transmit DC and low-frequency components, such as in a rotating head type recording/reproducing device, the waveform This can prevent distortion from occurring. In addition, the present invention provides a modulation method that does not have a DC component and has a ratio (Tmax/Tmin) of the minimum inversion interval to the maximum inversion interval (Tmin=T, Tw=0.5T), with Tmax=3T.
Miller-2 is known, but compared to them,
The frequency spectrum of the modulated waveform will be concentrated in a narrow range. Therefore, the band of the recording amplifier or the reproducing amplifier may be narrow, circuit design becomes easier, noise can be reduced, and the error rate of the reproduced waveform can be further reduced. At the same time, it is possible to easily design a PLL circuit for self-clock extraction.

An embodiment of the present invention will be described below.
In this example, the input data is divided into blocks from the first value (0) and the second value (1), with the boundaries before and after 0 being alternately used as boundaries. and,,
A first group consisting of two bits of a first value (0) or successive blocks of bits of a second value (1) sandwiched by a bit of 0 is determined according to the modulation rule shown in FIG. The second group consists of blocks of only 1 bits and no 0s.
Modulate according to the modulation rules shown in the figure.

A 0 always has a block boundary before or after it, and 0s with a boundary before and 0s with a boundary after appear alternately. Therefore, if the last 0 that appears is a 0 with a boundary before it, the next 1 will be modulated according to the rules shown in Figure 1, and if it is a 0 with a boundary after it, it will be modulated according to the rule shown in Figure 2. Modulated according to the rules shown.

In Figure 1, N is two zeros of input data.
It shows the number of 1's in between.

When (N=0), the input data 00 is converted to 0011 at twice the rate. In the case of input data containing consecutive 0s, 0s and 1s are inverted at each bit cell, resulting in an inversion interval of T.

When (N=1), the input data is inverted at the center of the 1 bit cell.

(N=2), 00111100 or 1100011
Convert to

(N=3), 0001100111 or
Convert to 1110011000.

When (N≧4) and (N=2n), the first 0 is set to a low level, and after that, high and low levels are alternately repeated for every two bits of 1 in the input data.

When (N≧5) and (N=2n+1), the first 0 is set as a low level, and after that, high and low levels are alternately repeated for every two bits of 1 in the input data. However, the last 5 bits of 1 in the input data are 2.5T twice in a row, and the remaining period is as follows:
2T.

It should be noted that two types of waveforms may exist, as shown by the broken lines, depending on whether the front or rear of the block shown in FIG. 1 is 0 or 1.

The second group also produces an inversion at the center position of the bit cell of the original input data. Therefore, no matter how many 1's occur in succession, the inversion interval is T.

According to the modulation rules shown in FIGS. 1 and 2 above, the sum of low-level periods and the sum of high-level periods within one block are equal, and even for a series of data consisting of multiple blocks. A similar relationship holds true and it is possible to eliminate the spectrum of DC components.

FIG. 3 shows the configuration of a modulation circuit in one embodiment of the present invention, in which input data is supplied from an input terminal 2 as a serial input of a shift register indicated by 1. Input data is (Y→Z→A→B→C→D)
The inverted value of each bit is also taken out from the shift register 1 and sent to the combinational circuit 4.
is supplied to Further, input data is input to J and K of the JK flip-flop 3, and the output Q of this flip-flop 3 is supplied to the combinational circuit 4. The output Q of this flip-flop 3 is
If the last 0 appearing up to Z gives a block boundary before it, it becomes 0, and if it gives a boundary after that, it becomes 1. Then, one bit of input data A from the combinational circuit 4 is converted into two bits of _P1 and _P2 .

The output of this combinational circuit 4 is supplied to D-type flip-flops 5 and 6 and a selector 7. A JK flip-flop 8a is connected to the selector 7,
Modulated data is obtained at the output terminal 8 of the JK flip-flop 8a. Previous modulation outputs a and b corresponding to bit Z of the input data appear at the outputs of the flip-flops 5 and 6, and are supplied to the combinational circuit 4. In addition, the selector 7 sequentially outputs the simultaneously generated two bits P ₁ and P ₂ at a transmission rate twice that of the input data, and outputs them to the output terminal 8.
Modulation data can be obtained. This modulation data is
The order is (a→b→P ₁ →P ₂ ). The output data generated at the output of selector 7 is 1 when the modulation waveform changes from low level to high level or vice versa.
When there is no change in level, it becomes 0.
By passing this signal through the JK flip-flop 8a, modulated data whose level is inverted when the output of the selector 7 is 1 and whose level is not inverted when it is 0 is obtained.

The combinational circuit 4 has bits Z, Y, B,
With reference to C and D, output bits _P1 and _P2 corresponding to bit A of the input data are generated using the following logical formula.

P ₁ =・{+・B・(+)・(+D)} P ₂ =A・[Q+・(+C・) +Z・・{B・C・+b・(+・)}] These logical formulas are , corresponds to the modulation rule set forth in claim 1, and its derivation will be explained below.

When input data A is 0, its input bit A
is modulated according to the first group of modulation rules.

P ₁ =・P ₂ =0 (1) When input data A is 1, depending on the value of Q, whether the modulation rule of the first group or the modulation rule of the second group is followed depends on the value of Q.

When Q = 0, the input data 0 that appeared last before that has a boundary before that bit, so A
are the first group of bits.

P ₁ =・A{・B・(+D) +・Z・B(+D)} P ₂ =・A・{・+・B・C・ +・Z・B・+・b・Z・ +・Z・B・C・} ...(2) When Q=1, conversely, A is the bit of the second group.

P ₁ = 0 P ₂ = Q・A...(3) By adding the above equations (1), (2), and (3) for each P ₁ and P ₂ , and simplifying by grouping the common terms, The above logical formula is found. However, the above-mentioned logical formula is not unique.

According to the above-mentioned modulation circuit, two types of modulated outputs as shown in FIG. 5 are generated for input data (01111100...). In Fig. 5, what is shown in the upper row is defined as the first 0 that appears with a boundary (indicated by ・) in front of it (Q=0),
This is a waveform in which five successive 1's are modulated according to the rules shown in FIG. In addition, in Fig. 5, in the case shown in the lower row, the first 0 that appears after that is defined as having a boundary (Q = 1), and the next 1 is defined as the second one.
This is a waveform modulated according to the rules shown in the figure.

FIG. 4 shows the configuration of the demodulation circuit, and the input terminal 1
The modulation data from 0 and the previous bit passed through flip-flop 10a are exclusive OR.
The signal is supplied to the gate 10b. exclusive
OR gate 10b generates a modulation signal that becomes 1 when the level of modulation data changes. A modulation signal is sent from the exclusive OR gate 10b to the shift register indicated by 9 (a→b
→c→d→e), c,
d, is supplied to the combinational circuit 11. Bit A corresponding to b and c of the modulation signal is connected to the combinational circuit 11.
is output from. Further, a detection signal that becomes 0 when the modulated signal is in period 0 of 2.5T and becomes period 1 of the next 2.5T is generated from the NAND gate 12.

That is, the NAND gate 12 is supplied with bits a, . . . of the modulated data, as well as bits . in modulated data
In the case of a continuous pattern of 2.5T, it is set to 1 when there is a level change, so the bits (w,
x, y, z, a, b, c, d, e) becomes (000010000), and the output of the NAND gate 13 becomes low level. Based on the output of the NAND gate 13, it is detected whether the 2-bit division of the modulated signal matches the 1-bit division of the demodulated data. The output of this NAND gate 12 is used as the K input of the JK flip-flop 13. This J input is always 1 and is supplied with a clock input from terminal 14. Normally, a 1/2 divided clock pulse appears from flip-flop 13, which is supplied to D-type flip-flop 15 as a clock input. Then, when the output of the NAND gate 12 becomes 0, the flip-flop 13
The output of is set to 1, and phase matching is performed. The output of the combinational circuit 11 is supplied as a data input to the flip-flop 15, and demodulated data is taken out at the output terminal 16.

Note that the phase matching of the modulated signal may be performed by inserting a synchronizing signal (of a bit pattern that does not normally appear) into the modulating signal and detecting this synchronizing signal.

The combinational circuit 11 converts bits b and c of the modulation signal.
It demodulates 1 bit of data corresponding to
A demodulated output is generated according to the following logical formula.

A=・+c+・ The logical formula for demodulation described above is for demodulating digital data modulated according to the modulation rule set forth in claim 1, and this is for demodulating to 1. It is based on the following data to be determined.

The first one is inverted at the center of the period of one bit of demodulated data, and can be demodulated with (A=c).

The second one is when there is no central inversion, and there is no inversion in a 2-bit period together with the previous 1-bit period, and it can be demodulated by (A=...).

The third case is when there is no central inversion, and there is no inversion in the subsequent 1-bit period as well as in the 2-bit period, and it can be demodulated by (=...).

Note that the modulation circuit combination circuit 4 and the demodulation circuit combination circuit 11 can be realized by a ROM.

As understood from the description of one embodiment above,
According to the present invention, it is possible to perform digital modulation in which the modulation signal does not have a DC component spectrum and the difference between the maximum value and the minimum value of the inversion interval is small. Therefore, even if DC components and low-frequency components cannot be transmitted, waveform distortion can be prevented, the frequency spectrum of the modulated waveform is concentrated in a narrow range, and self-clocking is facilitated.

FIG. 6 shows a modulation rule for another embodiment of the invention, as applied to a first group of consecutive blocks of 1 bits interspersed with 0 bits. A second group of 1-bit blocks containing no 0s is modulated according to the modulation rules shown in FIG. 2, as in the previous embodiment.

Comparing the modulation rules shown in Figure 1, (N=3)
The case is different from the case where (N≧5) and (N=2n+1). In other words, the data adjacent to the block outside the block is 0 both before and after the block, and (N
= 3), it is modulated as (T→2.5T→1.5T), and in the case of (N≧5) and (N=2n+1), the last one is (2.5T→1.5T) and the others are modulated as 2T. Separated by each.

As shown in Figure 7, three consecutive input data
Bits Z, A, and B, and modulation signal a corresponding to Z,
b, modulation signals P ₁ and P ₂ corresponding to input data A are generated according to the following logical formula.

P ₁ =・{+・B・(+)} P ₂ =A・{Q+・(+)} These logical expressions correspond to the modulation rule described in claim 2, and their The derivation will be explained below.

When input data A is 0, P ₁ =・P ₂ =0 (4) When input data A is 1 and Q=0, P ₁ =・A{・B+・Z・B} P ₂ =・A{・+・Z・} ...(5) When Q=1, conversely, A is the bit of the second group. Similar to the previous example, P ₁ = 0 P ₂ = Q・A...(6) Add the above equations (5), (6), and (7) for each P ₁ and P ₂ , and group the common terms. Then, by simplifying, the above logical formula can be found.

Therefore, when input data similar to that shown in Fig. 5 is modulated, two types of modulated signals can be obtained depending on whether the block boundary is before or after the first 0 that appears, as shown in Fig. 8. It will be done. Further, the demodulation rules are the same as those described above.

When the modulation rule shown in FIG. 6 is used, the number of input data bits required during modulation can be reduced, and the configuration of the modulation circuit can be made simpler.

FIG. 9 shows modulation rules in another embodiment of the invention. The modulation rule shown in FIG. 6 is applied to the first group consisting of consecutive blocks of 1 bits interleaved with 0 bits, and the second group consisting of blocks of only 1 bits without 0 bits is applied. The modulation rules shown in FIG. 9 are applied to the group. In other words, when the number M of consecutive 1 bits is (M≧5), not only the inversion interval of T, but also
The modulation is performed so that inversion intervals of lengths 2T and 2.5T occur. In this way, the frequency spectrum of the modulated signal can be made lower than when it consists only of the inversion interval of T, and the design of the recording amplifier and reproduction amplifier can be facilitated.

This modulation rule is based on input data (Z, A, B, C, D) and modulation signals (a,
b, c) is expressed by the following logical formula.

P ₁ =・(+B・[・(+) +a.b.{・(+)+C・D・}]) P ₂ =A・[・(+) +Q・{+(+)・(c+・F )}] In the above formula, F is the number of consecutive bits A.
It becomes 1 when it is the 4nth 1 or the (4n+3)th 1.

When the same input data as described above is modulated using such a modulation rule, two types of modulated signals are formed, as shown in FIG. 11, depending on whether the boundary is before or after the first 0.

Furthermore, the modulation rules shown in FIG. 6 may be applied to the first group, as described above, and the modulation rules shown in FIG. 12 may be applied to the second group.

What is shown in FIG. 12 differs from FIG. 9 in that when there are four or more consecutive even numbers M of 1, the modulation is performed so as to rise from the starting position of the boundary. By doing so, the rate at which a pattern with an inversion interval T appears in a modulated signal can be further reduced.

As shown in Fig. 13, modulation signals _P1 and _P2 are formed according to the following logical formula in response to bit A of consecutive bits (Z, A, B, C, D) of input data. be done.

P ₁ =・[+B・{(+C・D)・(+) +Q・a・・(+)}] P ₂ =A・[・(+)+Q・{・( +)・(+・F) +Z...b}] In the above formula, F becomes 1 when bit A is the (4n+2)th 1 or the (4n+3)th 1 of consecutive 1s.

When input data similar to that shown in FIG. 5 is modulated using the modulation rule shown in FIG. 12, as shown in FIG. Modulated signals with two different waveforms are obtained.

In addition, in the above explanation, 0 is taken as the first value, and 1
is taken as the second value, but this relationship may be reversed.

[Brief explanation of the drawing]

1 and 2 are waveform diagrams used to explain modulation rules in one embodiment of the present invention, and FIGS. 3 and 4 show the respective configurations of a modulation circuit and a demodulation circuit in one embodiment of this invention. A block diagram, FIG. 5 is a waveform diagram showing an example of a modulation signal in one embodiment of the invention, FIGS. 6 and 7 are waveform diagrams and schematic diagrams showing modulation rules in other embodiments of the invention, 8th
The figure is a waveform diagram showing an example of a modulation signal in another embodiment of the invention. 1, 9...Shift register, 4, 11...Combination circuit.

Claims (1)

[Claims] 1. When input data consisting of a combination of a first value (0) and a second value (1) is ), and a first group in which a second value (1) exists contiguously, and
In the bit pattern belonging to the first group when divided into the second group consisting only of the second value (1), (a) If two first values (0) are connected, (b) When a second value (1) is sandwiched between the first value (0), it is reversed at the center of the bit cell of the second value (1). , (c) When three second values (1) are connected to the first value (0), the second values (1) are inverted at the center of each bit cell, (d) The first value When an even number (2, 4,...) of second values (1) are sandwiched between (0), it is inverted at the boundary of the bit cell whose unit is two concatenated second values (1), (e) When an odd number (5, 7,...) of second values (1) are sandwiched between the first value (0), the unit is two concatenated second values (1). The bit cell is inverted at least at one end, and for one second value (1), it is inverted at the center of the bit cell, and for bit patterns belonging to the second group, it is inverted at the center of each bit cell. A digital modulation method characterized by modulating input data. 2 Input data consisting of a combination of a first value (0) and a second value (1), when two first values (0) are connected or when a first value (0) is sandwiched between a first group in which two values (1) exist in conjunction;
In the bit pattern belonging to the first group when divided into the second group consisting only of the second value (1), (a) If two first values (0) are connected, (b) When a second value (1) is sandwiched between the first value (0), it is reversed at the center of the bit cell of the second value (1). , (c) When three second values (1) are connected to the first value (0), it is inverted at both ends of the bit cell whose unit is the three connected second values (1). (d) When an even number (2, 4,...) of second values (1) are sandwiched between the first value (0), the unit is the two concatenated second values (1). (e) When an odd number (5, 7,...) of second values (1) are sandwiched between the first value (0), two concatenated second values is inverted at at least one end of the bit cell whose unit is the value (1) of A digital modulation method characterized by modulating input data with a modulation rule that is inverted at the center of each bit cell.