JPH04310672A - Voice signal reproducing circuit - Google Patents

Abstract

PURPOSE:To enable obtaining a good reproducing voice signal by performing the correct processing of an overlapping area regalrdless of the recording condition of data without using a memory besides a memory to store the voice data. CONSTITUTION:When a voice signal divided into plural data blocks and recorded in recording medium 1 is read from the medium 1 and written in a memory 4, the address data of the memory is corrected by an address correcting circuit 9, the overlapping area is processed, and the voice signal data divided into plural data blocks are converted to the continuous data and stored into the memory 4. The voice signal data is successively read from the memory 4, and the voice signal divided into plural data blocks is reproduced as a continuous voice signal.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an audio signal reproducing circuit for reproducing audio signals recorded on a recording medium, and in particular, audio signal data from a recording medium in which adjacent audio data are recorded at different positions. The present invention relates to an audio signal reproducing circuit for reproducing continuous audio.

0002

2. Description of the Related Art Hitherto, a still video audio recording system is well known as an audio signal data system in which n-th and (n±1)-th block data are recorded on a recording medium at separate positions. This still video is a system that records still images on a rotating magnetic recording medium and plays them back.Multiple concentric tracks are provided on a single magnetic disk, and each track corresponds to one still image. Generally, it is recorded by At this time, various information at the time of recording,
For example, the date, time, etc. are recorded simultaneously on the same track as an information signal, superimposed on the video signal.

However, this method has the disadvantage that since the video signal and the information signal are recorded in an overlapping manner on the same track, the amount of information is reduced due to the band limitation of the information signal. Therefore,
There has been a problem in that it cannot handle things that involve a large amount of information, such as audio signals and text information.

For these reasons, audio data is recorded separately from video signals on tracks for still image data, and the audio data is recorded in a predetermined format.

[0005] Furthermore, in order to obtain a large amount of audio data by recording on a track for still image data, the audio data is compressed into video signal band data by changing the sampling frequency of the audio data at the time of recording, and then recorded. There is.

By the way, in a still video, one audio data block is called a sector, and audio data is recorded in one sector in a signal arrangement as shown in FIG. 11(A). Also, one track is shown in (B) in Figure 11.
As shown in the figure, it is composed of the four sectors.

In FIG. 11(A), T1, T3, T
5, T8, T10 are fixed areas at the pedestal level, T
2 is a start flag area indicating the beginning of the sector, T9
is an end flag area indicating the end of a sector, T4 is a control code area for recording various information at the time of recording, T7 is an area for recording audio data, and T6 is an area for recording audio data divided into sectors, of the previous sector. This is an overlap area that has the same data as the last part. In addition, in FIG. 11(A), only the front part of T7 is shown as the overlap region, but
Since a similar overlap area exists at the front of the next sector, the area at the end with the same time length can also be regarded as an overlap area.

[0008] Furthermore, when reproducing audio data in formats such as those shown in FIGS. playback as a recorded audio.

FIG. 12 is a diagram showing a data state when audio data divided into four sectors is converted into continuous playback audio data. In Figure 12, sector 1
-4 shows only the area T7 in which the audio data shown in FIG. 11(A) is recorded out of the four sectors recorded on one track, and the shaded area in the figure is This is an overlap area. Furthermore, since the portion indicated by OL in the figure is a common area where adjacent blocks have the same data, data from one of the adjacent blocks is used. When such processing is performed,
This results in continuous reproduced audio data as shown in the lower part of FIG. 12. Note that the overlap area at the beginning of the reproduced audio data is used when continuous audio data is recorded over a plurality of tracks, and is used for the same processing as within the same track.

As an audio signal reproducing circuit including overlap processing, a configuration as shown in FIG. 13 is often used. That is, in the figure, 101 is a recording medium on which audio signals are recorded, and 102 is an analog/digital (hereinafter referred to as A/
103 is a digital/analog (hereinafter referred to as D/A) converter; 104 is the recording medium 101;
a memory (A) for temporarily storing audio data read from the
105 is a memory (A) that stores the flag position of the audio data stored in 104; 106 is a memory 1;
107 is a start flag indicating the beginning of the audio data block and an end flag detecting circuit is the end flag indicating the end of the audio data block. This is a microcomputer (hereinafter referred to as microcomputer) that performs various controls.

Next, the operation of the circuit shown in FIG. 13 will be explained. That is, the audio signal read from the recording medium 101 is
The signal is input to the A/D converter 102 and converted into digital audio data. The audio data output from the A/D converter 102 is input to a flag detection circuit 107, where a start flag indicating the beginning of the audio data block and an end flag indicating the end of the audio data block are detected. A) It is also input to 104 and accumulated.

[0012] Here, the audio data is stored in the memory (A) 104.
In order to know the address where valid audio data has been written, the microcomputer 108 records whether or not the start flag and end flag have been detected in the memory (B) 105 at the address where the flag detection circuit 107 has detected the start flag and end flag. Write 1-bit data.

[0013] Furthermore, the memory (A) 104 and the memory (B)
) 105 is controlled by the address generation memory control circuit 106 in response to a write start command from the microcomputer 108 in accordance with the audio data information.

Since the audio data stored in the memory (A) 104 is stored in the state shown in FIG. 11(B), overlap processing is applied to the reproduced audio data as shown in FIG. and read it out as a continuous sound, D/
It is necessary to send it to the A converter 103.

[0015] This overlap processing is carried out by the microcomputer 108.
Do it with That is, the address position where valid audio data is written is calculated from the address of the flag position written in the memory (B) 105, and the address value is used when actually reading data from the memory (A) 104. Corrections are made so that only valid audio data is read from memory (1) 104.

The address calculation method for this valid audio data will be explained with reference to the format of (A) in FIG. Therefore, the front part of the valid audio data can be found by advancing the address value corresponding to the period (T3+T4+T5+T6) from the detection position address of the start flag. Further, the last part of the valid audio data is found by returning the address value corresponding to the period (T8+T9) from the detection position of the end flag. In this way, the audio data read from the memory (A) 104 is input to the D/A converter 103 and reproduced as analog audio output.

As already mentioned, the still video audio signal is recorded on the recording medium 101 in a state compressed to the video signal band, so when it is stored in the memory (A) 104, it is written and read at high speed. When outputting the data, it is played back in the audio band, so the decompression operation is also performed by reading at a low speed.

[0018]

However, when the audio signal reproducing circuit is configured as shown in FIG. (B) 105 is required.

[0019]Also, overlap processing is performed by correcting the address from the flag detection position according to the format regulations, but in the format, 1
Since an error of about ±100 ns is allowed for two areas, it will hardly be a problem when recording and reproducing on the same system, but when reproducing from a recording medium 101 recorded on a completely different system, A shift of several clocks may occur with respect to the sampling frequency of the D converter 102. Therefore, there is a problem in that it is not possible to completely perform overlap processing between sectors, resulting in a reproduction state that is partially difficult to hear.

The present invention has been made in order to solve the above-mentioned problems in the conventional audio signal reproducing circuit that has overlap areas before and after each block and is divided into a plurality of data blocks and recorded on a recording medium. An object of the present invention is to provide an audio signal reproducing circuit that can correctly process an overlap area regardless of the data recording state without using any memory in addition to the memory for storing audio data. .

[0021]

[Means for Solving the Problems] In order to achieve the above object, the audio signal reproducing circuit of the present invention has a plurality of overlapping areas each having the same data as an adjacent data block before and after each block. An audio signal reproducing circuit that reproduces an audio signal divided into data blocks and recorded on a recording medium as continuous audio includes a memory that temporarily stores audio signal data read out from the recording medium, and a memory that temporarily stores audio signal data read out from the recording medium; When writing the recorded audio data to the memory,
Write control for controlling data writing to the memory so that data in the overlap area is overwritten at the same address in the memory based on a data comparison result of an overlap area of data blocks of adjacent audio data. and output means for reproducing and outputting the audio signal divided into a plurality of data blocks as a continuous audio signal by sequentially reading the audio signal data from the memory.

In particular, each data block of the audio signal recorded on the recording medium includes, in addition to the overlap area, a start flag indicating the beginning of the data block and an end flag indicating the end of the data block. The write control means compares an address generation circuit that generates address data to be supplied to the memory, a flag detection circuit that detects the start flag and the end flag, and data in an overlap area of adjacent data blocks. a comparison circuit; a coincidence detection circuit that determines a coincidence point in the overlap area from data of the comparison circuit; and an address that corrects address data when writing or reading the memory using data from the coincidence detection circuit. a correction circuit, when reading the audio signal divided into the plurality of blocks and recorded on the recording medium from the recording medium and writing the audio signal data to the memory, the address correction circuit corrects the address data of the memory. By doing so, the overlap region is processed, and the audio signal data divided into a plurality of data blocks is converted into continuous data and stored in the memory.

[0023]

[Operation] According to the audio signal reproducing circuit of the present invention, there is provided a memory that temporarily stores audio signal data, an address generation circuit that generates address data to be supplied to the memory, and a flag detection circuit that detects a start flag and an end flag. and,
a comparison circuit that compares data in an overlap region of adjacent data blocks; a match point detection circuit that determines a match point in the overlap region from data of the comparison circuit;
An address correction circuit corrects address data when writing or reading a memory using data from a matching point detection circuit, and uses a start flag indicating the beginning of a data block, an end flag indicating the end of a data block, and an adjacent data block. When an audio signal recorded on a recording medium divided into a plurality of data blocks having overlap areas containing the same data before and after each block is read from the recording medium and written to the memory, the address correction circuit The overlap area is processed by correcting the address data of the memory, and the audio signal data divided into multiple data blocks is converted into continuous data and stored in the memory, and the audio signal is transferred from the memory. By sequentially reading data, an audio signal divided into a plurality of data blocks is reproduced as a continuous audio signal.

In the audio signal reproducing circuit configured as described above, correct processing of the overlap area is performed regardless of the data recording state, without using any memory other than the memory for storing audio data, and a good performance is achieved. A reproduced audio signal can be obtained.

[0025]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the basic circuit configuration of an audio signal reproducing circuit according to an embodiment of the present invention. In the figure, 1 is a recording medium on which audio signals are recorded, 2 is an analog/digital (A/D) converter, and 3 is a digital/digital (A/D) converter.
An analog (D/A) converter; 4 is a memory for temporarily storing the audio data read from the recording medium 1; 5 is a memory for writing the audio data read from the recording medium 1 into the memory 4 or outputting audio from the memory 4; A microcomputer (microcomputer) instructs to read data, 6 a memory control circuit that generates a control signal when reading/writing the memory 4, 7
8 is an overlap processing circuit that performs overlap processing between sectors when storing audio data in the memory 4; 8 is a flag detection circuit that detects a start flag representing the beginning of an audio data block and an end flag representing the end of the audio data block; 9 is an address correction circuit that holds and corrects address values in memory 4 during overlap processing, 10 is an address generation circuit that supplies address values to memory 4, and 11 is from the start flag of audio data to the valid audio data area. This is a blanking counter that counts the blanking period of .

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the timing charts shown in FIGS. 2 and 3, taking as an example the case where the present invention is applied to a still video audio signal reproducing circuit.

The waveform in FIG. 2 read from the recording medium 1 (
Audio data like A) is input to the A/D converter 2 and converted into digital audio data. Note that this waveform (A) is shown for one sector of one track of a still video.

The audio data output from the A/D converter 2 is input to a flag detection circuit 8, where a start flag representing the beginning of the audio data block and an end flag representing the end of the audio data block are detected. Here, flag detection corresponds to positive polarity flags and negative polarity flags as shown in FIG. Threshold <A/D converter output data or negative polarity threshold> When data that becomes A/D converter output data is continuously input to the flag detection circuit 8 for a predetermined number of samples x or more, a flag is set. shall be determined to exist.

The flag detection circuit 8 outputs a pulse signal that rises at x from the beginning edge of the flag signal of the audio data (waveform (A)) as shown in FIG. 2 and falls at the end edge of the flag. The start flag detection signal (waveform (B)) and the end flag detection signal (waveform (C)) are output separately. Also, the polarity data of the flag is
This is used to determine the data recording state of each sector.

When the start flag is detected, the blanking counter 11 is cleared using the start flag detection signal (waveform (B)) as a reset signal, and starts counting from the last edge of the start flag. be.

Here, when the microcomputer 5 issues a command to the memory control circuit 6 to perform storage in the memory 4, the memory 4 enters a write operation. Sector 1 of the audio data is the first sector in the track, so no overlap processing is performed at the beginning of the valid audio data, so the count value corresponds to the blanking period (including the control code area) specified in the format. is obtained from the blanking counter 11, the counter of the address generation circuit 10 is started from the address value "0", and at the same time,
A control signal is generated from the memory control circuit 6 so that the memory 4 writes sector 1 data. Therefore, valid audio data of sector 1 is stored in memory 4 starting from address "0". Note that the sector number is determined and controlled by the microcomputer 5. The write operation of the memory 4 is performed by a memory write control signal as shown in waveform (F) in FIG.
This continues until the end flag of the same sector is detected.

Next, regarding the storage of the valid audio data of sector 2 in the memory 4, the valid audio data of sectors 1 and 2 are reproduced as continuous audio by performing overlap processing. Now, when audio data is stored in the memory 4, overlap processing is performed. Therefore, when writing the sector 1 data to the memory 4, the address correction circuit 9 holds the final address value of the valid audio data. However, at the end of the valid audio data, no control signal is output, and it is difficult to find the final address value, so in reality, as shown in waveform (G) in Figure 2, the end flag is detected. It is obtained by holding the address value of , and subtracting the value from the final address value to the end flag.

To store sector 2 data including overlap processing in the memory 4, as with sector 1, first, when a start flag is detected, the blanking counter 11 is operated. Here, when the count value of the blanking counter 11 advances to a predetermined value of m clocks earlier than the count value corresponding to the blanking period defined by the format, the address generation circuit 10 is activated. In this embodiment, m=6.

As the count start value of the address generation circuit 10, the final address value determined from the address value at the time when the end flag held during the write operation of sector 1 was detected is set. The final address value here is not the end of the valid audio data, but a value returned by a data period corresponding to the rear overlap.

When the counter of the address generation circuit 10 is operated and the memory 4 is put into a read operation state, data corresponding to the rear overlap of the sector 1 is read out. FIG. 3 shows the timing of the overlap processing of these sectors 1 and 2.

That is, when the last address value set pulse (waveform (I)) is output based on the count value from the blanking counter 11 and set in the address generation circuit 10, the sector 2 data input to the memory 4 next Sector 1 data (waveform (J)) is read out from the memory 4 at a timing that is six clocks earlier than (waveform (Q)). Note that A1~ and B1~ of the waveforms (J) and (Q) are data numbers assigned only to the data in the overlapping portion for convenience. Therefore, ideally A1 and B1 are the same data.

However, since still video is recorded on the recording medium 1 after performing analog modulation, errors occur compared to digital data, and the specified time of each area of the audio data format allows an error of approximately ±100 ns. Since the address value of the overlap area between adjacent sectors is determined from the start flag and end flag, A1 and B1 do not necessarily match. Therefore, in this embodiment, when performing overlap processing, the overlap areas between adjacent sectors are compared to find matching points where the data match, and the shifted data state of the overlap areas of the two sectors is corrected. then memory 4
The next sector data is stored.

The data comparison method for the overlap area is as follows. In other words, the comparison is sector 1 data (J)
A7, A8, and A9 of are latched with three types of data latch pulses (waveforms (K), (L), (M)), and the latch data (waveforms (N), (O), (P)) are The data is retained and the three data and sector 2 data (waveform (Q)
) is latched and compared with data delayed by one clock. Comparisons are made between A7 and B1 to B13, A8 and B2 to B14, and A9 and B3 to B15, and the comparison results show that the three adjacent data of sector 2 data are A7 of sector 1 data (waveform (J))
, A8, and A9, it is determined that the overlapping areas of sector 1 and sector 2 overlap at that part,
The address value from which sector 1 data was read is corrected by the number of clocks by which the data in sectors 1 and 2 are deviated.

The deviation between sector 1 and sector 2 can be corrected within the range of ±m clocks, and the sector 1 data is set in advance so that the data A7 of sector 1 has the same timing as the data B1 of sector 2. Since a comparison is made, correction can be easily performed by returning the address value read from sector 1 back in the range of 0 to 2×m. The obtained correction amount is held by the overlap comparison data latch signal (waveform (R)) and subtracted from the address value. Correction is performed by setting the data thus obtained in the counter of the address generation circuit 10 at the timing of the address value correction pulse (waveform (S)).

The overlap data comparison is performed at the front of the overlap, and at the rear, the overlap-corrected data of sector 2 is written to the memory 4 to overwrite the data of sector 1. This overwriting basically involves writing over the same data again in the overlap area, but this is achieved by shifting the address value when correcting the overlap difference between sectors 1 and 2. Since the data to be written in sector 2 changes depending on the amount of correction, such writing is performed so that sectors 1 and 2 are always stored in the memory 4 as continuous audio data.

[0041] The processing of sectors 3 and 4 is
By performing the same overlap process as above, the audio data of sectors 1 to 4 are stored in the memory 4 in a continuous state.

Since the valid audio data of sector 1 is stored in the memory 4 starting from address "0", if the address counter is reset to "0", read out in order and inputted to the D/A converter 3, Played as continuous analog audio output. On the other hand, the address value of the memory where the last valid audio data in the track is stored can be determined using the final address value used for overlap processing at the end of sectors 1 to 3. Easy to play. Furthermore, it is easy to repeatedly reproduce the audio data of the same track, and this can be achieved by resetting the counter of the address generation circuit 10 to "0" when the address value of the memory 4 becomes the final address value of valid audio data. .

Next, a specific embodiment of the overlap processing circuit 7 and address correction circuit 9 of the audio signal reproduction circuit explained in FIG. 1 will be described. FIG. 5 is a block diagram showing a specific embodiment of the data comparison circuit configured in the overlap processing circuit 7 of FIG. In the same figure, 21
24 is a D flip-flop (hereinafter referred to as DF/F) circuit, 25 is a data comparator, and 26 is an AND circuit.

Next, the operation of the circuit shown in FIG. 5 will be explained. That is, when comparing the data of sector n and sector (n-1), if n is "2", as described in the explanation of the operation of the circuit in FIG. 1, the sector 1 data (waveform (J ))
A7, A8, and A9 of 1 are latched with three types of data latch pulses (waveforms (K), (L), and (M)), and those three data and sector 2 data (waveform (Q)) are latched. Compare clock-delayed data. Therefore, the sector 2 data is latched by the D-F/F circuit 24, and the sector 1 data is generated by shifting the data by one clock in the D-F/F circuit 21 (waveforms (K), (L), ( M)), the D-F/F circuit 22 has a data comparison period A7,A
The data of 8 and A9 are held and input to the comparator 25. The three comparators 25 compare whether the data of sector 2 matches each of A7, A8, and A9 of sector 1,
If they match, "1" is output, and if they do not match, "0" is output.

The comparison result shows that the three adjacent data of sector 2 data are A7 and A8 of sector 1 data (waveform (J)).
, A9, it is determined that the overlapping areas of sectors 1 and 2 overlap at that part, so
The D-F/F circuit 23 delays the comparison results by two clocks for the data corresponding to A7 and one clock for the data corresponding to A8, and inputs them to the AND circuit 26, so that three adjacent pieces of data match. determine whether there is.

For example, if the comparator 25 determines that A7 and B1, A8 and B2, and A9 and B3 match, then A9 and B3 match.
A is sent to the AND circuit 26 at the clock timing when the
Since the comparison results of 7 and B1, A8 and B2, and A9 and B3 are input, "1" is output from the AND circuit 26 as the comparison result of the data comparison circuit. In this case, B2 and B1 and B3 on both sides of it match, which means that B2 and A8 in the overlap area are determined to be the same data.

FIG. 6 is a circuit diagram showing a specific embodiment of comparator 25 shown in FIG. In the same figure, 31 is EX
-NOR circuit, 32 to 46 are AND circuits, and 47 is an OR circuit. DA8 to DA3 and DB8 to DB3 are input data to be compared. In the system of this embodiment, data is processed in 8 bits, but the data comparison in the overlap part is performed by converting the audio signal read out as an analog signal from the recording medium 1 into a digital signal using the A/D converter 2. Since this is done using data, an error occurs, so the upper 6 bits are used. Note that DA8 and DB8 are the most significant bits.

Next, the operation of the circuit shown in FIG. 6 will be explained. The EX-NOR circuit 31 determines whether the DA data and DB data match in their respective bits. Since data comparison is to determine whether DA data and DB data are the same, all EX-NOR circuits 31 are "1".
”, it can be seen that the DA data and DB data match. However, if you make a judgment based on this alone, for example, the data will contain "10000000" and "10000".
011", the difference between the data is 3 steps, but the lower 2 bits are not used for comparison data, so it is judged that they match, and "10000000" and "0
1111111'' is input, the difference between the data is only one step, but it is determined that they do not match, and variations in determination occur depending on the input data. In the circuit of FIG. 6, to prevent this from happening, AND
Circuits 32 and 33 are used together with EX-NOR circuit 31.

That is, the AND circuit 32 determines that the DA data is "0".
”, the DB data is “1”, and the AND circuit 33 detects from each bit that the DA data is “1” and the DB data is “0”. In this embodiment, it is possible to compare data in which a carry occurs in one step from these detected data within a permissible range.

[0050] D where the above-mentioned carry occurs
The combination of A data and DB data may be as shown in the table of FIG. In the figure, X represents unspecified data, but it is assumed that the DA data and DB data to be compared match. By determining that the data combinations shown in FIG. 7 match, D
The error between the A data and the DB data has a maximum tolerance of 7 steps.

In the circuit of FIG. 6, the AND circuit 36 is
Based on the "1" output from the EX-NOR circuit 31, it is detected how many bits from the higher order the data match. Further, the AND circuit 34 receives “1” from the AND circuit 32.
” output, the data from the lowest bit to
It is detected whether the DA data is "0" and the DB data is "1". Further, the AND circuit 35 determines, depending on the "1" output from the AND circuit 33, the data from the lowest bit to the lowest bit is "1" for DA data and "0" for DB data.
” is detected. These AND circuits 34~
36 output, EX-NOR circuit 31 and AND circuit 32
, 33 are combined by AND circuits 37 to 46 to determine whether the combination of DA data and DB data shown in FIG. Outputs "1" representing "1".

FIG. 8 is a block diagram showing a specific embodiment of matching point detection and address correction in overlap processing according to the present invention. In the same figure, 51 is a matching point detection circuit that determines the optimal overlap matching point from data from the data comparison circuit shown in FIG. 53 is a latch circuit that holds the address correction amount, and 54 is a subtracter.

Next, the operation of the circuit shown in FIG. 8 will be explained. That is, the comparison data serially sent from the data comparison circuit has sector 1 data (waveform (
J)) A7, A8, A9 and sector 2 data (waveform (Q
)), and if multiple matching points are detected, it is necessary to determine the optimal matching point. Therefore, the matching point detection circuit 51 converts the comparison data into parallel data, prioritizes the comparison data, and determines the optimum point for overlapping the overlap area. The output from the matching point detection circuit 51 is obtained as 12-bit data, and the encoder circuit 52 determines a memory address where the sector 2 data (waveform (Q)) overlaps the sector 1 data (waveform (J)) at the optimal point. Convert to a 4-bit address correction value as obtained. The obtained correction value is held by the latch 53, subtracted by the subtracter 54 from the address value used to read sector 1 data of the memory 4, and the obtained correction address value is input to the counter of the address generation circuit 10. By setting, the address value for writing sector 2 data is supplied to the memory 4.

FIG. 9 is a circuit diagram showing a specific embodiment of the matching point detection circuit 51 shown in FIG. In the same figure, 6
1 is a D-F/F circuit, and 62 and 63 are AND circuits. Next, the operation of the circuit shown in FIG. 9 will be explained. That is, the comparison data serially sent from the data comparison circuit is obtained for 13 points as described in the explanation of FIG. By inputting it, it is converted into parallel data, and the optimal point is determined at the same timing. Sector 1 and sector 2 with ideal overlap area
When read from the recording medium, A8 of sector 1 data (waveform (J)) and B8 of sector 2 data (waveform (Q)) shown in FIG. 3 overlap. Therefore, in the circuit of FIG. 9, when multiple matching points are detected and it is necessary to prioritize the comparison data, the matched data of B8 is given the highest priority,
Priority is given to B8, B7, B9, and B10 in the order of points that depart from the ideal state one by one.

The AND circuit 62 is configured to detect the point with the highest priority among the comparison data in which a matching point has been detected.
” appears only once in any bit. Also, if no matching point is detected in the comparison data, it is not known where the overlap will match, so the AND
The circuit 63 is forced to determine that the overlap between sectors 1 and 2 is at an ideal position. Correction 1 to correction 12, which are the output terminal names in FIG. 9, represent the correction amounts to be subtracted, and are connected to the encoder 52 so that the output from each terminal can obtain the correction amounts.

As described above, according to the present invention, since a comparison circuit is used for overlap processing, accurate processing can be performed, and errors caused by differences in data recording conditions can also be absorbed. Furthermore, since sectors are connected to form a continuous signal when writing to the memory, once the data is written to the memory, the same track can be repeatedly reproduced by a simple read operation of the memory.

On the other hand, an audio signal recorded over a plurality of tracks can be easily reproduced as a continuous audio signal by using a plurality of circuits of the present invention. That is,
As shown in FIG. 10, the recording medium 1, A/D of the circuit of FIG.
The converter 2 and the D/A converter 3 are common, and two systems of other digital parts are provided as a reproducing circuit 1 and a reproducing circuit 2.

First, two track data are reproduced by the reproduction circuit 1.
, are stored in the memory of the reproduction circuit 2 as continuous audio as described above. For reproduction, the first track data is first read from the memory of one of the reproduction circuits and inputted to the D/A converter 3, and when it enters the last overlap area of the data, it is read from the first overlap area of the second track data. is read out from the memory of the other playback circuit with a delay of 6 clocks, compared using the same overlap processing circuit that processes between sectors, and after address correction is applied to the memory data of the second track, D/A conversion is performed. The read data from the memory input to the device 3 is switched to the second track data. By performing overlap processing in this way, 2
Audio data spanning two tracks can also be played back as a continuous audio signal. Furthermore, if audio data continues in the third and subsequent tracks, the third track data is stored in the memory where the first track was stored while the second track is being played back from the memory. By repeating such operations, it is possible to reproduce continuously without any limit on the number of tracks.

As described above based on the embodiments, according to the present invention, since overlap processing is performed using a comparator circuit, good continuously reproduced audio can be obtained regardless of the data recording state. In addition, processing for continuous audio is performed simply by correcting the address when writing to memory, so
No complicated reading control from memory is required during playback.

[0060]

[Effects of the Invention] As detailed above, according to the present invention,
It is possible to provide an audio signal reproducing circuit that correctly processes an overlap area regardless of the data recording state without using any memory other than the memory for storing audio data.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the basic circuit configuration of an audio signal reproducing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the circuit in FIG. 1;

FIG. 4 is a waveform diagram for explaining the operation of the flag detection circuit in FIG. 1;

FIG. 5 is a block configuration diagram showing a specific example of a data comparison circuit configured in the overlap processing circuit in FIG. 1;

FIG. 6 is a circuit diagram showing a specific example of the comparator in FIG. 5;

FIG. 7 is a table showing combinations of DA data and DB data in which carry occurs.

FIG. 8 is a block configuration diagram showing a specific example of matching point detection and address correction.

FIG. 9 is a circuit diagram showing a specific example of the matching point detection circuit in FIG. 8;

FIG. 10 is a block configuration diagram showing the basic circuit configuration of an audio signal reproduction circuit according to another embodiment of the present invention.

FIG. 11(A) is a diagram showing a signal arrangement for one sector for explaining the audio data format, and FIG. 11(B) is a diagram showing the arrangement of sectors in one track.

FIG. 12 is a diagram showing a data state when audio data divided into four sectors is converted into continuous playback audio data.

FIG. 13 is a block configuration diagram of a conventional audio signal reproduction circuit including overlap processing.

[Explanation of symbols]

1... Recording medium, 2... Analog/digital (A/D) converter, 3... Digital/analog (D/A) converter, 4
...Memory, 5...Microcomputer (microcomputer), 6
...Memory control circuit, 7.Overlap processing circuit, 8..Flag detection circuit, 9..Address correction circuit, 10..Address generation circuit, 11..Blanking counter.

Claims (7)

[Claims] Claim 1: An audio signal that reproduces as continuous audio an audio signal that is divided into a plurality of data blocks and recorded on a recording medium, which has overlap areas that contain the same data as adjacent data blocks before and after each block. In the reproduction circuit, a memory temporarily stores audio signal data read from a recording medium, and when writing the read audio data to the memory, data in an overlap area of data blocks of adjacent audio data is stored. Write control means for controlling data writing to the memory so that data in the overlap area is overwritten at the same address in the memory based on the comparison result, and sequentially reading audio signal data from the memory. 1. An audio signal reproducing circuit comprising: output means for reproducing and outputting an audio signal divided into a plurality of data blocks as a continuous audio signal. 2. Each data block of the audio signal recorded on the recording medium includes, in addition to the overlap area,
The write control means includes an address generation circuit that generates address data to be supplied to the memory, a start flag that represents the beginning of the data block, and an end flag that represents the end of the data block. a flag detection circuit that detects a flag; a comparison circuit that compares data in an overlap region of adjacent data blocks; a match point detection circuit that determines a match point in the overlap region from data of the comparison circuit; an address correction circuit that corrects address data when writing or reading from the memory using data from the point detection circuit, and reads the audio signal divided into the plurality of blocks and recorded on the recording medium from the recording medium. When writing audio signal data to the memory, the address correction circuit corrects the address data of the memory to process the overlap area, and converts the audio signal data divided into a plurality of data blocks into continuous data. 2. The audio signal reproducing circuit according to claim 1, wherein the audio signal reproducing circuit converts and stores the converted audio signal in a memory. 3. The data input to the comparison circuit is
(n-1), including the audio signal data of the nth block read from the recording medium and the audio signal data of the (n-1)th block temporarily stored in the memory after being read from the recording medium; )-th block audio signal data is read from the memory and compared so that the overlap area is m clocks earlier than the n-th block audio signal data, and the address correction circuit performs the matching check. 2. The audio signal reproducing circuit according to claim 1, further comprising a subtracter for determining an address correction amount based on data from the output circuit and subtracting the correction amount from the address data generated by the address generation circuit. 4. An audio signal that reproduces as continuous audio an audio signal that has been divided into a plurality of data blocks and recorded on a recording medium, and has overlap areas that contain the same data as adjacent data blocks before and after each block. In the reproduction circuit, first and second memories alternately and temporarily store block groups consisting of a predetermined number of data blocks among the audio signal data read from the recording medium, and the read audio When writing data to each memory, data in the overlap area is overwritten at the same address in the memory based on the data comparison result of the overlap area of adjacent audio data data blocks.
A write control means for controlling writing of data to the first and second memories, and switching of the memory to be read from one memory to the other memory in accordance with detection of coincidence of overlapped areas of data in both memories. Then, the first
The audio signal divided into a plurality of data blocks is converted into a continuous audio signal by reading blocks of audio signal data alternately from the second memory and sequentially reading data blocks of audio signal data from each memory. An audio signal reproducing circuit comprising: an output means for reproducing and outputting an audio signal. 5. In addition to the overlap area, each data block of the audio signal includes a start flag representing the beginning of the data block and an end flag representing the end of the data block, and the write control means comprises: , a plurality of address generation circuits that generate address data to be supplied to each memory, a flag detection circuit that detects the start flag and the end flag, and a comparison circuit that compares data in an overlap area of adjacent data blocks; A match point detection circuit that determines a match point in the overlap area from data of the comparison circuit, and an address correction circuit that corrects address data when writing or reading a memory using data from the match point detection circuit. The output means is characterized in that the address correction circuit corrects the address data of the memory to process the overlap area and reproduces the audio signal divided into a plurality of blocks as a continuous audio signal. The audio signal reproducing circuit according to claim 4. 6. The comparison circuit is configured to determine that the data match even if there is an error within a certain value between the data to be compared, and the comparison circuit is configured to determine that the data match even if an error within a certain value occurs between the data to be compared. 6. The audio signal reproducing circuit according to claim 2, wherein the audio signal reproducing circuit sends the data to the matching point detection circuit only when the data is continuous over n adjacent pieces of data. 7. The matching point detection circuit is configured to perform processing by assigning a priority order to perform optimal overlap processing on the data from the comparison circuit. 5. The audio signal reproducing circuit according to 5.