JPH04310676A - Data separator for FDD - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data separator for an FDD (floppy disk drive) that generates a window signal that separates a read data signal from a floppy disk drive into a data pulse and a clock pulse.

0002

[Prior Art] Generally, in an FDC (floppy disk controller), in order to correctly separate the MFM recording read data signal sent from the FDD into clock pulses and data pulses, a window is installed that follows the frequency change of the read data signal. Requires an FDD data separator that generates a signal. This data separator generally uses an analog VFO (variable frequency generator) to generate a window signal, but this analog VFO data separator is easily affected by the external environment, such as filter characteristics changing depending on temperature, and external components ( It had drawbacks such as requiring resistors and capacitors. Therefore, in recent years, digital VFO data separators made up of only logic circuits have become known. As shown in FIG. 9, this type of data separator has a phase comparison circuit 1, a bias generation circuit 2, a digital VFO 3, and a data separation circuit 4. In order to generate a window signal that follows the frequency change of the read data signal, As shown in FIG. 10, the phase comparison circuit 1 detects the center of the half cycle of the window signal and the phase of the read data signal, changes the bias value of the bias generation circuit 2 based on the comparison result, and uses this bias value to change the bias value of the bias generation circuit 2.
It has a PLL configuration that controls the oscillation frequency of O3 and feeds back the output of this digital VFO3 as a window signal to the phase comparator circuit 1. In the data separator configured in this way, by controlling the oscillation frequency of the digital VFO 3, an accurate window signal locked (synchronized) to the read data signal can be obtained. By the way, in the shift selector format generally used in FDD, as shown in FIG.
NC) field, and this sink field is “0”.
Since it consists of 0" data, it uses only clock pulses at equal intervals (3.5 inch 2DD, 4u in MFM recording method)
s) becomes the pulse train. Therefore, the interference from the front and rear pulses becomes equal, and no "shift" called peak shift occurs in the peak portion of their combined waveform. Therefore, by locking to the pulse train of this sync field, you can quickly lock in and obtain an accurate window signal.

0003

[Problem to be solved by the invention] If the window signal is locked to the pulse train of the sink field in this way,
Although it is possible to cause the window signal to quickly follow the read data signal, conventionally even faster tracking could not be expected. Therefore,
The present applicant previously proposed in Japanese Patent Application No. 2-246206 (title of invention: FDD data separator) that the phase difference between the read data signal and the window signal within the sink field period of the read data signal. We proposed a technology that controls the oscillation frequency of a digital VFO by taking into account the period of the read data signal and enables high-speed tracking of the window signal. In this type of device, after quickly locking in to the sync pattern and obtaining an accurate window signal, the window signal for the read data signal is adjusted to follow only the periodic fluctuations caused by the redundant rotational fluctuation elements of the disk. It is necessary to switch the tracking method. An object of this invention is to quickly lock in to the sync pattern of the read data signal and achieve accurate control by switching the tracking method of the window signal for the read data signal between when the sync field of the read data signal is detected and when the data field is detected. After obtaining the window signal, it is possible to follow only redundant rotational fluctuations of the disk.

0004

[Means for Solving the Problems] The means of the present invention are as follows. (1) The digital VFO generates a window signal for separating the read data signal from the FDD into data pulses and clock pulses. (2) The phase comparator circuit detects the read data signal sent from the FDD within the sink field period.
Compare the phases of the read data signal and the window signal. (3) The period measurement circuit calculates the period of the read data signal sent from the FDD within the sink field period.
Measure the period of the read data signal. (4) A bias value generation circuit generates a bias value to be input to the digital VFO from the output results of the phase comparison circuit and period measurement circuit. In this case, digital VF
By changing the bias value input to O, the oscillation frequency of the window signal output from the digital VFO is controlled. Here, the bias value generating circuit includes a first arithmetic circuit that corrects the output value of the period measuring circuit based on the comparison result of the phase comparator circuit, and a first arithmetic circuit that corrects the output value of the period measuring circuit based on the comparison result of the phase comparator circuit, and when detecting the sink field of the read data signal. A switching circuit that directly outputs the value as a bias value input to the digital VFO, and when detecting a data field, switches and outputs a corrected value using the bias value at the time of sink field detection as a reference value, and the bias output from this switching circuit. A holding circuit that temporarily holds a value, and a second arithmetic circuit that corrects a bias value in this holding circuit based on a comparison result of a phase comparator circuit and uses this correction value as an input value to a switching circuit. Become.

[0005]

[Operation] The operation of the means of the present invention is as follows. Now, within the synch field period of the MFM recording read data signal sent from the FDD, the phase comparator circuit compares the phase of the read data from the FDD and the window signal, and the period measurement circuit compares the phase of the read data signal from the FDD with the window signal. Measure the period of a signal. In this case, phase comparison and period measurement are performed for each period of the window signal. Here, in the bias value generation circuit, the first arithmetic circuit corrects the output value of the period measurement circuit based on the comparison result of the phase comparison circuit. Then, the switching circuit outputs the value corrected by this first correction circuit. This output is temporarily held in a holding circuit and then input to a digital VFO. This controls the oscillation frequency of the window signal, so that the window signal follows the read data signal at high speed. On the other hand, in the bias value generation circuit, when a data field is detected, the second arithmetic circuit corrects the bias value at the time of synchronization field detection held in the holding circuit as a reference value based on the comparison result of the phase comparison circuit. , this correction value is given to a switching circuit, and the correction value outputted from this switching circuit is temporarily held in a holding circuit and then input to a digital VFO. This controls the oscillation frequency of the window signal, so that the window signal follows the read data signal at a low speed. Therefore, by switching the tracking method of the window signal for the read data signal between when detecting the sync field of the read data signal and when detecting the data field, it is possible to quickly lock in to the sync pattern of the read data signal.
After obtaining an accurate window signal, only redundant rotational fluctuations of the disk can be followed.

[0006]

[Embodiment] An embodiment will be described below with reference to FIGS. 1 to 8. FIG. 1 is a block diagram showing the overall configuration of an FDD data separator. The data separator for FDD includes an oscillator 11, a synchronization circuit 12, a follow-up control circuit 13, and a data separation circuit 14, and the follow-up control circuit 13 includes a phase comparison circuit 13-1, a period measurement circuit 13-2, and a bias value generation circuit. 13-3 and a digital VFO 13-4. In addition, the bias value generation circuit 13-3
are the phase correction circuit 13-11 and the frequency correction circuit 13-12.
, selector 13-13, and register 13-14. The oscillator 11 oscillates and outputs the basic clock signal CK of 16 MHz, and the synchronizing circuit 12, the phase comparator circuit 13-1, the period measuring circuit 13-2, and the digital VFO 13
-4, applied to the data separation circuit 14.

A read data signal RD sent from the FDD is input to the synchronization circuit 12, and this read data signal RD is synchronized with the basic clock signal CK and has a width of one basic clock cycle (62.5 ns). The read pulse DATA having the same value is applied to the phase comparison circuit 13-1, the period measurement circuit 13-2, and the data separation circuit 14.

The phase comparator circuit 13-1 compares the phase of this read pulse DATA with the half-cycle signal Q4 of the window signal WD output from the digital VFO 13-4, and as a result, the read pulse DATA, that is, the read data When the signal RD is in a delayed phase or in phase, it outputs a low-level code signal +/-, and when it is in a leading phase, it outputs a high-level code signal +/- to generate a bias value. The bias value generating circuit 13-3 is supplied to the bias value generating circuit 13-3 by outputting the arithmetic control signal ADCK.
give to

The period measuring circuit 13-2 receives the read pulse DA.
Every time TA is input, its period is measured, and the difference value from the predetermined reference period (4 us) is calculated as the basic clock 1.
5-bit data F0 with period (62.5ns) as weight
~F4 and applied to the bias value generation circuit 13-3.

Next, in the bias value generation circuit 13-3, the code signal +/
- indicates phase correction circuit 13-11, frequency correction circuit 13-1
given to 2. Here, the phase correction circuit 13-11 corrects the output data F0 to F4 of the period measurement circuit 13-2 according to the code signal +/- from the phase comparison circuit 13-1, and
Bit data Q0 to Q4 are given to selectors 13-13. In this case, the phase correction circuit 13-11 is the phase comparator circuit 1.
When the code signal +/- from 3-1 is at a low level, "1" is added to the output data F0 to F4 of the period measurement circuit 13-2, and when the code signal +/- is at a high level, the period is measured. The data F0 to F4 are corrected by subtracting "1" from the output data F0 to F4 of the circuit 13-2. Also,
The frequency correction circuit 13-12 corrects the input data D0 to D7 from the register 13-14 according to the code signal +/- from the phase comparison circuit 13-1, and converts the input data D0 to D7 into 8-bit data S0 to S.
4 is given to the selector 13-13. In this case, the frequency correction circuit 13-12, like the phase correction circuit 13-11,
When the code signal +/- from the phase comparator circuit 13-1 is at a low level, "1" is added to the input data D0 to D7, and when the code signal +/- is at a high level, the input data D0 to D7 is added to the input data D0 to D7.
Data D0 to D7 by subtracting "1" from 7
Make corrections.

Selector 13-13 is frequency correction circuit 13
-12 input data A0 to A7 and phase correction circuit 13
-11 to selectively switch and output input data B0 to B7 from the floppy disk controller (FD
The external control signal C from C) is input as a select signal, and when this external control signal C is at high level, the input data A0 to A7 from the frequency correction circuit 13-12 are output, and the external control signal C is When at low level, input data B0 to B7 from the phase correction circuit 13-11 is output. Note that the external control signal C is a signal that becomes a low level when a sync field of a read data signal is detected, and becomes a high level when a data field is detected.

Registers 13-14 are selectors 13-13
It temporarily holds the output data X0 to X7 from the selector 13-13 according to the arithmetic control signal ADCK from the phase comparison circuit 13-1.
, that is, input data D0 to C7 to registers 13-14.
hold. Data Q0 to Q7 held in this register 13-14 are input to a frequency correction circuit 13-12, corrected, and provided to the register 13-14.

The digital VFO 13-4 has a binary counter with load, etc., and its 8-bit data Q
Among 0 to Q7, bit output Q5 is bias value generation circuit 1
The bit output Q4 is output as a window signal having a frequency corresponding to the bias value from 3-3, and the bit output Q4 is output as a half-cycle signal of the window signal (window half-cycle signal). Here, the window signal is the data separate circuit 1
4, etc., and the window half-cycle signal Q4 is sent to the phase comparison circuit 13-1 as a feedback signal.

Note that the data separation circuit 14 inputs the read pulse DATA from the synchronization circuit 12 to the digital VFO 1.
Data pulse D based on the window signal from 3-4
P and clock pulse CP.

Next, the operation of this embodiment will be explained with reference to FIGS. 2 to 8. First, the read data signal RD is synchronized with the basic clock signal CK by the synchronization circuit 12, and is sent to the data separation circuit 14 as well as the phase comparator circuit 13-1 as a pulse signal DATA having a width of one period of the basic clock.
It is sent to the period measurement circuit 13-2. Then, the phase comparison circuit 13-1 operates as shown in the time chart of FIG.

The phase comparator circuit 13-1 compares the rising edge of this pulse signal DATA with the rising edge of the window half-cycle signal Q4 output from the digital VFO 13-4, and compares their phases. As a result, as shown in FIG. 2A, the pulse signal DATA (read data signal RD)
If the phase is delayed with respect to the window half-period signal Q4,
The phase comparison circuit 13-1 receives the code signal + in synchronization with the detection.
/- is set to low level, and the window half-cycle signal Q4
A one-shot pulse arithmetic control signal ADCK is output in synchronization with the falling edge of . Further, as shown in FIG. 2B, when the pulse signal DATA has a lead phase with respect to the window half-cycle signal Q4, the phase comparator circuit 13-1 sets the code signal +/- to high level in synchronization with the detection, and also A one-shot pulse arithmetic control signal ADCK is output in synchronization with the falling edge of the half-cycle signal Q4. Note that when the phases of the pulse signal DATA and the window half-cycle signal Q4 are synchronized, the output of the arithmetic control signal ADCK cannot be obtained (see FIG. 2C).

On the other hand, the period measuring circuit 13-2 operates as shown in the time chart of FIG. Period measurement circuit 13-2
measures the period of the pulse signal DATA every time it arrives, and outputs data F0 to F4 in which the difference from the reference period is weighted by one period of the basic clock. For example, the period measurement circuit 13-2
is when the measurement period is equal to the reference period (reference period = 4 us
), "00H (hexadecimal representation, the same applies hereinafter)" is output as data F0 to F4 (see FIG. 3A). Also, Figure 3
As shown in B, when the measurement period is one period of the basic clock longer than the basic period (basic period + 1 = 4us + 62.
5ns), "01H" is output as data F0 to F4. Conversely, as shown in Figure 3C, if the measurement period is one basic clock period smaller than the reference period (basic period -
1=4us-62.5ns), "1FH" is output as data F0 to F4.

FIG. 4 shows the relationship between the difference value with respect to the reference period and the corresponding output data F0 to F4, with the difference value "-15" to "+15" centered on the difference value "±0"
The output state of data F0 to F4 within the range shown in FIG. Accordingly, the bias value generation circuit 13-3 uses the output data F0 to F4 of the period measurement circuit 13-2 as a reference in accordance with the sign signal +/- from the phase comparison circuit 13-1 and the calculation control signal ADCK. A correction is applied and the bias value is applied to the digital VFO 13-4.

FIG. 5 is a time chart showing the operation of the bias value generation circuit 13-3, especially the operation when detecting the sink field of the read data signal (hereinafter referred to as high-speed tracking mode). An example is shown in which "00H" is output as data F0 to F4. Note that the period measurement circuit 13-2 outputs data "00H" when the measurement period and the reference period are equal, as described above. Here, in high-speed tracking mode, FD
The external control signal C output from C is at a low level, and the selector 13-13 adjusts the input data B0 to B7 from the phase correction circuit 13-11 according to this external control signal C.
is output and given to registers 13-14. First, Figure 5A
When the pulse signal DATA has a delayed phase with respect to the window half-period signal Q4 as shown in FIG. The arithmetic control signal ADCK is output. Then, the phase correction circuit 13-1
1 is "1" in the output value "00H" of the period measurement circuit 13-2
is added and output, and the value "01H" is sent to the selector 13-
13 to the register 13-14 and held in the register 13-14 in response to the arithmetic control signal ADCK from the phase comparator circuit 13-1. Therefore, the outputs Q0 to Q7 of the register 13-14 are "01H". ” and is given to the digital VFO 13-4. In this case, in the selector 13-13, the lower 3 bits of the input value B0, B
1 and B2 are fixed at "0" (low level), and as a result, the lower three bits BLD0, BLD1, BLD21, and BLD3 of the input value of the digital VFO 13-4 are also fixed at "0". Therefore, in the high-speed tracking mode, the bias value input to the digital VFO 13-4 is BD0
, BD1, . . . BD4 are 5-bit data.

Further, as shown in FIG. 5B, when the pulse signal DATA is in a leading phase with respect to the window half-period signal Q4, the code signal +/- from the phase comparator circuit 13-1 becomes high level, and the phase comparator circuit 13 -1 outputs an arithmetic control signal ADCK. Then, the phase correction circuit 13
-11 is output by subtracting "1" from the output value "00H" of the period measuring circuit 13-2, and the value "FFH" is given to the register 13-14 via the selector 13-13, and the phase comparator circuit It is held in the register 13-14 in response to the arithmetic control signal ADCK from the register 13-1. Therefore, the outputs Q0 to Q7 of the register 13-14 become "FFH" and are applied to the digital VFO 13-4.

Note that when the phase of the pulse signal DATA is synchronized with the window half-cycle signal Q4 as shown in FIG. 5C, the sign signal +/- from the phase comparator circuit 13-1
becomes a low level as in the case of a delayed phase, but the output of the arithmetic control signal ADCK is not obtained from the phase comparator circuit 13-1, and as a result, the contents held in the register 13-14 do not change, and the contents held in the register 13-14 do not change. 14 outputs the data "00H" as is.

As a result, the digital VFO 13-4 generates a window signal with a frequency corresponding to the data from the bias value generation circuit 13-3, and outputs the window signal to the data separation circuit 1.
4, etc., and also generates a window half-period signal Q4 and provides it to the phase comparator circuit 13-1 as a feedback signal.

FIGS. 6 and 7 show the output states of the window signal and the window half-cycle signal Q4 that change according to the amount of change when the bias value is set to "00000" as the reference value in the high-speed tracking mode. 6 shows a case in which the amount of change in the bias value increases by plus "1" relative to the reference value, and FIG. 7 shows a case in which the amount of change in the bias value decreases by minus "1" relative to the reference value. ing. Here, the standard period (4 us) of the window signal is 16
This corresponds to 64 clocks in terms of the MHz basic clock signal CK, and therefore 1 of the window half-period signal Q4.
The period is 32 clocks, and the 1/2 period corresponds to 16 clocks, but the number of clocks within one period of the window signal increases or decreases as shown in the figure, depending on the amount of change in the bias value with respect to the reference value. At this time, the digital VFO 13-4 maintains the duty ratio of 50% of the window signal and the window half-cycle signal Q4 and maintains the accuracy of one cycle of the basic clock with respect to the amount of change in the bias value. Increase or decrease the cycle (number of clocks).

In this way, in the high-speed tracking mode, the above-described operation is repeated every cycle of the window signal to correct the bias value and control the oscillation frequency of the window signal.

Next, the operation when detecting the data field of the read data signal (hereinafter referred to as low-speed follow-up mode) is shown in FIG.
Explain with reference to. When entering low-speed tracking mode, FDC
The control signal C from the circuit becomes high level, and the period measurement circuit 1
3-2, the frequency correction circuit 13-12 becomes effective instead of the phase correction circuit 13-11. That is, selector 13
-13 outputs the input value from the phase correction circuit 13-11 instead of the phase correction circuit 13-11 when the control signal C switches from low level to high level. At the moment the mode is switched, the bias value in the high-speed tracking mode is held in the register 13-14 as it is, and correction is applied using this bias value as a reference value. Note that the lower 3 bits of the bias value in high-speed tracking mode are “0”.
" and is treated as a 5-bit bias value, but in low-speed tracking mode it is released and the bias value is treated as 8-bit data.

FIG. 8 is a time chart showing the operation of the frequency correction circuit 13-12, taking as an example the case where the input values D0 to D7 of the frequency correction circuit 13-12 are "00H". First, as shown in FIG. 8A, when the pulse signal DATA has a delayed phase with respect to the window half-period signal Q4, the code signal +/- from the phase comparison circuit 13-1 becomes a low level, and the phase comparison circuit 13- From 1, calculation control signal A
DCK is output. Then, the frequency correction circuit 13-1
2 adds “1” to its input value “00H” and outputs it,
The value "01H" is given to the register 13-14 via the selector 13-13, and is held in the register 13-14 in response to the arithmetic control signal ADCK from the phase comparison circuit 13-1. Therefore, the output Q of registers 13-14
0 to Q7 become "01H", and the frequency correction circuit 13-1
2 and input to the digital VFO 13-4.

Further, as shown in FIG. 8B, when the pulse signal DATA is in a leading phase with respect to the window half-period signal Q4, the code signal +/- from the phase comparison circuit 13-1 becomes high level, and the phase comparison circuit An arithmetic control signal ADCK is output from 13-1. Then, the frequency correction circuit 13-12 subtracts "1" from its input value "00H" and outputs it, and the value "FFH" is given to the register 13-14 via the selector 13-13, and the phase comparison circuit 13
-1 in register 1 in response to the arithmetic control signal ADCK from
It is held at 3-14. Therefore, register 13-1
4 outputs Q0 to Q7 become "01H" and are fed back to the frequency correction circuit 13-12, and the digital VFO 13
-4 is input.

Note that, as shown in FIG. 8C, when the phase of the pulse signal DATA is synchronized with the window half-cycle signal Q4, the code signal +/
- becomes a low level as in the case of the delayed phase, but the output of the arithmetic control signal ADCK is not obtained from the phase comparator circuit 13-1, and as a result, the contents held in the registers 13-14 do not change, and the register 13-1 -14 outputs the data "00H" as is. In this manner, in the low-speed tracking mode, the above-described operation is repeated for each period of the window signal to correct the bias value and control the oscillation frequency of the window signal.

[0029] In the above embodiment, the digital VFO 13-
Although the bias value input to 4 is set to 8 bits, the number of bits is arbitrary, and the phase correction circuit 13-11 and the frequency correction circuit 13-12 are configured to perform "±1" correction. ±n (n: an integer greater than or equal to 1)" correction may be used, and the value thereof is arbitrary, and by changing each value, the tracking state of the window signal also changes.

[0030]

According to the present invention, by switching the tracking method of the window signal for the read data signal between when detecting the sync field of the read data signal and when detecting the data field, it is possible to quickly lock onto the sync pattern of the read data signal. After inputting and obtaining an accurate window signal, it is possible to follow only the redundant rotational fluctuations of the disk.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data separator for FDD.

FIG. 2 is a time chart for explaining the operation of the phase comparator circuit 13-1 shown in FIG. 1.

3 is a time chart for explaining the operation of the period measuring circuit 13-2 shown in FIG. 1. FIG.

FIG. 4 is a diagram showing the relationship between a difference value with respect to a reference period and output data F0 to F4 in the period measuring circuit 13-2 shown in FIG. 1;

5 is a time chart for explaining the operation of the phase correction circuit 13-11 shown in FIG. 1. FIG.

6 is a diagram showing the operation of the digital VFO 13-4 shown in FIG. 1, and showing the output state of a window signal etc. that changes as the bias value increases with respect to its reference value.

7 is a diagram showing the operation of the digital VFO 13-4 shown in FIG. 1, and showing the output state of a window signal etc. that changes as the bias value decreases with respect to its reference value.

8 is a time chart for explaining the operation of the frequency correction circuit 13-12 shown in FIG. 1. FIG.

FIG. 9 is a block diagram of a conventional data separator for FDD.

FIG. 10 is a diagram for explaining a phase comparison between a read data signal and a window signal in the conventional example.

FIG. 11 is a diagram for explaining the FDD format in the conventional example.

[Explanation of symbols]

11 Oscillator 12 Synchronous circuit 13 Follow-up control circuit 13-1 Phase comparison circuit 13-2 Period measurement circuit 13-3 Bias value generation circuit 13-4 Digital VFO 13-11 Phase correction circuit 13-12 Frequency correction circuit 13-13 Selector 13-14 Register 14 Data separation circuit

Claims (1)

[Claims] 1. A digital VFO that generates a window signal for separating a read data signal from an FDD into a data pulse and a clock pulse; a phase comparison circuit that compares the phases of the read data signal and the window signal; a period measuring circuit that measures the period of the read data signal; and a bias value generating circuit that generates a bias value that is input to the digital VFO from the output results of the phase comparator circuit and the period measuring circuit, and is input to the digital VFO. Digital VFO by changing the bias value
A data separator for FDD that controls the oscillation frequency of a window signal output from the bias value generating circuit, wherein the bias value generating circuit includes a first circuit that corrects the output value of the period measuring circuit based on the comparison result of the phase comparing circuit. an arithmetic circuit, and a value corrected by the first arithmetic circuit when detecting a sink field among the read data signals, and outputs the value corrected by the first arithmetic circuit to the digital VF.
There is a switching circuit that directly outputs the bias value that is input to O, and when detecting the data field, switches and outputs the corrected value using the bias value at the time of sink field detection as the reference value, and temporarily outputs the bias value that is output from this switching circuit. A holding circuit for holding and correcting the bias value in this holding circuit based on the comparison result of the phase comparison circuit,
A data separator for an FDD, comprising: a second arithmetic circuit that uses this correction value as an input value of the switching circuit.