JPH04310695A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for increasing the access time of a semiconductor memory device.

0002

2. Description of the Related Art FIG. 3 shows a circuit configuration from a sense amplifier circuit for amplifying a data signal read from a memory cell to an output data buffer circuit in a conventional semiconductor memory device. In the figure, 1 is a pair of data lines connected to memory cells, 2 is a sense amplifier, 3 is an inverter, 4 is a block selector signal, 5 is an output data buffer circuit, 6 is a data bus line, and Q1 and Q2 are switching transistors. be.

A memory cell matrix of a conventional large-capacity semiconductor memory device is divided into a plurality of memory cell array blocks, which are operated in divided manner. For example, if the memory cell matrix of a semiconductor memory device with an n-bit data output configuration is divided into m blocks, there are n data buses and (m×n) sense amplifiers in FIG. I will do it. Therefore, the number of sense amplifiers connected to one data bus line is m.

Next, the operation of a conventional semiconductor memory device will be explained using FIG. 3. Minute signal data read from the memory cell selected by the address signal input to the semiconductor memory device is input to the sense amplifier 2 from the data line pair 1, and is sent to the data bus line 6 as an amplified data signal.
is output to.

As shown in FIG. 3, the memory cell matrix is m
In a semiconductor memory device that is divided into blocks, each block performs a divided operation, so a signal (hereinafter referred to as 4 (referred to as a block selector signal) is input to switching transistors Q1 and Q2. Therefore, even if m sense amplifiers are connected to one data bus line, the sense amplifiers operate in division, so the outputs of the sense amplifiers do not conflict with each other simultaneously on the data bus line, and the selected sense The output of the amplifier is input to the output data buffer circuit 5, and can be output as the output of the semiconductor memory device.

[0006]

[Problems to be Solved by the Invention] Conventional semiconductor memory devices are configured as described above, so as the storage capacity becomes larger and the number of divided blocks increases, it becomes difficult to use a single data bus. As the number of sense amplifiers connected to the data bus line increases and the output capacitance of the sense amplifiers increases, the capacitance component distributed on the data bus line increases. As the capacity of the data bus line increases, the time required for transmitting a signal through the data bus line increases, which poses a problem in that speeding up access time is hindered.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device which can reduce the capacitance distributed on a data bus line and has a fast access time.

[0008]

[Means for Solving the Problems] A semiconductor memory device according to the present invention has m memory cell matrices (where 4≦m
; m is an integer) memory cell blocks, each block is divided and operated, and the output data configuration is n-bit (however, 1≦n; n is an integer), the minimum unit of storage. In a semiconductor memory device having (m×n) sense amplifiers that amplify a small amplitude data signal read from a memory cell, for each bit of an n-bit output data configuration, a sense amplifier (however, 2≦a; a is an integer) data bus lines are provided, and the outputs of the (m/a) aforementioned sense amplifiers are input to each of the a data bus lines, and from the signal for selecting the sense amplifier. A switching means controlled by the formed signal is provided to select one of the a data bus lines for the 1 bit and input it to the output means for forming output data of the semiconductor memory device. It is.

[0009]

[Operation] The semiconductor memory device according to the present invention has the above configuration, and although the output data configuration n is bits, it has (a×n) data bus lines, so the memory If the number of divisions of the cell matrix is m, the number of sense amplifiers connected to one data bus line is (m/a). Since a=1 in the conventional configuration and a≧2 in the present invention, the number of sense amplifiers connected to one data bus line is reduced. Therefore, by using the data bus configuration of the present invention, it is possible to reduce the output capacitance of the sense amplifiers distributed on the data bus line, and it is possible to obtain a semiconductor memory device with high-speed access time. .

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIG. In Figure 1, the output data structure is n
A configuration diagram around a data bus line of a semiconductor memory device in which a memory cell matrix is divided into m blocks (4≦m; m is an integer) with bits (1≦n; n is an integer). Among the n data bus configurations, only one set of data bus configurations is omitted.

In FIG. 1, 1 is a data line pair connected to a memory cell, and 2 is a data line pair 1 that inputs minute signal data read from a memory cell selected by an address signal input to a semiconductor memory device. However, there are (m×n) sense amplifiers for amplification in the semiconductor memory device of this embodiment. 3 is an inverter,
4 is a block selector signal B0, B1,...Bm-1, Bm for selecting a memory cell array block in order to inactivate the sense amplifier 2 of the memory cell array block in which data is not read; 5 is an output data buffer circuit, 6 is a first data bus line, 7 is a second data bus line, 8a is a data bus selector signal D1, 8b is a data bus selector signal D2, Q1
, Q2 are switching transistors controlled by the block selector signal 4, Q3 and Q4 are switching transistors controlled by the data bus selector signal D1 8a, and Q5 and Q6 are switching transistors controlled by the data bus selector signal D2 8b.

FIG. 2 shows a specific circuit configuration example of a data bus selector signal generation circuit for generating the data bus selector signal shown in FIG.
The same reference numerals as in FIG. 1 indicate the same or corresponding parts, and 9a indicates block selector signals B0, B2,...Bm-3, Bm
-1 as input and outputs the result of ORing these as the data bus selector signal D1;
9b is a block selector signal B1, B3,...Bm-2,
This is an OR circuit which takes Bm as an input and outputs the result of ORing these as a data bus selector signal D2.

Next, the operation will be explained. Small amplitude signal data read from a memory cell of a semiconductor memory device is input to a sense amplifier 2 from a data line pair 1 in FIG. 1, and becomes an amplified data signal.

Further, only the output of the sense amplifier 2 selected by the block selector signal 4 is brought into conduction with the first data bus line 6 or the second data bus line 7 and transmitted through the switching transistors Q1 and Q2.

In this embodiment, there are two data bus line groups, a first and a second data bus line group, for one set of output data configuration, and (m/2) of the m sense amplifiers are connected to the first data bus line group.
data bus lines 6, and the remaining (m/2) data bus lines 7 are input to another second data bus line 7. The first data bus line 6 is connected to a switching transistor Q3 to which a data bus selector signal 8a is input.
, Q4 to the output data buffer circuit 5, and the second data bus line 7 is input to the output data buffer circuit 5 through switching transistors Q5, Q6 to which the data bus selector signal 8b is input.

Therefore, the output of the selected sense amplifier 2 is transmitted through one of the two data bus lines 6 and 7, and is transmitted from the data bus line 6 or 7 to the switching transistor Q3, Q4 or Q5.
, Q6 to the output data buffer circuit 5.

Furthermore, data bus selector signals 8a, 8b
is formed by the OR logic of the block selector signal 4 as shown in FIG. This allows the selected sense amplifier output to be transmitted to the output data buffer circuit 5.

According to this embodiment, when the memory cell matrix is divided into m blocks, each block operates in a divided manner, and the output data structure is n-bit structure, the memory cell matrix is divided into m blocks. In a device equipped with (m×n) sense amplifiers 2 that amplify small amplitude data read from a memory cell, which is the minimum unit, two sense amplifiers are used for each bit of the n-bit output data configuration. Data bus lines 6 and 7 are provided, and the outputs of (m/2) sense amplifiers 2 are connected to each of the data bus lines 6 and 7, and a block selector signal 4 for selecting the sense amplifier 2 is provided.
Data bus selector signal 8 formed from the OR logic output of
Since one of the two data bus lines is selected by a and 8b and inputted to the output data buffer circuit 5, the number of sense amplifiers 2 connected to the data bus line is The number can be reduced from the conventional m number to (m/2). Therefore, the capacitance components of the sense amplifiers distributed on the data bus line can be reduced, and the time for transmitting signals on the data bus line can be shortened, thereby making it possible to speed up the access time of the semiconductor memory device.

In the above embodiment, an example was shown in which two data bus lines were provided for each bit of the n-bit output data configuration, but this is not limited to two; More than one may be provided. In this case, it is possible to further speed up the access time.

[0020]

[Effects of the Invention] As described above, according to the present invention, the data bus line configuration of a semiconductor memory device is divided, and the data bus line is configured to operate separately. The number of sense amplifiers used can be reduced, and the capacitance component of the sense amplifiers distributed on the data bus line can be reduced. Therefore, with this,
This has the effect of enabling high-speed data transfer and providing a semiconductor memory device with high-speed access time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration around a data bus of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a data bus selector signal generation circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration around a data bus of a conventional semiconductor memory device.

[Explanation of symbols]

1 Data line pair 2 connected to memory cell
Sense amplifier 3 Inverter 4 Block selector signal 5 Output data buffer circuit 6 First data bus line 7 Second data bus line 8a Data bus selector signal 8b Data bus selector signal 9a OR circuit 9b OR circuit Q1 Switching transistor Q2 Switching transistor Q3 Switching transistor Q4 Switching transistor Q5 Switching transistor Q6 Switching transistor

Claims (1)

[Claims] [Claim 1] There are m memory cell matrices (however,
When the memory cell block is divided into 4≦m (m is an integer) memory cell blocks, each block operates separately, and the output data configuration is n bits (1≦n; n is an integer).
A sense amplifier (m x n
) semiconductor memory device, for each bit of the n-bit output data configuration, a semiconductor memory device (where 2≦
a; a is an integer) data bus lines are provided, each of which receives the outputs of the (m/a) sense amplifiers, and is controlled by a signal formed from a selection signal for selecting the sense amplifier. A semiconductor device characterized in that a switching means is provided, and the switching means selects one of the a data bus lines and inputs the selected one to an output means for forming output data of the semiconductor memory device. Storage device.