JPH043112A - Display control device and display control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, a display that is updated by applying an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a display control device for a display device including a display element that can maintain a state.

[Prior Art] Generally, a display device is connected to an information processing system or the like as an information display means that performs a visual display function of information. CRTs are widely used as such display devices, and FIG. 7 shows an example of a display control device for a CRT connected to such an information processing device.

In the figure, 1 is an address bus driver, 2 is a control bus driver, and 3 is a data bus driver, each of which is connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3; 6 is a driver for data transfer between the display control device and the CRT; and 7 is the CRT.

The video memory 5 is composed of a dual-port DRAM (dynamic RAM), and display data is directly written therein. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on the CRT 7.

That is, when writing display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is applied to the memory controller 9 via the control bus driver 2, and this signal is arbitrated with a data transfer request signal or a refresh request signal applied from the CRTC 8. Accordingly, when the CPU accesses memory, the memory controller 9 to the address selector 10
An address selection signal is given to the address driver 1, and the access address for data writing from the CPU is given to the address driver 1.
and is applied to the video memory 5 via the address selector 1o. Along with this, the video memory 5 has the following information:
A DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are applied. This causes the display data to be written into the video memory 5.

On the other hand, the CRT7 display indicates that the CRTC8 gives a synchronizing signal to the driver 6, and in accordance with the synchronizing signal, the CRT
This is executed by C8 providing a data transfer request signal to the memory controller 9 and a data transfer address to the address selector 10.

First, a data transfer request signal is arbitrated by the memory controller 9, and in response, an address selection signal is given from the memory controller 9 to the address selector 1o. A DRAM control signal is applied to the video memory 5 from the memory controller 9, thereby executing a data transfer cycle.This data transfer cycle is as follows:
The process is to transfer data in units of lines (corresponding to rasters on the front screen) from the video memory 5 to the shift register in the video memory 5, and one data transfer cycle transfers data from one line to several lines to the shift register. can be transferred to

The display data transferred to the shift register is sequentially shifted/read out from the register by a serial port control signal from the CRTC 8 applied to the video memory 5, and output to the CRT 7 for display. The reading of display data from the video memory 5 and the accompanying display are performed line by line from the top to the bottom corresponding to the display area, and within each line, the reading is carried out in a fixed order from the left end to the right end. This is performed by a so-called full refresh operation.

In this way, in the case of CRT display control, the CPU's writing operation to the video memory 5 and the reading and displaying operation of display data from the video memory 5 by the CRT controller 8 are executed independently.

In the case of a display control device for a CRT as described above, the writing of display data to the video memory 5 for changing display information and the operation of reading display data from the video memory 5 and displaying the data are independent. Therefore, there is no need to consider display timing or the like in the program of the information processing system (it has the advantage that desired display data can be written at any timing).

On the other hand, however, since a CRT requires a certain length in the thickness direction of the display screen, its overall volume becomes large, making it difficult to downsize the entire display device. Moreover, this impairs the degree of freedom in using an information processing system using such a CRT as a display, ie, the degree of freedom in terms of installation location, portability, etc.

A liquid crystal display (hereinafter referred to as LCD) can be used to compensate for this point. That is, according to the LCD, the entire display device can be made smaller (particularly thinner). Some of these LCDs include the above-mentioned ferroelectric liquid crystal (FLC).
A display device using a liquid crystal cell (hereinafter referred to as FLCD: FLC display)
One of its features is that its liquid crystal cell maintains its display state against the application of an electric field. Therefore, when driving an FLCD, unlike a CRT or other liquid crystal display, there is a time margin in the cycle of continuous refresh drive of the display screen, and apart from the continuous refresh drive, Partial rewriting drive that updates the display state of only the changed portion on the display screen becomes possible. Therefore, such a FLCD can have a larger screen than other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC molecules therein are oriented in a first stable state or a second stable state depending on the direction of electric field application, and the electric field is It maintains its orientation even when cut. Due to such molecular bistability of FLC, FLCD has memory properties. Details of such FLCs and FLCDs are described in, for example, Japanese Patent Application No. 76357/1983.

[Problems to be Solved by the Invention] However, when an FLCD having the above-mentioned advantages is used as a display device of an information processing system by display control similar to the above-mentioned CRT, the time required for the display update operation of the FLC is relatively short. For example, cursor, character input,
In some cases, it was not possible to follow changes in display information such as Suflorol, which required the display to be immediately rewritten.

On the other hand, in order to perform this process by taking advantage of the FLCD's ability to partially rewrite, the information processing system must provide information to identify this process. Although there are configurations that do this, in order to realize the above-mentioned partial rewriting drive on the display screen, the control program in the information processing system must be significantly changed.

The present invention has been made based on the above-mentioned viewpoint, and can be implemented without significantly changing the software of the information processing system.
It is an object of the present invention to provide a display control device such as an FLCD that is compatible with RT.

Another object of the present invention is to provide a display control device that can realize optimal image quality by effectively utilizing the storage property of display states in FLCDs and the like.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a display control device for a display device that can partially change the display state of pixels, in which the display of the entire screen of the display device is updated. The present invention is characterized in that it includes means for time-sharingly alternating a period in which the display contents are updated and a period in which only the portion in which the display contents are changed is updated.

[Function] According to the present invention, by providing a means for time-sharingly performing alternately a cycle of sequentially rewriting the entire screen and a cycle of rewriting a portion of the screen accessed on the host side such as CPLI, etc. It is possible to maintain a constant display update speed (refresh rate) for the entire screen without having to identify whether data is to be partially written in response to commands, etc., and it is also possible to display rewritten data immediately. Become.

(Hereafter, extra white) [Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of the entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, 11 is a C that controls the entire information processing system.
Po, 12 is a system bus consisting of an address bus, a control bus, and a data bus; 13 is a main memory used for storing programs and as a work area;
4 is a DMA controller (Djrect) that transfers data between the memory and the I10 device without going through the CPUI1.
Memory Access Controller,
(hereinafter referred to as DMAC), 15 is Ethernet (XERO
LAN (local network) 1 by Company X) etc.
LAN interface between 6, 17 is ROM, S
I10 device for connecting the Ilo 4m1 device consisting of RAM, R5232C specification interface, etc. 18 is a hard disk device, 19 is a floppy disk device, 20 is a hard disk device 18 and a floppy disk device 19
21 is a high-resolution printer such as a laser beam printer or an inkjet printer; 22 is a printer interface for the printer 21; 23 is a keyboard for inputting characters such as letters and numbers; 24 is a keyboard for inputting characters such as letters and numbers; A mouse is a pointing device; 25 is an interface for the keyboard 23 and the mouse 24; 26 is an FLCD (FLC display) that can be constructed using a display device disclosed in Japanese Patent Application Laid-Open No. 63-243993 by the present applicant, for example; 27 is a FLCD interface for FLCD2B.

FIG. 2 shows an FLC as an embodiment of the display control device of the present invention.
2 is a block diagram showing an example of the configuration of a D interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. The address data from the CPL III is given from the address bus driver 31 to one input section of the memory controller 40 and the address selector 35, and is selectively given to the FIFO memory 36 or 37 by switching the first switch S1. and memorized. That is, these memories 36 and 37 (hereinafter referred to as FIFO (A) and FIFO (A), respectively)
BJ) is a FIFO (First In First Out) memory that reads data in the order in which it is written, and the address data written in these memories 36 and 37 can be selectively read out by switching the second switch S2. It will be done.

Address data read from these memories 36 or 37 and address data from an address counter 38, which will be described later, are selectively applied to the other input section of the address selector 35 by switching the third switch S3. The address counter 38 generates address data for refreshing the entire screen line-sequentially, and the timing of generation of the address data is controlled by the synchronization control circuit 39. This synchronous control circuit 3
9 also generates switching control signals for the switches Sl, S2, and S3 and a data transfer request signal to a memory controller 40, which will be described later.

Control signals from the CPU II are given from the control bus driver 32 to the memory controller 40, which generates control signals for the sampling counter 34, address selector IO, and video memory 4, which will be described later. . The sampling counter 34 performs a counting operation based on the step signal from the memory controller 40, and the synchronous control circuit 39
0 control signal is generated.

Further, the address selector 35 is connected to the memory controller 4
Based on the control signal from 0, the address selector 3
One of the two address data given to the input section 5 is selected and given to the video memory 41.

The video memory 41 stores display data.
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads display data via the data bus driver 33.

The display data written in the video memory 41 is transferred to the FLCD 26 via the driver receiver 42 and displayed. Further, the driver receiver 42 is a FLCD
The synchronization signal from No. 26 is applied to the synchronization control circuit No. 39. F
The LCD 26 includes a temperature sensor 2 that detects the temperature of the FLC.
6a is included.

Further, setting data, which will be described later, from the CPU II is provided to the synchronization control circuit 39 via the data bus driver 43. Further, the output signal of the temperature sensor 26a is transferred to the CPL III via the data bus driver 44.

In the above configuration, when the CPU II changes the display, the video memory 4 corresponding to the desired data rewriting is
1 address signal is given to the memory controller 40 via the address bus driver 31, where the CPU II
Arbitration is performed between the memory access request signal and the data transfer request signal from the synchronization control circuit 39. When the CPU accessing side obtains the right, the memory controller 40 switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 4J. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, CPU access address 2
0 is stored in FIFO (A) 36 or FIFO (B) 37 via switch S1, and is used when transferring display data, which will be described later. In this way, the method of accessing display data seen from C:PUll is no different from the case of the CRT described above.

It also reads data from the video memory 41 and displays it on the FLCD.
26, a data transfer request is generated from the synchronization control circuit 39 to the memory controller 40, and the address counter 38 or FIFO side address address selector 3 is sent as the address to the video memory 41.
5 to 8 is selected, and the memory controller 4
By generating a control signal for data transfer from 0, data at the corresponding address is transferred from the memory cell to the shift register, and is output to the driver 42 by the control signal of the serial port.

The synchronization control circuit 39 performs a cycle and CP in which the screen is completely refreshed line by line in units of multiple lines based on the horizontal synchronization signal H3YNC from the FLCD 2B.
A timing is generated to alternately generate a partial rewrite cycle in which the line accessed by UI 1 is rewritten. Here, the full refresh cycle means that rewriting is performed sequentially downward from the top line (first line) on the display screen, and when it reaches the bottom line, it returns to the first line and rewrites again. It is something that is repeated. In addition, an access line rewriting cycle means that the CPU 1. This rewrites the line accessed from l.

In this way, basically, in this example, the operation of sequentially refreshing the entire screen of the FLC display 26 and the operation of changing the display contents (rewriting the line accessed by CPIJII) are performed at different times. The division is performed alternately, but it is also possible to set the repeat synchronization of these operations and the time ratio of these operations within one cycle, and the operation period of line rewriting (partial rewriting) can be set by the CPU.
The number of lines accessed by 11 is adjusted accordingly.

First, the basic operation of this example in which refresh operation and line rewriting operation are performed alternately in a time-sharing manner will be explained using FIG. Here, we set the refresh cycle to 4.
An example will be shown in which the access line rewriting cycle is performed in units of three lines, with each line as a unit.

In FIG. 3, REE/AC5 is a timing that causes a full refresh cycle and an access line rewrite cycle to occur alternately, and when it is "1" it is a full refresh cycle and when it is "0" it is a timing that causes the access line rewriting cycle to occur alternately. Indicates a rewrite cycle. Further, ``■'' represents the time of the full refresh cycle and the time of the rewriting cycle of the T-divided access line. In this example,
Although T:T=4:3, an optimal value can be selected depending on the required refresh rate, etc.

That is, by increasing the ratio of T, the refresh rate can be increased, and by increasing the ratio of T, the responsiveness of partial changes can be improved. This aspect will be described later.

To explain the states of FIFD(A) 3B and FIFO(B) 37, when switch S1 is connected to FIFO(A) 3B side (state A/B = 1), CPLI
The address of the line accessed by II is FIFO (A)
36 samples and stored. On the other hand, when switch S1 is connected to FIFO (B) 37 side (A/1
1i=O), the line address accessed by the CPU II is stored in the FIFO (B) 37. Also, when switch S2 is connected to FIFO (A) 3B side (
A/B=1), the address stored in the FIFO (A) 36 is output, and the switch S2 is set to the FIFO (B) 37.
When connected to the side (A/N=O), FIFO (B
) 37 is output.

One refresh of the entire screen is completed, and the FLCD26
outputs the vertical synchronization signal VSYNC, or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the 0th line, and the FLCD 26
The count is sequentially increased to "1", "2", and "3" for each horizontal synchronization signal H3YNC given via the synchronization control circuit 39. During this time, lines L1, L2 .
When the address of L3 is accessed, switch Sl is set to F.
Since it is connected to IFO (A) 36, Ll, L2
．． The address of L3 is stored here and then switch S
2 is connected to FIFO (A) 36, Ll, L
2. The address of L3 is output from here, and the output lines are Ll, L2 . L3 is selected. Here, switch S
The switching signal 3 is the RFF/AC from the synchronous control circuit 39.
S, and in the line access cycle, FIFO(A), FIFO(
B) side.

At this time, switch S1 is set to FIFO (B) 37
Since the access address is connected to the FIFO (B) 37 side, the access address is stored on the FIFO (B) 37 side. REF/AC3 is “1”
Then, the switch S3 is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In Figure 3, after the line output of L3, "4", "5", "6", and "7" which are the continuation of the previous cycle are displayed.
line is output. The above operation is repeated in the same way, but the reason for preparing two FIFOs is that one can sample the memory accessed address and the other can output the sampled address at the same time. In other words, the address sampling period is from the start of output of the access line of the other FIFO until the end of the full refresh cycle, and after the end of the full refresh cycle, the address sampled in the previous sampling period is output. At the same time as the access line rewrite cycle begins,
The address sampling period for the other FIFO will begin.

As described above, in the basic operation of this example, refresh cycles and line rewrite cycles are alternately repeated, and the third
In the figure, the repetition period is Ta:
Although the explanation has been made assuming that T = 4 = 3, in this example, the environmental conditions such as temperature, the type of data to be displayed, or even F
The ratio between T and T5 can be changed depending on the refresh rate required depending on the difference in the display device material of the LCD. That is, the ratio of T (corresponds to the number of lines M in one refresh cycle; that is, T, = MX (
By increasing J (SYNC period), the refresh rate can be improved, and a good display state can be obtained, for example, even when the response of a low-temperature special FLC element is low or when displaying an image. On the contrary, T5
(corresponds to the number of lines N in one partial rewrite cycle; that is, T = N x (HSYNC period))
By increasing the value, it is possible to increase the responsiveness of partial display changes, and it is possible to cope with cases where the refresh rate does not need to be high, such as when the temperature is high or when displaying characters such as letters.

Furthermore, in this embodiment, by making it possible to set the number of lines in the repetition cycle, it is possible to more finely change the refresh cycle and the partial rewrite rate, thereby achieving more fine-grained optimization. For example, if you need or want to give priority to the refresh rate, if you set the number of lines in the repetition period to 40 lines and set it to 4:1, the total refresh rate will be 32
The access lines can be rewritten for 8 lines. Also, if you can or want to give priority to partial rewriting, if you set the number of lines in the repetition cycle to 10 lines and set Ta:Tb = 3:2, perform full refresh 2 for 6 lines and rewrite access lines for 4 lines. It can be carried out.

Furthermore, in this embodiment, within the range of the number of lines for partial rewriting set in this way, the actual number of lines for partial rewriting performed between refresh cycles is determined according to the number of lines accessed by the CPU II and the line access state. Try adjusting P. That is, the CPUI
TI dynamically depending on the number of lines accessed by l,
By adjusting the time, for example, wasteful in-rewrite cycles when the CPU II is not frequently accessed are eliminated, and the refresh rate is improved. This makes it possible to dynamically optimize the relationship between motion followability and refresh rate.

This can be done, for example, according to the rules shown in the table below.

In the example shown in Table 1, T5 changes depending on the number of access lines by the time from line 0 to line 10.

If the ratio of Tb is small (the refresh rate increases, and if the ratio of T is large the refresh rate decreases), Since a limit value is set as above, it is possible to maintain a refresh rate higher than the set value.In other words, since the ratio of T:T is changed depending on the number of accessed lines, it is dynamically optimized. This means that the timing of partial rewriting can be adjusted, and the refresh rate can be further improved.

FIG. 4 shows the signal REF/A that determines the refresh cycle and partial rewrite cycle by performing the above settings and adjustments.
An example of the internal configuration of the synchronous control circuit 39 for outputting C5 is shown.

Here, C is a count value by the sampling counter 34, M is a signal indicating a value corresponding to the number of lines within one refresh cycle, which is set from the CPU II side via the data bus controller 43 according to conditions such as temperature, Similarly, N is a signal indicating a value corresponding to the number of lines within one partial rewriting cycle.

390 is a group of tables storing P values as shown in Table 1 corresponding to the given N values (Nl, . . . , Nnl) (the maximum P value in each table is Nl).

. . , Nn), and can be configured using, for example, a ROM. 391 receives the count value input from the sampling counter 34,
This is a reference table switching unit that provides a table corresponding to the N value at that time. And with this, memory 3
The value selected from 90 is input to the counter 393 as the number P of transfer lines. Then, the counter 393 counts the synchronization signal H5YNC according to the applied M value and P value, and outputs the signal REF/AC5.

By the way, in this example, even if the same line is accessed more than once in one sampling period, this is counted as one access. That is, if a certain address given in one sampling period is included in the same line as an address already given in that period, the sampling counter 340 is prevented from running, and the address given in a different line is Only count the numbers.

FIG. 5 shows an example of a configuration for controlling the counting operation of such a sampling counter. For example, the memory controller 4
0. Here, 401 is an address latch unit that latches an address input during one sampling period, and 403 is a comparison circuit that compares the input address with the address latched in the address latch unit. The increment signal of the sampling counter 34 is output only when the input address is not on the same line as any of the latched addresses.

In the above, the contents of the address latch unit 401 and the sampling counter 34 may be reset at the end of one sampling period. Further, the operations of each part shown in FIG. 5 may be performed when the CPU 1 writes data to the video memory 41.

Note that even if the address of the same line is accessed multiple times, if the count is performed each time, the configuration shown in FIG. good.

Next, a mode of adjusting the operation period of partial rewriting will be illustrated using FIG. 6.

Similarly to FIG. 3, when one refresh of the entire screen is completed and the FLCD 26 outputs a vertical synchronization signal or a carry occurs in the address counter 38, the address counter 38 is cleared and the next full refresh is started. The line output in each cycle returns to "0" and counts up sequentially to "1", "2", and "3" for each horizontal synchronizing signal H3YNC.

During this time, Ll, L2. L3. L4.
When the address of L5 is accessed, switch S1
IFO (A) Since it is connected to the 36 side, Ll, L
2. L3. L4. L5 address is FIFO (A) 3
6 is stored. Further, the value of the sampling counter 34 indicates "5". When the table corresponding to Table 1 is referred to, if the sampling counter value is "5", it is the output of P=4 lines, so switch S2 is set to FIF.
When connected to O(A) 36, the first four lines Ll, L2 . L3. L4 is output from FIFO (A) 36, and Ll is output as an output line.

L2. L3. L4 is selected. Here, switch S
Since the switching signal No. 3 is given by REF/AC3, the address on the FIFO side is selected as the eight column address at this time.

Also, at this time, since the switch Sl (A/B) is set to "0", the access address is stored on the FIFO (B) 37 side. When REF/AC3 becomes "1", switch S3 switches to the address counter side and continues the previous cycle of the refresh line. In Figure 6, after the line output of L4, 4 and 5 which are the continuation of the previous cycle are shown.
．． 6.7 lines are output.

Here, during the access address sampling period of PIFO (B) 37, the same L6 was accessed only three times, and the sampling counter value was "1", so
In the case of a table corresponding to Table 1, the period of the access address rewrite cycle is "0", and the entire refresh cycle continues. Next FIFO (A) 3
The B access address sampling period is only during the full refresh cycle, but two lines out of the three lines sampled during this period are transferred in the next access address rewriting cycle. Thereafter, similar operations are repeated, but the lines that were not partially rewritten (for example, L5, L6, and 19) will also be rewritten in the refresh cycle.

Next, the operations performed by the above-mentioned parts of the apparatus of this example will be explained.

FIG. 7 shows an example of the operation procedure. First, step 52
At 00A, the CPU 11 reads the detected value of the temperature sensor 26a, and at step 3200B, the optimum M is determined accordingly.
value (the number of lines in the refresh cycle, T,
) and the N value (the number of lines within one partial rewrite cycle, which is the maximum T).

) is set in the synchronization control circuit 39.

Next, in step 5201, the initial states of switches S1 and S2 are set. Here, switch Sl is set to FIF
O (A) Set to 36 side, switch S2 to FIFO (B)
I chose the 37 side, but you can start from either side as long as you decide on either side. In step 5202, the address counter 38 is cleared and its refresh address is set to an initial value, for example "O". Next, step 5203
Then, REF/n is set to "1" so that a full refresh cycle is performed. Also, a counter for counting the number of transfer lines within one refresh or partial rewrite cycle (here, one refresh cycle) is cleared, and the counter value LN is set to "o".

Next, in step 5205, it is determined whether the refresh to the final line is completed and a carry occurs in the address counter (retrace period), and if it is during that period, the process returns to step 5200A. If it is not within the period, wait for HSYNC in step 5206. H.S.
When YNC arrives, the data on the line indicated by the refresh line address is transferred to FLCD2B. In step 5208, it is determined whether the number M of lines to be transferred in one full refresh cycle has been completed, and LN
If it is smaller than M, the process moves to step 5209, the address counter 38 is counted up, and step 5210
Then, LN is incremented by +1 and the process returns to step 3206. This is repeated until M lines are transferred, and since M=4 in the example shown in FIG. 6, steps 5206 to 5 are performed.
The loop of 210 will be repeated four times.

When the transfer of the M line is completed, the number of transfer lines P during the rewriting cycle of the access line obtained from the set N value and the count value C of the sampling counter 34 is referred to in step 5219, and if "O", the access line is The rewrite cycle is omitted, and the process moves to step 5203, where a full refresh cycle is performed again. On the other hand, if P is not "0" in step 5219, the process moves to step 5211 for executing an access line rewrite cycle.

In step 5211, REF/AC5 is set to "O" so that an access line rewrite cycle is performed.

Furthermore, the respective connection states of switch Sl and switch S2 are reversed, and the roles of FIFO address sampling and line address output are reversed. Next, step 5
In step 2i2, in order to count the number of transfer lines during the access line rewriting cycle, the counter value LN is set to "O" again (in step 5213, sampling is performed from either FIFO (A) 3B or FIFO (B) 37). Read the address.

Step 5215 waits for HSYNC to arrive, and if HSYNC arrives, step 3216 transfers the data on the line at the address read earlier to the FLCD 26. Next, in step 5217, it is determined whether the line transfer has been completed for 2912 minutes. That is, if LN is smaller than P, proceed to step 3218, increment LN by +1, and proceed to step 5.
213, and repeat this until the end of 2912 minutes. If P=4, steps 3213-52
18 loops will be repeated four times.

Then, when the P line ends, the process returns to step 5203 to execute the full refresh cycle again.

As described above, the contents of the video memory 41 are displayed during the full refresh cycle from steps 5203 to 5208 and from steps 5211 to 5217.
This is carried out by repeating the rewrite cycle of the access line up to and when a carry occurs in the address counter 38, returning the line of the full refresh cycle to the beginning and initializing the signal. On the other hand, in order to obtain the displayed contents, the CPU II uses the video memory 41 independently of the above display operation.
All you have to do is read or write data from there.

As described above, reading data from the video memory 41 and transferring it to the FLCD 26 does not require command interpretation, and can be constructed with a relatively simple circuit, as well as a graphic processor or the like can be installed to interpret the commands. It can be realized at a lower cost than performing display control, and it is possible to improve performance while reducing the cost of the entire system.

(Second Embodiment) In FIG. 2, FIFO is used as a storage means for sampling addresses, but as shown in FIG. As shown in FIG. 9, it is also possible to discard the old addresses among the sampled addresses and transfer the latest addresses.

Here, only the parts that are different between FIGS. 8 and 9 compared to FIGS. 2 and 6 will be explained.

In FIG. 8, in this example, FIFO (A) 36. PIF
Randomly accessible SR instead of O(B)37
AM(A) 145 and SRAM (B 1146) are provided, and an address controller 147 is provided to control the address of the SRAM.Then, according to the output value C from the sampling counter 34, the number of transfer lines obtained from Table 1, for example. For example, by changing the writing address of the sampling address as “O” → “1”-2”-”3” → “4” → “5”, the number of transfer lines can be increased. If it is 4 lines, SRA
Start reading address from M from “2”, for example “
2"-"3"-"4"→"5". At this time, at the start of the next address sampling period, the write address is returned to "O" and the old address information is discarded. Therefore, it is sufficient to prepare an SRAM with a capacity that can store the minimum necessary information within one cycle.

In the example of FIG. 9, LL, L2 . L3. L4. Among L5,
The latest 4 lines, L2. L3. L4. L5 is transferred in the access line rewrite cycle. Also, the L7. L8. Among L9, the latest two lines, L8. L9 is transferred in the access line rewrite cycle.

In the case of FIFO, reading is performed in the order in which it is written, and there is no need to perform address control from the outside, so it can be configured compactly, but if you want to read the latest information as shown in this example, you can use a dummy read operation. Must be done, SRA
It is easier to control if configured with M. In addition, by appropriately controlling the SRAM address, it can also be operated like a FIFO, and furthermore, for example, in the above example, "5" → "4"
Since it is also possible to read in the reverse direction, such as "→"3"→"2," there is a high degree of freedom in determining the output address relative to the sampled address. In other words, whether the older accessed address has meaning or not, Whether the newer one has more meaning will change depending on the case, and it cannot be said which one is more appropriate, and the read order may also be related to making the hardware configuration more advantageous.
In a configuration using AM, it becomes possible to select what seems appropriate depending on the situation.

(Others) It goes without saying that the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the present invention.

For example, in the above example, ■Basically, refresh cycles and partial rewrite cycles are performed alternately, and ■Also, the repetition period (T, +T,) of these cycles is made variable, and the ratio of both cycles is settable. , (2) In addition, although the partial rewriting cycle is adjusted according to the number of access lines, etc., all of these need not be performed. Further, instead of performing these steps (1) to (2) in a series of sequences, one of the modes may be appropriately selected and executed as desired.

Further, in the above example, a table group of P values each having the set N value as an upper limit was provided, but the relationship between the setting in (1) above and the adjustment in (2) can be determined appropriately. For example, a group of P value tables may be provided in which each set N value is set to a medium value. Further, the table of count value C and P value is made into a single table, and for example, in step 5200A, corresponding to the maximum P value, (
Even if only an appropriate M value is determined, the period of Ta+Tb and the ratio between T and Tl can be changed. Also, instead of providing a sampling counter to count the number of access lines, it is possible to
The number of access lines may be known using flags such as "half" and "empty j."

In addition, on the upper side, C during the retrace period based only on temperature information.
Although the PUII is configured to perform the settings described in ■ above, the timing of the settings can be adjusted as appropriate, and the cpuit
By providing means for performing such processing on the FLC interface 27 side, M,
It may also be one in which P is rewritten. In addition to such temperature information, other environmental conditions may also be considered (
, Instead of this, or in addition to this, display data types such as images and characters may be considered.

Furthermore, one unit of access or display may be one line or may be multiple lines.

[Effects of the Invention] As explained above, according to the present invention, a means is provided for alternately performing a cycle of sequentially rewriting the entire screen and a cycle of rewriting lines accessed from the host side such as the CPU in a time-sharing manner. This makes it possible to maintain a constant refresh rate without having to identify whether data is to be partially written in response to a command or the like, and it is also possible to immediately display rewritten data. Therefore, without changing the software specifications of the system using the FLC display, it is now possible to make the screen display highly responsive to the movements of figures and cursors, and further improve the characteristics of the FLC. It is also possible to perform a good display using the information in minutes. Also, C from the perspective of the system
Compatibility between RT and FLC is also maintained. Moreover, since it is realized with a simple circuit configuration, it is possible to perform high-speed display control at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the entire information processing device incorporating a display control device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an FLCD interface as an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2, FIG. 4 is a block diagram showing an example of the internal configuration of the synchronous control circuit shown in FIG. 2, and FIG. 6 is a timing chart illustrating a mode of adjusting the rewriting operation period of the FLCD LAN interface shown in the second figure; FIG. 8 is a block diagram showing the configuration of an FLCD interface as another embodiment of the present invention, and FIG. 9 is a timing chart for explaining the operation of the FLCD interface shown in FIG. 8. , FIG. 10 is a block diagram showing the configuration of a conventional CRT interface. DESCRIPTION OF SYMBOLS 11... CPU, 12... Address bus, 13... System bus, 14... DMA controller, 15... LAN interface, 16... LAN, 17... I10 device, 18... - Hard disk device, 19... Floppy disk device, 20... Disk interface, 21... Printer, 22... Printer interface, 23... Keyboard, 24... Mouse, 25... Interface, 26...FLCD (FLCD display), 26
a... Temperature sensor, 27... FLCD interface, 31... Address driver, 32... Control bus driver, 33, 43.4
4... Data bus driver, 34... Sampling counter, 35... Address selector, 36... FIFO (A) memory, 37... FIFO (B) memory, 38... Address counter, 39 ... Synchronous control circuit, 40 ... Memory controller, 41 ... Video memory, 42 ... Driver receiver, Sl, S2. S3...Switch, 390...Memory, 391...Reference table switching unit, 393...Counter,...Address latch unit,...Comparison circuit,...SRAM (A),...・SRAM (B), ...address controller. Procedural amendment form) Procedural amendment written August 30, 1990

Claims (1)

[Claims] 1) In a display control device for a display device that can partially change the display state of pixels, a period for updating the display of the entire screen of the display device and updating only the portion where the display content is changed. 1. A display control device characterized by comprising means for time-divisionally alternating periods of time. 2) The display control according to claim 1, wherein during the period of updating the display of the entire screen, pixels from one end of the screen to the other end on a diagonal line are changed in order. Device. 3) The display control device according to claim 1, further comprising means for storing information regarding a portion where the display content is changed for a certain period of time. 4) During a period in which only the portion where the display content has changed is updated, the display state of the pixel is changed in accordance with information about the portion where the display content has changed stored in the storage means. The display control device according to claim 3.