JPH0431133B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a pipeline-controlled information processing device that can input one instruction per cycle, an operand buffer memory and an instruction buffer memory are provided separately so that each can be pipeline-controlled independently. to eliminate read conflicts between operands and instructions.

[Industrial application field]

The present invention relates to an information processing device for pipeline control, and particularly to a pipeline control method for reading operands and instructions.

[Conventional technology]

Pipeline control divides the processing of one instruction into multiple stages (steps), inputs multiple instructions at predetermined cycle intervals, and processes them in parallel to avoid duplication at each stage. This shortens the average processing time.

In general, instruction processing can be broadly divided into instruction reading, instruction decoding, operand reading, and instruction execution, which are further divided into several detailed stages.

In an information processing device using such pipeline control, it is important to pack as many instructions as possible into the pipeline without any blank spaces, and to minimize waiting time.

Conventionally, a cycle pipeline method in which one instruction is input every two cycles is often used for pipeline control. In the case of this two-cycle pipeline method, two cycles are allocated to buffer memory access for high-speed reading of operands or instructions. Designed to avoid conflicts.

On the other hand, due to the recent demand for faster speeds,
One-cycle pipeline type devices have appeared in which one instruction is input in each cycle. In the case of this one-cycle pipeline system, if buffer accesses for operand reading and instruction reading conflict, a wait may occur.

[Problem that the invention seeks to solve]

In the conventional one-cycle pipeline method, if a wait occurs during buffer memory access to read an operand or instruction, the pipeline becomes completely interlocked and the wait time is added to the instruction execution time. , there was a problem of degrading pipeline performance.

[Means for solving problems]

The present invention provides buffer memory access for operands and instructions by separately providing a buffer memory for operands and a buffer memory for instructions in a one-cycle pipeline system, and configuring each access to be controlled by an independent pipeline. This prevents waiting due to contention. For this reason, in addition to the buffer memory, an adder for address calculation and an address conversion buffer are provided separately for operands and for reading instructions.

FIG. 1 is a diagram showing the basic configuration of the present invention. In the figure, 1 is general-purpose register GR, 2 is base register BR, 3 is index register XR,
4 is a displacement register DR, 5 is an adder for operand addresses, 6 is an operand effective address register OEAR, 7 is a buffer memory section for operands O-LBS, 8 is an operand word OWR, 9 is an instruction address register IARA, 1
0 is an instruction address register IARB, 11 is an increment register PFO, 12 is an adder for instruction read address, 13 is a selector, 14 is an instruction effective address register IEAR, 15 is an instruction buffer memory unit I-LBS, 16 is an instruction buffer, 17
represents the instruction word register IWR.

Here, the upper and lower stages of the diagram constitute independent pipelines, and the operand buffer memory section O-LBS7 and the instruction buffer memory section I-LBS15 each constitute an address conversion buffer and a TLB.
(table rutsquaside batshua) and
It includes TAG (tag section).

The instruction to be executed is taken from the instruction buffer 16, decoded in an instruction decode cycle D, and
A portion of the data passes through the general-purpose register GRI, and the base, index, and displacement values of the operand address are set in BR2, XR3, and DR4, respectively.

Operand adder 5 adds the values of BR2, In the case of instruction read access, an instruction effective address is generated and stored in the IEAR 14 via the selector 13.

In the case of operand access, in the next address conversion cycle T, the operand buffer memory section O
- In LBS7, the operand effective address is
Translation from a logical address for virtual storage to a real address is performed in the TLB via an address translation buffer.

Furthermore, in the next buffer cycle B, a TAG reference is made to access the buffer memory.
When a hit occurs, the operand read from the buffer memory is stored in OWR8.

The operand of OWR8 is the next execution cycle E
Then, it is transferred to an arithmetic circuit and processed.

In addition, in the case of instruction read access, IEAR1
Similar address conversion and buffer memory access are performed in the instruction buffer memory unit I-LBS 15 in the T cycle and B cycle for the instruction effective address set to 4, and the read instruction is read out via the IWR 17. It is stored in the instruction buffer 16.

The instruction effective address is stored in either IARA 9 or IAR 10 from the exit of selector 13, and is added with the increment value of PFO 11 (for example, 8 bytes in instruction width) by instruction read address adder 12. The next order of instruction effective address is generated.

[Effect]

According to the present invention, for example, when a branch instruction is executed, a branch destination address is calculated using an adder for operand addresses, and that address is used as an instruction read address, thereby controlling the reading of the branch destination instruction of the branch instruction. The operand pipeline can be completely transferred from the operand pipeline to the instruction read pipeline, and the operand pipeline can be opened for the next instruction.

Conversely, even if the operand pipeline is interlocked due to another reason such as no operand in the buffer memory, by transferring control to the instruction read pipeline, the branch destination instruction can be read quickly. It becomes possible.

〔Example〕

FIG. 2, FIG. 3, and FIG. 4 are flowcharts each showing an example of a pipeline instruction execution control sequence according to the present invention.

The illustrated examples all show processing in which a branch instruction calculates a branch destination address and reads the target instruction. In each figure, 5 is an adder for operand addresses, 9 is an instruction effective address register IARA, 12 is an adder for instruction read addresses, and 15 is an instruction buffer memory section I-
It is LBS. Further, D stands for instruction decoding, A for address calculation, T for address translation, B for buffer access, E for execution, W for writing, and I for instruction address generation.

In the example of FIG. 2, the operand address adder 5 of the operand pipeline calculates the branch destination address of the branch instruction in the A cycle, requests the instruction read pipeline to execute it, and transfers it.
The instruction read pipeline accepts the instruction immediately and its T
In cycle and D cycle, the instruction buffer memory unit I-LBS15 performs address conversion and buffer access, and reads out the branch destination instruction. The read branch destination instruction is unconditionally input into the operand pipeline, but is controlled to be executed only if the branch condition is satisfied in the execution of the previous branch instruction.

In Fig. 3, unlike the case in Fig. 2, a request from the operand pipeline to the instruction read pipeline is not accepted immediately, so the address is temporarily stored in IARA9 in the I cycle, and then the address is returned after one cycle. This is an example in which conversion and buffer access are performed.

In Figure 4, the operand pipeline interlocks in the A cycle of the branch instruction, but the instruction read pipeline does not interlock, so the pre-read of the branch destination instruction is executed, and after the interlock is released, the branch condition is satisfied. This is an example in which the branch destination instruction is executed immediately.

〔Effect of the invention〕

According to the present invention, since the operand pipeline and the instruction read pipeline are separated and can be controlled independently, it is possible to realize complete parallelism between operand access and instruction read access, and to reduce latency. By reducing this, performance can be improved.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of the present invention, Figures 2 and 3.
4 are flowcharts of a pipeline instruction execution control sequence according to an embodiment of the present invention. In Fig. 1, 5...adder for operand address, 7... buffer memory unit for operand O-
LBS, 12...Adder for instruction read address,
15...Buffer memory section for instructions.

Claims (1)

[Claims] 1. In a pipeline control information processing device,
A pipeline for operand control and a pipeline for instruction read control are provided, and each pipeline is independently provided with a buffer memory and address translation buffer for operands, and a buffer memory and address translation buffer for instructions, An adder 5 for calculating an operand address and an adder 12 for calculating an instruction read address are provided independently, and the address calculated by the adder 5 for calculating the operand address and the adder 12 for calculating the instruction read address are provided independently. It has a selection means that selects one of the addresses calculated in and supplies it to the instruction read control pipeline as the instruction read address, and when the instruction is a normal instruction other than a plant instruction, the operand control pipeline and the instruction The pipeline for read control operates independently, and when a branch instruction is input to the pipeline for operand control, the branch destination instruction address is calculated by the adder 5 for calculating the operand address. The branch destination instruction address calculated by the adder 5 for operand address calculation is calculated at the timing of the address calculation of the pipeline for the operand address, and after the calculation by the adder 5, the instruction readout control is performed by the selection means. 1. A pipeline control method characterized in that control regarding subsequent instruction reading is transferred to a pipeline for controlling instruction reading. 2. In claim 1, the branch destination address given to the instruction read control pipeline by the selection means is converted into an address by the instruction address conversion buffer, and then transferred to the instruction read buffer memory. A branch destination instruction is read from a branch destination instruction, and the branch destination address calculated at the address calculation timing by the address calculation adder 5 of the operand control pipeline is read from the branch destination instruction at the address calculation timing. If an instruction read access is requested by passing it to a pipeline for instruction read control, and the pipeline for instruction read control cannot accept the request immediately, the branch destination address is passed to the pipeline for instruction read control. The instruction readout control is performed at a timing after the timing when the branch destination address is temporarily held in the instruction address register 9 provided in the pipeline and passed from the operand control pipeline to the instruction readout control pipeline. The branch destination address held in the instruction address register 9 provided in the instruction pipeline is sent to the address conversion buffer of the instruction read control pipeline, the address is converted, and the branch destination instruction is read from the instruction read buffer memory. A pipeline control method characterized by: