JPH043118A - Display controller - Google Patents

Abstract

PURPOSE:To vary the way of generating addresses by generating the addresses from an address converting means, such as address conversion table. CONSTITUTION:Nearly the irregular addresses are generated from the address converting means, such as address conversion table 44. If the addresses correspond to the scanning lines consisting of plural display elements on, for example, a display screen 26, these lines are nearly irregularly accessed and the display state thereof is refreshed. The address converting means 44 has the plural converting means which are changed according to set information and the temp. information of the display screen 26. The way of generating the addresses is varied by the set information, etc., in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, a display that is updated by applying an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a display control device for a display device including a display element that can maintain a state.

[Prior Art] Generally, a display device is connected to an information processing system or the like as an information display means that performs a visual display function of information. CRTs are widely used as such display devices, and FIG. 7 shows an example of a display control device for a CRT connected to such an information processing device.

In the figure, 1 is an address bus driver, 2 is a control bus driver, and 3 is a data bus driver, each of which is connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3; 6 is a driver for data transfer between the display control device and the CRT; and 7 is the CRT.

The video memory 5 is composed of a dual-port DRAM (dynamic RAM), and display data is directly written therein. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on the CRT 7.

That is, when writing display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is applied to the memory controller 9 via the control bus driver 2, and this signal is arbitrated with a data transfer request signal or a refresh request signal applied from the CRTC 8. Accordingly, when the CPU accesses the memory, the address selector lO is sent from the memory controller 9.
An address selection signal is given to the address driver l, and the access address for writing data from the CPU is given to the address driver l.
and is applied to the video memory 5 via the address selector IO. Along with this, the video memory 5 has the following information:
A DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are applied. This causes the display data to be written into the video memory 5.

On the other hand, the display on the CRT 7 is performed by the CRTC 8 giving a synchronizing signal to the driver 6, and in accordance with the synchronizing signal.
This is executed by C8 giving a data transfer request signal to the memory controller 9 and a data transfer address to the address selector IO.

First, when a data transfer request signal is arbitrated by the memory controller 9 and an address selection signal is applied from the memory controller 9 to the address selector 10 in response, the data transfer address from the CRTC 8 is transferred via the address selector 10. video memory 5. Further, a DRAM control signal is applied to the video memory 5 from the memory controller 9, thereby executing a data transfer cycle. This data transfer cycle is to transfer data in units of lines (corresponding to rasters on the front screen) of the video memory 5 to the shift register in the video memory 5. One data transfer cycle transfers data from one line to several lines. Lines of data can be transferred to the shift register.

Then, the display data transferred to the shift register is sequentially read out from the shift register and output to the CRT 7 for display according to a serial port control signal from the CRTC 8 applied to the video memory 5. The display data is read out from the video memory 5 and the accompanying display is performed line by line from the top to the bottom corresponding to the display area, and within each line, it is performed in a fixed order from the left end to the right end. This is performed by a so-called full refresh operation.

In this way, in the case of CRT display control, the CPU's writing operation to the video memory 5 and the reading and displaying operation of display data from the video memory 5 by the CRT controller 8 are executed independently.

In the case of a display control device for a CRT as described above, the writing of display data to the video memory 5 for changing display information and the operation of reading display data from the video memory 5 and displaying the data are independent. Therefore, there is no need to consider display timing etc. in the program of the information processing system, and there is an advantage that desired display data can be written at any timing.

On the other hand, however, since a CRT requires a certain length in the thickness direction of the display screen, its overall volume becomes large, making it difficult to downsize the entire display device. Moreover, this impairs the degree of freedom in using an information processing system using such a CRT as a display, ie, the degree of freedom in terms of installation location, portability, etc.

A liquid crystal display (hereinafter referred to as LCD) can be used to compensate for this point. That is, according to the LCD, the entire display device can be made smaller (particularly thinner). Some of these LCDs include the above-mentioned ferroelectric liquid crystal (FLC).
There is a display device (hereinafter referred to as FLCD: FLC display) that uses a liquid crystal cell (called Quid Crystal), and one of its features is that the liquid crystal cell maintains its display state against the application of an electric field. be. Therefore, when driving an FLCD, unlike a CRT or other liquid crystal display, there is a time margin in the cycle of continuous refresh drive of the display screen, and apart from the continuous refresh drive, Partial rewriting drive that updates the display state of only the changed portion on the display screen becomes possible. Therefore, such a FLCD can have a larger screen than other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC molecules therein are oriented in a first stable state or a second stable state depending on the direction of electric field application, and the electric field is It maintains its orientation even when cut. Due to such molecular bistability of FLC, FLCD has memory properties. Details of such FLCs and FLCDs are described in, for example, Japanese Patent Application No. 76357/1983.

[Problems to be Solved by the Invention] However, when an FLCD having the above-mentioned advantages is used as a display device of an information processing system by display control similar to the above-mentioned CRT, the time required for the display update operation of the FLC is relatively short. For example, cursor, character input,
In some cases, it was not possible to follow changes in display information such as Suflorol, which required the display to be immediately rewritten.

On the other hand, in order to perform this process by taking advantage of the fact that it is possible to partially rewrite, which is one of the features of FLCD, the information processing system side has to provide information to identify this process. Although there are configurations that do this, in order to realize the above-mentioned partial rewriting drive on the display screen, it is necessary to significantly change the control program in the information processing system.

The present invention has been made based on the above-mentioned viewpoint, and can be implemented without significantly changing the software of the information processing system.
It is an object of the present invention to provide a display control device such as an FLCD that is compatible with RT.

Another object of the present invention is to provide a display control device that can realize optimal image quality by effectively utilizing the storage property of display states in FLCDs and the like.

[Means for Solving the Problem J To this end, the present invention includes a display screen in which a plurality of display elements capable of maintaining an updated display state are arranged, and updates the display based on display data on the display screen. In a display control device for a display device, address generation means generates an address corresponding to each of the plurality of display elements in the order of arrangement of the plurality of display elements, and an address generated by the address generation means. , conversion means for associating addresses corresponding to other display elements different from the display element of the address in a substantially irregular manner, and generating the associated address in response to generation of the address by the address generation means; a plurality of address conversion means, and a method for setting the conversion means used for generating the address from among the plurality of conversion means possessed by the address conversion means according to setting information and/or the temperature of the display screen. a setting means, a storage means for storing display data of the display element corresponding to each of the plurality of display elements;
5. Transfer means for transferring display data corresponding to the display element at the address generated by the conversion means set by the setting means from the storage means to the display device.

[Function] According to the above configuration, a substantially irregular address is generated from the address conversion means such as an address conversion table, so that this address corresponds to, for example, a scanning line made up of a plurality of display elements on a display screen. If so, these lines are accessed almost irregularly and their display state is updated.

Further, the address translation means has a plurality of translation means,
Since these are changed according to the setting information and the temperature information of the display screen, the manner in which addresses are generated can be changed depending on the setting information and the like.

(The following is a margin) [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an FLC display device equipped with a display control device according to an embodiment of the present invention as a display device for displaying various character and image information.

In the figure, ]] is a CPU that executes control of the entire information processing system, 13 is a main memory that stores programs executed by the CPU II and is used as a work area during this execution, and 14 is a main memory that is used as a work area for executing programs without using the CPU 11. A DMA controller (Direc) transfers data between the main memory 13 and the various devices that make up this system.
tMemory Access Control
r, hereinafter referred to as DMAC). 15 is a LAN interface between this system and a LAN (local area network) 16 such as an Ethernet (by fXEROX), and 17 is a ROM, SRAM, R323.
It is an input/output device (hereinafter referred to as Ilo) having a 2C interface and the like.

Various external devices can be connected to Ilo 17.
18 and 19 are a hard disk device and a floppy disk device, respectively, as external storage devices, and 20 is a disk interface for signal connection between the hard disk device 18 and floppy disk device 19 and this system. 21A is a laser beam printer (hereinafter also simply referred to as a printer) capable of relatively high-resolution recording, ZIB is a scanner as an image reading device, and 22 is a printer 21A and a scanner 21B.
A scanner/
It is a printer interface. 23 is a keyboard for inputting various character information, control information, etc.; 24 is a mouse as a pointing device; 25 is a key interface for signal connection between the keyboard 23 and the mouse 24 and this system. 26 is a FLCD as a display control device according to an embodiment of the present invention.
This is an FLC display device (hereinafter also referred to as FLCD) whose display is controlled by an interface 27, and has a display screen using the above-mentioned ferroelectric liquid crystal as its display operation medium. Reference numeral 12 denotes a system bus consisting of a data bus, a control bus, and an address bus for signal connection between the above-mentioned devices.

In the information processing system that connects the various devices described above, the system user generally uses the FLCD2B
Operate while responding to various information displayed on the display screen. That is, external device 2 hard disk 18. connected to LAN 16.11017. floppy disk 1
9. Character 9 image information supplied from the scanner 21B, keyboard 23, mouse 24, etc., and main memory 1
3 and related to the user's system operation are displayed on the display screen of the FLCD 26, and the user edits the information and gives instructions to the system while looking at this display. Here, each of the above-mentioned devices etc. is FL
A display information supply means is configured for C026.

FIG. 2 is a block diagram showing details of the FLCD interface 27.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 45 are data bus drivers, each of which is connected to each bus of the system bus 12. Address data when the CPU I accesses the video memory 41 (described later) for rewriting display contents is provided to one input section of the memory controller 40 and the address selector 35 via the address bus driver 31, and is also provided to the first switch. FIFO (A) memory 36 or FIFO (
B) selectively applied to and stored in memory 37; FIFO (A) memory 36 and FIFO (B) memory 37 (hereinafter simply referred to as "A memory" and "B memory") are FIs in which data is read out in the order in which it is written.
This is a FO (First In First Out 1 memory), and the address data written in these memories 36 and 37 is selectively read out in response to switching of the second switch S2.

Address data read from these memories 36 or 37 and address data for accessing the video memory 41 from an address conversion table 44, which will be described later, are transferred to the third switch S3. The signal is selectively applied to the other input section of the address selector 35 in accordance with the switching. The address conversion table 44 is referred to based on the address from the address counter 38, which increments its value every time one line of the display screen is driven, and its contents are output as address data. The address counter 38 is
As described above, the address is incremented by "1" to generate address data for refreshing the entire display screen, and the timing of generation of the address data is controlled by the synchronization control circuit 39. This synchronization control circuit 39 also generates switching control signals for the switches Sl, S2, and S3 and a data transfer request signal to a memory controller 40, which will be described later. The timing of the signal generation by the synchronous control circuit 39, the switch Sl,
The switching timing of S2 and S3 is controlled in accordance with the horizontal synchronization signal (IsYNc) generated by the FLCD 26 every time one line of the display screen is driven.

A control signal from the CPljl 1 is given to a memory controller 40 via a control bus driver 32, and the memory controller 40 controls a sampling counter 34, an address selector 35, and a video memory 41, which will be described later, according to this control signal. . That is, the memory controller 40 determines the address data by which the CPU II accesses the memory 41 during a predetermined period, and when a different address is accessed, outputs the data to the sampling counter 34, and outputs the data to the sampling counter 34.
This is counted in step 4. This count value is calculated by the synchronous control circuit 3
9, and can be used to determine the ratio of partial rewriting and refresh drive, which will be described later.

The memory controller 40 also arbitrates between the memory access request signal from the CPL III and the data transfer request signal from the synchronization control circuit 39, and switches the output of the address selector 35 accordingly.
One of the two address data applied to the input section of the address selector 35 is selected and applied to the video memory 41.

The video memory 41 stores display data.
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads display data via a data bus driver 33. Video memory 41
The display data written in is read out to the FLCD 26 via the driver receiver 42 and displayed. Further, the driver receiver 42 provides the synchronization signal from the FLCD 26 to the synchronization control circuit 39.

Further, data for setting the ratio of partial rewriting and refresh driving, which will be described later, is provided to the synchronization control circuit 39 via the data bus driver 43. Further, header information regarding display image data, which will be described later, is set in the header register 44A via the data bus driver 45.

The FLC panel 26A of the FLCD 26 is provided with a temperature sensor 26B for detecting its temperature, and the temperature control circuit 26C controls the temperature of the FLC panel 26A using a heater or the like based on the temperature detected here. . Further, the temperature control circuit 26C, based on the detected temperature,
The flag value is set in the flag register 26H by referring to a table that it owns and will be described later in FIG. On this occasion,
The controller 26D that controls the FLCD 26 is
The referenced temperature table is switched according to the state of a temperature table changeover switch 26S provided in the outer case of the FLCD 26 and operable by the user, for example. By providing a plurality of tables depending on the switch state, the temperature threshold value for the flag value can be changed, and as a result, the number of flags can be reduced. This makes it possible to simplify the hardware configuration. Note that a volume may be provided in place of the switch, and a plurality of temperature tables may be provided depending on the value of the volume.

In the above configuration, when the CPU II changes the display, the address signal of the video memory 11 corresponding to the desired data rewriting is given to the memory controller 40 via the address bus driver 31, where the CPU II
Arbitration is performed between the memory access request signal of I and the data transfer request signal from the synchronization control circuit 39. Then, when the CPU accessing side obtains the right,
The memory controller 40 switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41. At the same time, a control signal for the memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, the address data accessed by CPU 1 is transferred to F via switch Sl.
It is stored in the IFO (Al 36 or FIFO (B) 37) and is used when transferring display data, which will be described later.In this way, the method of accessing display data seen from the CPU II is no different from the case of the CRT described above. .

It also reads data from the video memory 41 and displays it on the FLCD.
26, a data transfer request is generated from the synchronization control circuit 39 to the memory controller 40, and the address conversion table 44 or FIFO side address is selected by the address selector 35 as the address for the video memory 41. When the memory controller 40 generates a control signal for data transfer, the data at the corresponding address is transferred from the memory cell to the shift register, and is output to the driver 42 according to the control signal of the serial port.

In the synchronous control circuit 39, as mentioned above, FLC:D26
According to one embodiment of the present invention, timings are generated to generate a cycle in which the entire screen is randomly refreshed and a partial rewrite cycle in which lines accessed by the CPU II are rewritten based on the horizontal synchronization signal H3YNC from the CPU II. Here, the full-scale refresh cycle refers to a cycle in which the lines constituting the display screen are randomly driven to display at least once, and this is a cycle in which the lines constituting the display screen are displayed at least once. The line to access is determined. Also,
An access line partial rewriting cycle is a cycle in which a line accessed by the CPU II is rewritten within a predetermined time period immediately before the cycle.

In this way, in this example, basically, the operation of refreshing the entire screen of the FLC display 26,
In order to change the display contents, the operation of rewriting the partial line re-accessed by the CPU II is performed alternately in a time-sharing manner, and the repetition period of these operations and the time ratio of these operations within one cycle are also changed. and can be set.

First, a description will be given of the basic operation of this example in which a refresh operation and a line rewriting operation are performed alternately in a time-sharing manner.

To explain the states of FIFO (A) 36 and FIFO (B) 37, when switch S1 is connected to the FIFO (A) 36 side, the address of the line accessed by (:PUll is sampled to FIFO (A) 36). On the other hand, when the switch S1 is connected to the FIFO (B) 37 side, the address of the line accessed by the CPU II is stored in the PIFO (B) 37. Also, when the switch S2 is connected to the FIFO (A) 36 When connected to the FIF
When the address stored in O(A) 36 is output and switch S2 is connected to FIFO(B) 37 side, FIFO
The address stored in FO(B) 37 is output.

One refresh of the entire screen is completed, and the FLCD26
outputs the vertical synchronization signal VSYNC, or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the line according to the conversion table 44, and from FLCD2B The horizontal synchronization signal given via the synchronization control circuit 39) is counted up sequentially for each ISYNC (.During this period, when the address of a certain line is accessed from the CPU II, the switch S1 is set to the FIFO (
A) 3B, so the address of this line is stored here, and then switch S2 is connected to FIFO (A
) 36, the memorized address is output from here and the output line is selected. Here, the switching signal for the switch S3 is given from the synchronous control circuit 39, and in the partial rewriting cycle, the output line address is switched to the FIFO (A) 36° FIFO (B) 37 side.

At this time, switch S1 is set to FIFO (B) 37
Since it is connected to the FIFO (B) 37 side, the address for access is stored on the FIFO (B) 37 side. Also, in the refresh cycle, the switch S3 is connected to the address conversion table 4.
4 side, and refresh operations are performed randomly based on the contents of the conversion table.

The above operation is repeated in the same way, but the reason why two FIFOs are prepared is to sample the memory accessed address on one side and simultaneously output the sampled address on the other side without any contradiction and efficiently. It is. In other words, the address sampling period is from the start of output of the access line of the other FIFO until the end of the full refresh cycle, and after the end of the full refresh cycle, there is a rewrite cycle of the access line that outputs the address sampled in the previous sampling period. Upon entering, the address sampling period of the other FIFO will begin.

As described above, in the basic operation of this example, refresh cycles and partial rewriting cycles are repeated alternately, and the ratio of these cycles is determined depending on environmental conditions such as temperature, the type of data to be displayed, and the FLCD display device. It can be changed depending on the difference in materials, etc. That is, by increasing the refresh rate, the refresh rate can be improved, and a good display state can be obtained even when the responsiveness of the FLC element is low, such as at low temperatures, or when displaying an image. On the other hand, if the proportion of partial rewriting is increased, the responsiveness of partial display changes can be increased. This means that we will be able to respond to any situation that may be appropriate.

Furthermore, in one embodiment of the present invention, in order to prevent or adjust flickering and image dispersion on the display screen and to obtain optimal image quality, the above-mentioned refresh cycle is performed in a so-called interlace mode, and this interlace mode is applied to the image data. and the temperature of the FLC panel. Hereinafter, a refresh cycle operation in interlace mode according to an embodiment of the present invention will be described.

FIG. 3 is a schematic diagram showing details of the address conversion table 44 shown in FIG. 2. As shown in FIG. 3, the conversion table 44 has n tables from table 1 to table n, and these tables are used to convert image data into header information set in the ladder register 44A and temperature flag register 26H. selected according to the temperature flag information. Each table stores address data of a line to be accessed on the display screen in accordance with each of the addresses O-N generated by the address counter 38. For example, in table 1, address 0 is the 900th, address 1 is the 821st, etc.
. . . The address data of the 8th line is stored at address N-1, and the address data of the 999th line is stored at address N. That is, if this table is used for translation, address 0
In this order from address N to address N, the lines of address data stored therein are refresh driven. This address data storage pattern, that is, the address generation pattern in the refresh operation (line access pattern in the refresh cycle), is determined by the characters, !, etc. in each table. ! The header information is set according to the type of display image such as a picture, a natural picture (photo mode, photo fine mode), the image quality of the display screen, and the temperature flag information is set according to the temperature of the FLC panel 26A. Each type has a different tendency. For example, if the displayed image is a natural image and the temperature of the FLC panel 26A is relatively high, the way the addresses jump as the address from the address counter 38 advances from O to N will be compared. Tables with a tendency to have a small target are selected. Thereby, the refresh cycle operation can be performed at an appropriate cycle depending on the displayed image and the temperature of the FLC panel.

In addition, the address generation pattern in each table is random number, and unlike the refresh cycle operation in which the lines of the display screen are sequentially driven one by one as in a CRT display device, for example, each line is driven at regular intervals. Since it has no properties, it has the effect of suppressing flicker and image dispersion.

Furthermore, as will be described later, the user can change the header value by operating a knob provided on the exterior case of the FLCD 26 while looking at the display screen,
That is, the address generation pattern can be changed by changing the table selected by the conversion table 44. This allows for good adjustment of screen flicker and the like.

In the above embodiment, in the conversion table shown in FIG. 3, N is made to match one cycle of the at1no counter, that is, the number of lines on the display screen, and all lines are converted once in one refresh cycle. For example, if N is twice the number of lines, then 2
It is also possible to output a small number (one time each) for all lines in one refresh cycle. Also, the contents of each table can be changed.
These operations can be performed by data lines input to the address conversion table 44 via the data bus driver 45.

FIG. 4 shows an example of the structure of data processed by the system shown in FIG. One unit of data consists of a management area CA and a data area, and data consisting of character strings such as letters and numbers, data such as line drawings, natural drawings, photographs, etc. are developed in the data area.

The management area CA is provided with an area CTRL for management information regarding the developed data (for example, data size, pitch in the case of character data, and other information) and an area HA for header information indicating the image type.

When a user inputs a document or the like using the keyboard 23, information indicating that the data consists of a string of characters etc. is provided in the area HA, and management information for editing and other purposes is added to the area CTRL. Ru. In addition, when inputting using the scanner 21B, the modes set for the reading (character mode for reading character strings, photo mode for reading photos, photo fine mode for reading photos clearly), etc. The information on ) is expanded to the header information area )IA, and other management information is expanded to the area CTRL. Then, the data to which the management area CA set in this manner is added is registered in the form of a file on the hard disk or floppy disk.

In this example, when displaying an image input from a scanner 21B or the like, characters input from a keyboard 23, or a file read from a hard disk or floppy disk, information indicating the image type is retrieved from the header information area. This is stored as header information H in the image data header register 44A in FIG. 2. Furthermore, as will be described later in FIG. 6, the contents of the header information area HA can be rewritten by the user operating knobs displayed on the display screen using, for example, a mouse, and the user can also select the display image quality. possible.

FIG. 5 is a conceptual diagram showing a temperature flag table included in the temperature control circuit 26C shown in FIG.
Temperature detected by temperature sensor 26B and switch 26S
The temperature flag register 26H is selected according to the state of the temperature flag register 26H. The switch 26S is operated by the user as described above, and the user can change the state of the switch 26S to A or B depending on the image quality or the like. Thereby, it is possible to provide a plurality of temperature threshold values for the flags, and it is possible to reduce the number of flags and simplify the hardware configuration.

6(A) to 6(C) are a flowchart showing a control procedure by the CPU 1 according to a user's operation in the information processing system shown in FIG. 1, and FIG. FIG. 6(D) is a flowchart showing the operation procedure of the FLCD 27 in accordance with the above control procedure.

FIG. 6(A) shows the image input mode by the scanner 21B and the control procedure for displaying this input data by the FLCD 26. In step 5501, FLC0
When the scanner icon on the display screen 26 is selected, for example, by the user operating the mouse 24, a window for displaying the input image at a predetermined location on the display screen is opened in step 5502. Further, in step 5503, when the user sets an input mode among text, photo, and photo fine depending on the image input by the scanner 21B, in step 5504, the header information as described above in FIG. , is selected as a default from among a plurality of predetermined header values and is added. At the same time, in step 5505, the second
This header information is set in the image data header register 44A shown in the figure.

After that, in step 5506, the input operation of the scanner 21B is started, and in step 5507, the input image data is temporarily stored in the main memo January 3 in order to adjust the resolution of the scanner 21B and the FLCD 26, and then In step 5508, this image data is expanded into the video memory 41 and displayed.

Next, in step 5509, it is determined whether the user has changed the display state by operating a knob on the display screen with a mouse or the like in order to change the image quality. Depending on the change, a header value is selected from among the plurality of header values, and in step 5511 this header value is set in the header register 44A. If it is determined in step 5509 that the display state has not been changed, this process ends.

FIG. 6fB) shows a control procedure in a character input mode compatible with a word processor. For example, when this process is started by a predetermined key operation on the keyboard 23, step 5521
An input form is displayed at a predetermined location on the display screen. Accordingly, in step 5522, a predetermined header value is selected by default from among the plurality of header values described above and added to a predetermined area of the memory. Further, in step 5523, this header value is set in the header register 44A.

Thereafter, when key manual input is performed in step 5524, this key manual input data is developed in the video memory 41 and displayed in step 5525.

Next, in step 8526, it is determined whether the display state has been changed by the user in the same manner as the control procedure in FIG. 6(A), and if the display state has been changed, step 552
The header value is changed in step 7, and the process returns to step 5523 to set the header value in the register 44A for display change. If the display state has not been changed, it is determined in step 5528 whether or not the key input has ended, and if it has ended, this process ends; if it has not, the process returns to step 5524.

FIG. 6(C) shows a control procedure for a file display mode for displaying files stored on the hard disk 18 or floppy disk 19.

When this process is started, the header information of the file is read in step 3531, and the header information added to the file is set in the header register 44A in step 5532. Subsequently, in step 5533, the data in the file is stored in the memory 13 in order to adjust the resolution as described above, and then, in step 5534, these data are developed in the video memory 41 and displayed. Furthermore, in steps 3535 to 5537, FIG.
Processing similar to steps 3509 to 5511 in A) is performed.

FIG. 6(D) shows the operation of the FLCD interface 27 according to each control procedure shown in FIGS. 6(A) to 6(C) above.

That is, in the FLCD interface 27, in step 5541, the content of the ladder register 44A and the flag register 26H is changed to the image data (if there is a change in either one, the address conversion table 44 is converted in accordance with this change in step 5542). The table used for this is changed, and in step 5543, the above-described refresh operation is performed according to this table.

As explained above, according to an embodiment of the present invention, interlacing during refresh drive is determined depending on the type of display image, the image quality of the display screen, and the type of equipment that constitutes the information processing system and supplies display data. Mode is changed.

In the above embodiment, the table is changed according to the contents of the header register 44A and the temperature flag register 26E, but the table may be changed according to either one of them.

Furthermore, in the upper part, table changes in the address conversion table 44 are made independently at any time according to changes in the header, temperature flag, etc. However, for example, a synchronization control circuit may control the timing of changes in the address conversion table 44. It is also possible to make the change every time H3YNC occurs.

Furthermore, instead of generating addresses using the above address conversion table, by generating random numbers, the line corresponding to this random number is first accessed, and a flag is set for the line that has been accessed. Also, the same refresh drive as in the above embodiment can be performed. That is, if lines for which flags have already been set are not accessed and only lines for which flags are not set are accessed, the refresh cycle will be completed when the flags are set for all lines.

[Effects of the Invention] As is clear from the above description, according to the present invention, an almost irregular address is generated from an address conversion means such as an address conversion table, so that this address is as long as it corresponds to a scanning line consisting of display elements.

These lines are accessed almost irregularly and their display status is updated.

Further, the address translation means has a plurality of translation means,
Since these are changed according to the setting information and the temperature information of the display screen, the manner in which addresses are generated can be changed depending on the setting information and the like.

As a result, access for updating the display to each line of the display screen does not have periodicity, so that flicker on the display screen can be effectively prevented or adjusted.

In addition, since the method of accessing the above lines can be changed depending on the setting information according to the display data etc. and the temperature of the FLC panel, a predetermined tendency in the irregularity of each of the above conversion tables can be created. If the setting information is set, display can be performed with appropriate image quality according to the setting information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to an embodiment of the present invention, and FIG. 2 shows an FLC as the display control device shown in FIG.
3 is a conceptual diagram of the address translation table shown in FIG. 2; FIG. 4 is a conceptual diagram illustrating an example of a data structure used in an embodiment of the present invention; FIG. 5 is a conceptual diagram of a temperature flag table included in the temperature control circuit shown in FIG. 2, and FIGS. 6 (A) to (C) are flowcharts showing control procedures in the information processing system shown in FIG. 1. , FIG. 6(D) is a flowchart showing the operating procedure of the display control device shown in FIG. 2, and FIG. 7 is a block diagram showing the configuration of a conventional CRT interface. 11...C20, 12...Address bus, 13...System bus, 14...DMA controller, 15...LAN interface, 16...LAN. 17... I10 device, 18... Hard disk device, 19... Floppy disk device. 20... Disk interface, 21... Printer, 22... Printer interface, 23... Keyboard, 24... Mouse, 25... Interface, 26... FLCD (FLCD display), 26
B...Temperature sensor, 26E...Temperature flag register, 26S...Switch, 27...FLCD interface, 3]...Address bus driver, 32...Control bus driver, 33, 43.4
5... Data bus driver, 34... Sampling counter, 35... Address selector, 36... FIFO (A) memory, 37-FIFO (B) memory, 38... Address counter, 39...・Synchronous control circuit. 40...Memory controller, 41...Video memory, 42...Driver receiver, 44...Address conversion table, 44A...Image data header register, SL, S2.
S3...Switch. No. 4 Kyou (A) Figure 6 (C) Procedural amendment sound (sword procedure amendment sound August 30, 1990)

Claims (1)

[Claims] 1) Display control for a display device that includes a display screen in which a plurality of display elements capable of maintaining an updated display state are arranged and updates the display based on display data on the display screen. In the apparatus, address generating means generates an address corresponding to each of the plurality of display elements in the order of arrangement of the plurality of display elements, and for the address generated by the address generation means, a display element corresponding to the address and a address converting means which has a plurality of converting means for associating addresses corresponding to different other display elements almost irregularly and generating the associated addresses in response to generation of addresses by the address generating means; a setting means for setting the conversion means used for generating the address from among the plurality of conversion means included in the address conversion means according to setting information and/or the temperature of the display screen; and the plurality of display elements. storage means for storing display data of the display element corresponding to each of the display elements; and a storage means for storing display data of the display element at an address generated by the conversion means set by the setting means, from the storage means to the display device. A display control device comprising: a transfer means for transferring; and a display control device. 2) The setting information may include the type of the display data, the type of data supply means for supplying the display data to the display device, and the display image quality of the display screen. The display control device described in . 3) The display control device according to claim 1 or 2, wherein the display element has a ferroelectric liquid crystal as an operating medium for updating the display state.