JPH04312143A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device which can have the continuous accesses to plural memories just with a single access operation. CONSTITUTION:An address generator 12 produces continuously the address signals 5 through a start address register 10 and a length register 11. A 1st access means 30 reacts out the data to a data register 3 from a memory cell 1 with the signal 5. A 2nd access means 40 reads the date out of the cell 1 with the contents of the register 3 used as an address. A selector 50 produces a selection signal 9 with an access mode signal 7 to switch a selector 8 and switches alternately and continuously the 1st and 2nd access means 30 and 40.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for storing data in a computer or the like.

0002

2. Description of the Related Art FIG.
FIG. 5 is a diagram showing a conventional memory device disclosed in Publication No. 5 (Memory Device). In FIG. 3, 1 is a memory cell, 2 is an address register that indicates which location in memory cell 1 is to be accessed, and 3 is for holding data read from the location specified by address register 2 of memory cell 1. a data register; 4 is a memory control unit that controls reading or writing to the memory cell 1, address register 2, and data register 3; 5 is an address signal input to the memory device; 6 is an input signal from the memory device or This is the data signal to be output.

Next, regarding the operation of the memory device shown in FIG. 3, four pieces of data on the memory cell 1 starting from address A shown in FIG. 2, data M0, whose addresses are B, B+2, B+1, B+3, An example in which M1, M2, and M3 are read out consecutively will be explained. These operations take the steps shown below. (Step 1) Address A is set in address register 2 through address signal 5. (Step 2) Data B is read from the location of the memory cell 1 specified by the address register 2 and set in the data register 3. The contents set in this register 3 are transferred to the central processing unit through a data signal 6, for example. (Step 3) The central processing unit sets the data B read in (Step 2) in the address register 2 through the address signal 5. (Step 4) Data M0 is read from the location of memory cell 1 specified by address register 2 and set in data register 3. The contents set in this register 3 are transferred to the central processing unit through a data signal 6, for example. (Step 5) Increase address A by 1, and the value A+1
is set in address register 2 through address signal 5. (Step 6) Read data B+2 from the location of memory cell 1 specified by address register 2 and set it in data register 3. The contents set in this register 3 are transferred to the central processing unit through a data signal 6, for example. (Step 7) The central processing unit sets the data B+2 read in (Step 6) in the address register 2 through the address signal 5. (Step 8) Data M1 is read from the location of memory cell 1 specified by address register 2 and set in data register 3. The contents set in this register 3 are transferred to the central processing unit through a data signal 6, for example. (Step 9) Repeat the same operation two more times.

0004

[Problem to be Solved by the Invention] Since the conventional memory device is configured as described above, data written in the memory cell 1 as shown in FIG. 2 is used as an address.
When accessing a memory cell, a processing device connected to the memory device, such as a central processing unit, needs to set an address to an address register and access a data register twice, which reduces the memory access speed. was there.

The present invention was made to solve the above-mentioned problems, and when accessing the memory cell 1 using data written in the memory cell 1 as shown in FIG. 2 as an address, It is an object of the present invention to obtain a memory device that allows multiple consecutive memory accesses with one setting.

[0006]

A memory device according to the present invention has the following elements. (a) a memory cell that retains data; (b) an address generation means that continuously generates addresses for reading and writing from and to this memory cell; (c) data from the memory cell based on the address generated by the address generation means. (d) a second access means that accesses the memory cell using the data accessed by the first access means as an address; (e) the first access means and the second access means; Selection means to select.

[0007]

[Operation] In the memory device according to the present invention, the address generation means automatically generates a plurality of addresses to be accessed,
Generate addresses to be accessed consecutively. The first access means accesses the memory cells using the continuously generated addresses (referred to as normal access mode). Further, the second access means accesses the memory cell using the data in the memory cell accessed by the first access means as an address (referred to as indirect addressing access mode). The selection means selects the first access means or the second access means by determining whether the addresses consecutively generated by the address generation means are in the normal access mode or the indirect addressing access mode. do.

[0008]

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an example of a configuration diagram of a memory device according to the present invention, and 1 to 6 are similar to the conventional device shown in FIG. In the figure, 7 is an access mode signal which specifies the normal access mode or the indirect addressing access mode. 8 is a selector that selects either the address signal input to the memory device or the output of the data register 3 in the memory device; 9 is a selection generated by the memory control unit 4 based on the access mode signal 7; 10 is a start address register that holds a start address to be accessed continuously; 11 is a length register that holds the number of addresses to be continuously generated;
Reference numeral 12 denotes an address generator that continuously generates addresses to be accessed from the contents of the start address register 10 and length register 11.

Reference numeral 20 denotes an address generation means that continuously generates addresses for reading and writing from and to the memory cells. Reference numeral 30 denotes a first access means that accesses data from the memory cells based on the addresses generated by the address generation means. , 40 is a second access means that accesses the memory cell using the data accessed by the first access means as an address, and 50 is a selection means that selects the first access means and the second access means.

[0010] 1 of Example 1. Next, the operation of the memory device according to the present invention configured as shown in FIG. 1 will be explained. First, the case of normal access mode will be explained. Four pieces of data on memory cell 1 starting from address A shown in FIG. 2 shown in the conventional example, B, B+2, B+1, B
The operation of continuously reading +3 takes the following steps. (Step 1) Set address A in the start address register 10 and set 4 in the length register 11. (Step 2) The address generator 12 first generates the address A set in the start address register 10 as the address signal 5 as the first address generation. (Step 3) The address generator 12 also sets the access mode signal 7 to the normal access mode. The selection means 50 determines that the access mode signal 7 designates the normal access mode, and first selects the output of the selector 8 to be equal to the address signal 5 using the selection signal 9. (Step 4) Address A is set in address register 2 through address signal 5. (Step 5) 1. The first access means 30 reads data B from the location of the memory cell 1 specified by the address register 2 and sets it in the data register 3. Even after the setting, the selection means 50 selects the selector 8 by the selection signal 9.
The output of the address signal 5 is selected to be equal to the address signal 5. 2. In this way, the contents set in this register 3 are transferred to a central processing unit (not shown) through, for example, a data signal 6. Thereafter, the selection signal 9 of the selection means 50 sets the selector 8 so that its output becomes equal to the address signal 5. (Step 6) Address generator 12 sets address A to 1
Then, the value A+1 is generated as address signal 5. Address signal 5 is set in address register 2 through selector 8 . (Step 7) 1. The first access means 30 reads data B+1 from the location of the memory cell 1 specified by the address register 2 and sets it in the data register 3. Even after the setting, the selection means 50 is set so that the output of the selector 8 becomes equal to the address signal 5 by the selection signal 9. 2. Data B+1 set in the data register 3 is transferred to a central processing unit (not shown) through a data signal 6, for example. (Step 8) Repeat the same operations as steps 6 and 7 two more times (total 4 times).

As described above, in the normal access mode, the selector 8 selects the address generator 1 by the selection signal 9.
The first access means 30 selects the address signal 5 generated in step 2, and reads data from the memory cell 1 based on this address signal 5. At this time, the second access means is not used.

Example 1-2. Next, the operation of the memory device according to the present invention configured as shown in FIG. 1 will be described in the indirect addressing access mode. The operation of successively reading out four pieces of data on the memory cell 1 starting from the address A shown in the conventional example in FIG. Take the steps listed below. (Step 1) Set address A in the start address register 10 and set 4 in the length register 11. (Step 2) Address generator 12 first generates address A set in start address register 10 as address signal 5. (Step 3) The address generator 12 also sets the access mode signal 7 to indirect addressing access mode. The selection means 50 determines that the access mode signal 7 specifies the indirect addressing access mode, and first selects the output of the selector 8 to be equal to the address signal 5 using the selection signal 9. (Step 4) Address A is set in address register 2 through address signal 5. (Step 5) 1. The first access means 30 reads data B from the location of the memory cell 1 specified by the address register 2 and sets it in the data register 3. After the setting, the selection means 50 sets the output of the selector 8 to be equal to the output of the data register 3 using the selection signal 9. 2. In this way, the output of the selector 8, that is, the data B set in the data register 3, is set in the address register 2 through the selector 8. 3. The second access means 40 reads data M0 from the location of the memory cell 1 specified by the address register 2 and sets it in the data register 3. The contents set in this register 3 are transferred to a central processing unit (not shown) through a data signal 6, for example. Thereafter, the selector 8 is switched by the selection signal 9 of the selection means 50, and its output is set to be equal to the address signal 5. (Step 6) Address generator 12 sets address A to 1
Then, the value A+1 is generated as address signal 5. Address signal 5 is set in address register 2 through selector 8 . (Step 7) 1. The first access means 30 reads data B+1 from the location of the memory cell 1 specified by the address register 2 and sets it in the data register 3. After the setting, the selection means 50 sets the output of the selector 8 to be equal to the output of the data register 3 using the selection signal 9. 2. The output of the selector 8, that is, the data B+1 set in the data register 3, is set in the address register 2 through the selector 8. 3. The second access means 40 reads data M1 from the location of the memory cell 1 designated by the address register 2 and sets it in the data register 3. The contents set in this register 3 are transferred to a central processing unit (not shown) through a data signal 6, for example. Thereafter, the selector 8 is switched by the selection signal 9 of the selection means 50, and its output becomes equal to the address signal 5. (Step 8) Repeat the same operations as steps 6 and 7 two more times (total 4 times).

As described above, in the case of the indirect addressing access mode, the selector 8 selects either the address signal 5 generated by the address generator 12 or the data read by the first access means 30 according to the selection signal 9. The contents of the register 5 are alternately selected, and the second access means 40 selects the data read from the memory cell 1 by the first access means 30 based on the address signal 5 as the address to be accessed next. Data will be read from.

Example 2. In the first embodiment, a read operation for a memory device has been described, but the same applies to a write operation.

Example 3. In the first embodiment, a case was explained in which four pieces of data on a specific memory cell are accessed consecutively, but the same effect can be achieved even if the position of the memory cell, the number of pieces of data, etc. are set to other arbitrary values. .

Example 4. In the first embodiment, a one-dimensional memory device in which one address is given has been described, but a two-dimensional memory device in which access is given by row and column addresses may also be used.

Example 5. In the first embodiment, the address generator 12 continuously generates addresses from the contents of the start address register 10 and length register 11. It is also possible to generate an address by

Example 6. In the first embodiment, the address generator 12 accesses data at consecutive memory addresses starting from address A, but the address generator 12 does not need to access data at consecutive memory addresses starting from address A. The address generator 12 may also generate addresses that are not consecutive.

Note that there is a storage device technology similar to the memory device according to the present invention described in Japanese Patent Laid-Open No. 143643/1983. However, this technology has
The memory device according to the present invention is not configured so that a central processing unit or the like that accesses the memory can perform multiple memory accesses in one access to the memory device, and has a different purpose, configuration, and effect from the memory device according to the present invention. It is.

[0020]

[Effects of the Invention] As described above, according to the present invention, when accessing data written in a memory cell,
The configuration allows the central processing unit that accesses the memory to perform multiple memory accesses in a single access to the memory device, which simplifies processing by the central processing unit and speeds up data access to the memory device. There are effects that can be achieved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of data on a memory cell to be accessed.

FIG. 3 is a configuration diagram showing an example of a conventional memory device.

[Explanation of symbols]

1 Memory cell 2 Address register 3 Data register 4 Memory control section 5 Address signal 7 Access mode signal 8 Selector 9 Selection signal 10 Start address register 11 Length register 12 Address generator 20 Address generation means 30 First access means 40 Second access means 50 Selection means

Claims (1)

[Claims] Claim 1: A memory device (a) having the following elements:
A memory cell that holds data; (b) address generation means that continuously generates addresses for reading and writing from and to this memory cell; (c) data is accessed from the memory cell based on the address generated by the address generation means. a first access means; (d) a second access means that accesses the memory cell using the data accessed by the first access means as an address; and (e) selects the first access means and the second access means. means of selection.