JPH04312189A - Multiplier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to multipliers, and more particularly to improving dynamic range.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional multiplier. This multiplier consists of bipolar transistors 31,3
2, 33, 34, 35, 36, load resistors 37, 38, emitter resistors 39, 40, and a constant current source 41. Between the bases of transistors 31 and 32 and transistor 33
, 34, and a signal source 43 is connected between the bases of transistors 35, 36. A power supply potential is applied to the power supply terminal 44, and a ground potential is applied to the ground terminal 45. Output signals are obtained from output terminals 46 and 47. Note that the constant current source 41 includes at least one bipolar transistor.

In this multiplier, the signal source 42 connects the bases of the transistors 31 and 32 and the transistor 33.
, 34, and a second input signal from a signal source 43 between the bases of transistors 35, 36. Currents flowing out of the emitters of transistors 31 and 32 and from the emitters of transistors 33 and 34 are controlled by transistors 35 and 36, respectively.

As a result, a signal current in which the amplitude of the first input signal of the signal source 42 is modulated by the amplitude of the second input signal of the signal source 43 flows through the load resistors 37 and 38 . Therefore, an output signal obtained by multiplying the first input signal and the second input signal is obtained between the output terminals 46 and 47.

[0005]

In the conventional multiplier shown in FIG. 3, at least three transistors are connected vertically between a power supply terminal 44 and a ground terminal 45. Since each transistor has a forward voltage between its base and emitter, there is a problem in that the input/output dynamic range cannot be increased.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a multiplier that can be designed to have a large input/output dynamic range.

[0007]

SUMMARY OF THE INVENTION A multiplier according to the present invention includes a plurality of logarithm compression means, addition means, and exponent expansion means. The plurality of logarithmic compression means each compresses the plurality of input signals logarithmically. The adding means adds together the plurality of output signals from the plurality of logarithmic compression means. The exponential expansion means expands the output signal of the addition means exponentially.

[0008]

[Operation] In the multiplier according to the present invention, a plurality of input signals are each compressed logarithmically, the compressed signals are added linearly, and the added signal is expanded exponentially. be done. As a result, as the output signal,
A signal is obtained by multiplying multiple input signals together.

Since the plurality of input signals are first compressed logarithmically, the dynamic range of the input signals can be increased. Further, since the output signal is obtained by expanding the added signal exponentially, the dynamic range of the output signal can be increased.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the structure of a multiplier according to an embodiment of the present invention. This multiplier includes a first logarithmic compression circuit 1, a second logarithmic compression circuit 2, an addition circuit 3, and an exponential expansion circuit 4. The first logarithmic compression circuit 1 compresses the first input signal A applied to the input terminal I1 according to a logarithmic function. The second logarithmic compression circuit 2 has an input terminal I
2 is compressed according to a logarithmic function. The adder circuit 3 adds the output signal of the first logarithmic compression circuit 1 and the output signal of the second logarithmic compression circuit 2. Exponential expansion circuit 4 expands the output signal of adder circuit 3 according to an exponential function. An output signal from the exponential expansion circuit 4 is applied to the output terminal O.

The operation of the multiplier shown in FIG. 1 will be explained. When the first input signal A is applied to the input terminal I1 and the second input signal B is applied to the input terminal I2, the first logarithmic compression circuit 1
The output signal of the second logarithmic compression circuit 2 becomes logA, and the output signal of the second logarithmic compression circuit 2 becomes logB. Furthermore, the output signal of the adder circuit 3 becomes (logA+logB). Here, (lo
gA+logB) is mathematically equal to log(A×B). Therefore, the output signal of the exponential expansion circuit 4 is elog(
AxB). Here, elog(AxB) is mathematically equal to AxB. Therefore, the output signal output from the output terminal O is A×B.

FIG. 2 is a circuit diagram showing the detailed configuration of the multiplier in FIG. 1. This multiplier consists of bipolar transistors 5, 6, 7, 8, 9, 10, 11, 12, diode 1
3, 14, emitter resistors 15, 16, 17, 18, load resistors 19, 20, and constant current sources 21, 22, 23.

A signal source 24 for generating a first input signal A is connected between the bases of transistors 5 and 6. A signal source 25 for generating a second input signal B is connected between the bases of transistors 7 and 8. A power supply potential is applied to the power supply terminal 26, and a ground potential is applied to the ground terminal 27.

Diode 13 is connected between power supply terminal 26 and the collector of transistor 5, and diode 14 is connected between power supply terminal 26 and the collector of transistor 6. The emitters of transistors 5 and 6 are connected to constant current source 21 via resistors 15 and 16, respectively.

The collectors of transistors 9 and 10 are connected to a power supply terminal 26. The bases of transistors 9 and 10 are connected to the collectors of transistors 5 and 6, respectively. The emitters of transistors 9 and 10 are connected to the collectors of transistors 7 and 8, respectively. Transistors 7, 8
The emitters of are connected to a constant current source 22 via resistors 17 and 18, respectively.

The collectors of transistors 11 and 12 are connected to a power supply terminal 26 via resistors 19 and 20, respectively. The bases of transistors 11 and 12 are connected to the collectors of transistors 7 and 8, respectively. transistor 11
, 12 are connected to a constant current source 23. The collectors of transistors 11 and 12 are connected to output terminals 28 and 12, respectively.
Connected to 29.

Next, the circuit operation of the multiplier shown in FIG. 2 will be explained. Diodes 13 and 14 are connected to the collectors of the transistors 5 and 6 as loads, respectively. Therefore, when the first input signal A is applied between the bases of the transistors 5 and 6 by the signal source 24, the diodes 13 and 14
A collector current flows through each. Since the forward current-forward voltage characteristic of the diode is a logarithmic function characteristic, an output voltage obtained by compressing the voltage of the first input signal A according to a logarithmic function is obtained between the collectors of the transistors 5 and 6.

On the other hand, transistors 9 and 10 are connected to the collectors of transistors 7 and 8, respectively, as loads. Therefore, the signal source 25 causes the transistors 7,
When the second input signal B is applied between the bases of transistors 8 and 8, collector current flows through transistors 9 and 10. Since the emitter current-base-emitter voltage characteristic of a transistor is a logarithmic function like that of a diode, an output voltage obtained by compressing the voltage of the second input signal B according to a logarithmic function is obtained between the collectors of transistors 7 and 8. It will be done.

However, since the output voltage between the collectors of transistors 5 and 6 is applied between the bases of transistors 9 and 10, the first input signal A is compressed according to a logarithmic function between the collectors of transistors 7 and 8. An output signal is obtained by adding the signal obtained by compressing the second input signal B according to a logarithmic function. This added output signal is applied between the bases of transistors 11 and 12.

[0020] Transistor base-emitter voltage -
Since the collector current characteristic is an exponential characteristic, a signal obtained by expanding the output signal between the bases of the transistors 7 and 8 according to an exponential function is obtained between the output terminals 28 and 29. In this way, a signal obtained by multiplying the first input signal A and the second input signal B is obtained between the output terminals 28 and 29.

In the multiplier of FIG. 2, the diode 13
, 14, transistors 5, 6, emitter resistors 15, 16
and constant current source 21 constitute the first logarithmic compression circuit 1,
Transistors 7, 8, 9, 10, emitter resistors 17, 1
8 and constant current source 22 constitute the second logarithmic compression circuit 2. Furthermore, transistors 9 and 10 constitute an adder circuit 3. Further, load resistors 19, 20, transistors 11,
12 and a constant current source 23 constitute an exponential expansion circuit 4.

Note that the logarithmic compression circuit 1, the logarithmic compression circuit 2,
The configurations of the addition circuit 3 and the exponent expansion circuit 4 are not limited to the configuration shown in FIG. 2, and may be other configurations.

[0023]

[Effects of the Invention] As described above, according to the present invention, each of a plurality of input signals is compressed logarithmically, the compressed signals are added together, and then the added signal is expanded exponentially. , a multiplier with a large input/output dynamic range can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a multiplier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of the multiplier in FIG. 1;

FIG. 3 is a circuit diagram showing the configuration of a conventional multiplier.

[Explanation of symbols]

1... First logarithmic compression circuit 2... Second logarithmic compression circuit 3...Addition circuit 4... Exponential expansion circuit Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A plurality of logarithmic compression means for logarithmically compressing a plurality of input signals, an addition means for adding together a plurality of output signals from the plurality of logarithm compression means, and an output signal of the addition means. A multiplier equipped with an exponential expansion means that expands exponentially.