JPH04313111A - Photoelectron parallel multiplier - Google Patents

Abstract

PURPOSE:To perform the vector matrix operations including the additions and subtractions simultaneously by using a single optical parallel multiplier. CONSTITUTION:A surface light emitting device consisting of an LED array 1 is provided together with a light receiving device 2 consisting of a symmetrical structure floating base hetero junction bipolar phototransistor. The emitters of the elements forming the device 2 are controlled independently of each other so that the light receiving current of each element is independently modulated. Therefore the matrix elements of the vector matrix operations can be varied at every operation with a photoelectron parallel multiplier. Furthermore the positive and negative operations are attained with the use of the light. Thus, the function of the photoelectronic parallel multiplier is remarkably improved.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a photoelectronic parallel multiplier using a photodetector device having a symmetrical npn or pnp structure and integrating floating base heterocoupled transistors in a two-dimensional array. The aim is to apply it to processing.

0002

2. Description of the Related Art FIG. J. Appl. Ph
ys. vol28. This is a conventional parallel multiplier shown in L2101. In the figure, 61 is an LED constructed by arranging linear light emitting diodes (LEDs) in a plane.
Array 62 is a light transmission mask 63 in which elements that transmit or do not transmit light are arranged in a grid pattern.
is a PD array constructed by arranging linearly extending PIN photodiodes (PDs) in a plane. Now each LED
The status of 61 is 1 when the LED emits light, and 0 when it does not emit light.
The state of the LED array is represented by vj (j=1, 2, . . . N) (where N is the number of LEDs in the LED array). Also, the state of the transmission mask 2 can be changed to the transmission mask 62.
The matrix Tij (i=1
, 2, . . . N, j = 1, 2, . . . N).

[0003] Here, since the longitudinal direction of the PDs constituting the PD array 63 and the longitudinal direction of the LEDs constituting the LED array 61 are assembled so as to be perpendicular to each other, the photocurrent generated in the PD array is Since the amount of light expressed by is irradiated, a photocurrent proportional to this value is generated. The photocurrent generated in this way is
If Ui is set for each time, (η is the photo-electronic conversion efficiency), it can be seen that a vector-matrix parallel multiplication function is realized.

FIG. 7 is a conceptual diagram of the circuit configuration of the PD array 3 in FIG. 6, in which N PIN photodiodes are connected in parallel in each column and function as photodiodes by applying a reverse bias to one side. FIG. 8 is an energy band diagram of a PIN photodiode, in which incident light is absorbed by the depletion layer in the i-layer, electron-hole pairs are generated, and photocurrent is generated by the drift of these pairs. The direction in which this current flows is fixed and cannot be changed.

[0005]

[Problems to be Solved by the Invention] Since the conventional optical parallel multiplier is constructed as described above, the matrix Tij
It is not possible to change the elements in calculations, so it lacks versatility. In addition, since the photocurrent generated in each PIN photodiode that makes up the PD array flows in the same direction, addition is possible in the calculation of Ui above, but subtraction is not possible. The problem is that it is necessary to prepare two sets of parallel multipliers, one for addition and the other for subtraction, and to add and subtract the values (photocurrent) of both using, for example, a separately prepared computer. there were.

The present invention was made to solve the above-mentioned problems, and aims to provide a device that can make matrix elements variable for each operation. The purpose is to enable execution on a set of parallel arithmetic units.

[0007]

[Means for Solving the Problems] An optical parallel multiplication device according to the present invention includes a transmission mask 62 and a PD array 6 in FIG.
The PIN photodiode constituting 3 is connected to an npn or pnp heterojunction floating base phototransistor (a floating base phototransistor is a structure in which the emitter and collector terminals are operated without wiring to the base and has a symmetrical material composition). It is a phototransistor.)
It is possible to change the photocurrent generated by the voltage VEC between the emitter and collector of a heterojunction floating base phototransistor.

[0008]

[Operation] In the above phototransistor,
When the emitter-collector voltage VEC is changed, the depletion layer expands in accordance with the emitter-collector voltage VEC at the pn junction of this phototransistor, which is in a reverse bias state, and the photocurrent generated in this depletion layer changes. . Due to this change in photocurrent, the amplification factor of the transistor changes, and the output current of the phototransistor changes. Changes in this current can be made to correspond to changes in the values of each matrix element in vector-matrix parallel multiplication. Also,
Since the polarity of VEC can be made to correspond to the positive and negative values of each element of matrix Tij, addition and subtraction can be performed simultaneously by the optical parallel multiplier configured in this manner.

[0009]

[Example] Example 1. FIG. 1 is a cross-sectional view showing one embodiment of the present invention, which is composed of both a surface emitting device 1 and a light receiving device 2, of which the surface emitting device 1 is similar to the conventional parallel multiplier described above. It is a LED array. Similarly, the electrode 3 of the LED array is also the same.

FIG. 2 is a circuit diagram of the light receiving device 2 in FIG.
Instead of an IN photodiode, a symmetric structure floating base heterojunction bipolar phototransistor (hereinafter referred to as S-HPT) is used.
(unction Photo Transistor)
) is used. N collectors of the S-HPT are connected in parallel and grounded for each column. However, unlike a conventional PIN photodiode, the emitter side is wired for each element, and the light receiving current of each S-HPT is modulated by controlling the emitter. As a result, the light-receiving device 2 in FIG. 1 has a photocurrent modulation function as well as a light-receiving ability, so that a function of changing matrix elements in vector-matrix calculations for each calculation can be realized.

In other words, the conventional transmission mask indicating matrix elements is no longer necessary, and the configuration of the optical parallel multiplier can be simplified. For example, it is possible to implement an integrated optical parallel multiplier on one chip. In Figure 3, S-H
An energy band diagram when no bias voltage is applied to PT is shown. This example will be explained using an npn type S-HPT as an example. The emitter and collector of S-HPT are each made of n-type AlGaAs.
By making the bandgap larger than the energy of the light emitted by the light emitting device, the light transmittance is achieved. The base is made of p-type GaAs, and light is mainly absorbed by the base.

FIG. 4 shows an energy band diagram when a negative bias voltage is applied to the emitter side of the S-HPT. In this case, the pn junction between the emitter and base is in a forward bias state, and the pn junction between the base and collector is in a reverse bias state. Therefore, at the pn junction between the base and the collector, a depletion layer with a width corresponding to the reverse bias voltage applied to the emitter expands, and light is absorbed in an amount proportional to the width of this depletion layer, causing electron-hole pairing. occurs. This electron-hole pair drifts, and the electrons flow toward the collector side and the holes flow toward the base side. Since the injection of holes into the base side corresponds to the base current of a conventional transistor, a transistor action with an amplification factor corresponding to the base current occurs, and electrons are injected from the emitter to the base, diffuse through the base, and reach the collector. reaches the collector current. It is important here that the base current changes depending on the reverse bias voltage applied between the emitter and the collector, and this changes the amplification factor of the transistor. This is the principle by which photocurrent can be modulated.

Next, FIG. 5 shows an energy band diagram when a positive bias voltage is applied to the emitter side. In this case, the pn junction between the emitter and the base is in a reverse bias state, and the pn junction between the base and collector is in a forward bias state. At this time, the light is absorbed between the emitter and the base,
This generates a base current, but since the direction is opposite to that in FIG. 4, electrons are injected from the collector to the base, resulting in a transistor action. In this case, since the transistors have a completely symmetrical structure, the same amplification factor as in FIG. 4 can be obtained. The current flowing at this time is in the opposite direction to that in the case of FIG. In other words, this S-HPT allows photocurrent to flow in both directions.

Example 2. In the above embodiment, a case has been described in which an LED array is used as a light emitting device, but it goes without saying that a two-dimensional LED array or a surface emitting laser array can also be used as a light emitting device. Of course, this embodiment can also be integrated in the same way as the above embodiment.

Example 3. Further, in the above embodiment, the case where an npn type S-HPT is used as the light receiving device has been described, but it goes without saying that the same can be realized using a pnp type S-HPT.

Example 4. Furthermore, in the above embodiment, S-H
Although the case where an AlGaAs-GlAs-based material is used as the PT has been shown, it goes without saying that the same can be achieved using other compound semiconductors.

[0017]

As described above, according to the present invention, each matrix element can be changed for each operation in vector-matrix operations in a photoelectronic parallel multiplier, and positive and negative operations using light can be performed. Since the structure is configured such that this is possible, it has the effect of dramatically improving the functionality of the optoelectronic parallel multiplier. By using the optoelectronic parallel multiplier of the present invention as hardware for a neural network, its functionality can be dramatically improved.

[Brief explanation of drawings]

[Figure 1] Simple conceptual diagram of the present invention

[Figure 2] Circuit diagram of the PD array in Figure 1

[Figure 3] S-
Energy band diagram showing HPT operation

[Figure 4] S-H
Energy band diagram showing PT operation

[Figure 5] S-HP
Energy band diagram showing the operation of T

[Figure 6] Conceptual diagram of a conventional optoelectronic parallel multiplier

[Figure 7] Circuit diagram of the PD array in Figure 6

[Figure 8] Energy band diagram showing the operation of a PIN photodiode

[Explanation of symbols]

1 LED array 2 Light receiving device 3 LED electrode 4 Light receiving device electrode

Claims (3)

[Claims] Claim 1: A light-emitting device in which a plurality of light-emitting elements are arranged in a two-dimensional array, and a plurality of phototransistors.
A photoelectronic parallel multiplier comprising light receiving devices arranged in a dimensional array so that the light receiving current of each phototransistor can be controlled independently from the outside. 2. The phototransistor is composed of a floating base heterojunction transistor, and the width of the depletion layer of the heterojunction part of the floating base heterojunction transistor is controlled by the emitter-collector voltage of the floating base heterojunction transistor, thereby increasing the light receiving current. 2. The optoelectronic parallel multiplier according to claim 1, wherein the optoelectronic parallel multiplier is configured to control. [Claim 3] The phototransistor is composed of an emitter and a collector made of the same material, and has a symmetrical npn structure.
2. The photoelectronic parallel multiplier according to claim 1, wherein the photoelectronic parallel multiplier has a pnp structure so that the photocurrent of the phototransistor can flow in both directions.