JPH0431331B2 - - Google Patents

Description

[Detailed description of the invention]

<Industrial Application Field> The present invention relates to a capacitive differential pressure transmitter that converts displacement based on a change in a physical quantity such as pressure into an electrical signal via capacitance, and particularly relates to a capacitive differential pressure transmitter that converts displacement based on a change in a physical quantity such as pressure into an electrical signal, and in particular, This invention relates to a capacitive differential pressure transmitter that eliminates the influence of capacitance. <Prior art> Such a capacitive differential pressure transmitter detects the flow rate or pressure of various processes as a change in capacitance, converts it into an electrical signal, and transmits it to a distant receiving section, etc. It is used in An example of such a conventional capacitive differential pressure transmitter is shown in the sixth example.
It is shown in the figure and will be explained. Fixed electrodes 11 and 12 are arranged facing the moving electrode 10, and have a capacitance that functions as a sensor capacitance.
C ₁ and C ₂ are formed. In addition, the moving electrode 10
A distributed capacitance C _s is formed between and the case. The connection point between the capacitances C ₁ and C ₂ is connected to the input end of the inverter G ₁ , and a constant value current limiting circuit CC ₁ is connected in negative feedback between the output end and the input end of the inverter G 1 .
The output end of inverter _G1 is an n-bit counter.
It is connected to the input terminal CL of CT ₁ , and its output terminal Q _o is connected via a NAND gate G ₂ to a fixed electrode 11 forming the first electrode of capacitance C ₁ , and at the same time connects an inverter G ₃ and a NAND gate G ₄ . It is connected via a fixed electrode 12 forming a second electrode of capacitance C ₂ . Furthermore, the other input ends of the NAND gates G ₂ and G ₄ are connected to the output end of the inverter G ₁ . With this configuration, the first positive feedback loop to the inverter _G1 is formed by the NAND gate _G2 and the capacitance _C1 ,
Inverter G ₁ with NAND gate G ₄ and capacitance C ₂
These loops are connected to the NAND gates G 2 and ₂ by the output of the counter CT ₁ .
The oscillation is continued by switching alternately via _G4 . The output of the counter _CT1 is smoothed by a filter circuit _FC1 . Now, as shown in Figure 7A, the output A of NAND gate _G2 is set to high level "H", and the voltage +E is applied here.
When this occurs, the capacitance increases due to its rise.
The combined capacitance C _t of C ₁ , distributed capacitance C _s , and electrostatic capacitance C ₂ is charged in series, and the input terminal of inverter G ₁ suddenly reaches a constant voltage and rises almost vertically as shown in Figure 7B. . Therefore, the change e ₁₀ in the terminal voltage of the distributed capacitance C _s with respect to the threshold level V _TH of the inverter G ₁ is expressed by the following equation. e ₁₀ = C ₁ / C ₁ + C _t E (1) At this time, the output C of the inverter G ₁ is at the low level “L”, but the constant value current limiting circuit CC ₁ is connected between the input and output terminals of the inverter G ₁ . Since they are connected, the charges in the distributed capacitance C _s and the capacitance C ₂ immediately start discharging via the constant value current limiting circuit CC ₁ and the output impedance of the inverter G ₁ .
However, since the discharge current i caused by this discharge is regulated to a constant current value by the constant value current limiter circuit _CC1 , the voltage at the input terminal of the inverter _G1 has a threshold value that decreases linearly, as shown in FIG. 7B. Discharge time required to decrease to hold level V _{TH 10}
is obtained from the following equation. it ₁₀ = e ₁₀ (C ₁ + C _t ) (2) From equations (1) and (2), t ₁₀ = C ₁ E/i (3). Threshold level V _TH of inverter G ₁
When _the voltage drops to
Output A of NAND gate _G2 becomes “L” level,
The voltage at the input terminal of inverter G ₁ has the same value as equation (1) and has the opposite polarity e′ ₁₀ . After this, constant value current limit circuit
CC ₁ causes a discharge of opposite polarity to occur linearly.
As a result, when the threshold level _VTH of inverter _G1 is reached, the output C of inverter _G1 is inverted as shown in FIG. 7C. This reverse polarity discharge is also carried out with a constant value of current i, so the discharge time
t' ₁₀ is also equal to t ₁₀ , so t ₁₀ = t' ₁₀ (4). These relationships are the same even when the output of the counter CT ₁ is switched to the capacitance C ₂ side after the counter CT ₁ has counted a predetermined value, so the following equation holds true. t ₂₀ = C ₂ E/i (5) Therefore, during the “H” period of the pulse signal obtained from the output Q _o of the counter CT ₁ , the capacitance C ₁ is “L”
The period corresponds to the capacitance C ₂ , and if this is averaged by the filter circuit FC ₁ , the calculation result of C ₁ /(C ₁ +C ₂ ) related to the duty ratio of the pulse signal is obtained. This calculation result provides a value proportional to the displacement of the moving electrode 10, that is, the differential pressure (P _H - P _L ).
Furthermore, the distributed capacitance C _s has been removed. <Problems to be Solved by the Invention> However, although the distributed capacitance C s distributed between the moving electrode 10 and the case can be removed by conventional techniques, the distributed capacitance C _s that is formed between the moving electrode 10 and the conversion circuit If a distributed capacitance such as, for example, a distributed capacitance C _s0 is formed at both ends of the constant value current limiting circuit CC ₁ as shown in FIG. 6, an error will occur. When the distributed capacitance C _s0 is formed across the constant value current limiting circuit CC ₁ , considering equation (1), there are two cases: switching to the capacitance C ₁ side and switching to the capacitance C ₂ side. Since the voltage changes e _{10 and e 20} at the input end _{of inverter} G ₁ that occur in This has the disadvantage of being different and creating an error factor. <Means for Solving the Problems> The present invention solves the above problems and further provides a method for obtaining the relative change amount of the capacitances C ₁ and C ₂ as numerical data inside the microcomputer. , first and second sensor capacitances that change according to the differential pressure, and an input end connected to a common connection point to which each end of the sensor capacitance is connected, and in response to a change in input voltage exceeding a predetermined threshold. A detection gate means for changing an output level, a negative feedback means for supplying a negative feedback current to a common connection point in response to a change in the output level of the detection gate means, and a microcomputer for reading a change in the output level of the detection gate means. , first and second excitations, one of which is selected by the microcomputer, transmits a change in the output level of the detection gate means to the first and second sensor capacitors, and excites the other ends of the first and second sensor capacitors. a gate, and a digital-to-analog converter for converting the digital signal from the microcomputer into a voltage signal and transmitting the voltage signal to the first and second excitation gates to modulate the excitation amplitude for the first and second sensor capacitances. and a transmission means for transmitting a signal from the microcomputer to the outside, and the microcomputer includes a first signal from the detection gate means.
and reading the changes in the first and second output levels associated with the capacitance of the second sensor capacitor and manipulating the digital signals to the digital-to-analog converter such that these readings match the corresponding digital signals. The configuration is such that the information is supplied to the transmission means. <Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is an overall block diagram showing one embodiment of the present invention. The moving electrode 10 is connected to the input end of a buffer gate _G5 serving as a detection gate means, and its output end is connected in negative feedback to the input end of the buffer gate _G5 via an inverter _G6 and a constant current limiting circuit _CC1 . There is. Further, the output terminal of the buffer gate _G5 is connected to the input terminal of the microcomputer μCOM via a line 13. Microcomputer μCOM
Lines 14 and 15 are drawn out from AND gates G ₇ and G ₈ which function as excitation gates, respectively.
connected to one end of the input. The other input ends of AND gates G ₇ and G ₈ are respectively connected to the output end of buffer gate G ₅ .
The output terminals of the AND gates G ₇ and G ₈ are connected to the fixed electrodes 11 and 12, respectively, and the first loop (buffer gate G ₅ −AND gate G ₇ −capacitance C ₁ −
A first positive feedback circuit is formed with buffer gate G ₅ ), and a second loop (buffer gate G ₅ -AND gate G ₈ -capacitance C ₂ -buffer gate G ₅ ) is formed.
A second positive feedback circuit is formed. These loops are line 1 from the microcomputer μCOM.
It is switched to either one by loop switching signals LS ₁ and LS ₂ applied to one end of the input of AND gates G ₇ and G ₈ via terminals 4 and 15. The microcomputer μCOM reads the changes in the output level of the buffer gate G ₅ in relation to the capacitance values of the capacitors C ₁ and C ₂ provided via the line 13 and outputs a digital signal with which these readings coincide.
Sends a digital signal to the analog converter DAC.
The digital-to-analog converter DAC converts the digital signal into a corresponding analog variable voltage V and energizes the AND gates G ₇ and G ₈ . For example, C-MOS devices are used for the AND gates _G7 and _G8 , and the logic output level thereof is provided by the energizing voltage values +E and V, or V and -E. The variable voltage V is a value within the range of the fixed energized voltage ±E. Further, the microcomputer μCOM outputs a value corresponding to the digital signal to the output circuit OC, and transmits a current of, for example, 4 to 20 mA to a distant place via the line 16. Furthermore, between the moving electrode 10 and the output end of the buffer gate _G5 or the output end of the inverter _G6 ,
Distributed capacitances C _s1 and C _s2 are generally formed, respectively. Note that the buffer gate G ₅ and the NAND gate G ₆ are composed of C-MOS devices, and are energized with a fixed voltage of ±E. FIG. 2 is a block diagram showing the internal configuration of the microcomputer μCOM in FIG. 1. A frequency signal that selects capacitance C ₁ and a frequency signal that selects capacitance C ₂ are selectively generated on line 13, but these frequency signals are transmitted in synchronization with the internal clock. synchronization circuit
It is input to SYC, synchronized with internal clock CLK ₂ , counted by integration counter CT ₂ , and sent to bus BUS.
sent to. When the integration counter _CT2 integrates frequency signals of 100 KHz or less and reads them every 1 millisecond, its bit size may be set to 8 bits. ROM is a program memory, RAM is a data memory, and the microprocessor CPU uses data stored in the data memory RAM to perform necessary operations according to the program memory ROM. The clock signal CLK ₁ generated by the clock generator CLG is input to the microprocessor CPU,
This advances the microprocessor CPU. Also, the clock signal CLK ₁ is used as a ring counter.
Step-down by RCT to internal clock
CLK ₂ and is used as a clock signal for input/output operations. Further, a clock signal _CLK3 is inputted to the microprocessor CPU from an arbitrary output terminal of the ring counter RCT, thereby providing timing for real-time interrupts of input/output services of the microprocessor CPU. If the frequency signal from line 13 is about 30-100KHz,
1MHz each as CLK ₁ , CLK ₂ , CLK ₃ ,
Values such as 200KHz and 1KHz are selected. The microcomputer CPU receives frequency signals f ₁ , corresponding to the capacitances C ₁ and C ₂ from line 13, respectively.
f ₂ is input, signal processing is performed so that a variable voltage V that matches these frequency signals f ₁ and f ₂ is outputted, and the signal is outputted to the output port OP via the bus BUS. The output port OP simply latches data from the microcomputer. The digital-to-analog converter DAC which receives data from the output port OP and outputs a variable voltage V is composed of a rate multiplier RM, an inverter _G9 , an AND gate _G10 , an OR gate _G11 , and a smoothing circuit _FC2 . The data D _SET from the output port OP is, for example, D ₁ ,
It has a 12-bit configuration of D ₂ to _{D 12} , of which D ₁ and D ₂
The 11 bits of ~ _D11 are set to the rate multiplier RM. The rate multiplier RM receives an internal clock CLK ₂ at its input terminal IN, multiplies it by a digital value / ²¹¹ given by the set data D ₁ , D ₂ to _{D 11} , and outputs the result to its output terminal OUT. As the rate multiplier RM, a type in which input and output phases are inverted, for example, a commercially available CMOS device such as TC4527BP (Toshiba) can be used. Data from output port OP Data out of D _SET
D12 is applied via an inverter _G9 to one input of an AND gate _G10 , the other input of which is applied with an internal clock _CLK2 . or gate
One end of the input of _G11 is connected to the output end of AND gate _G10 , and the other end of its input is connected to the output end of rate multiplier RM. or gate
The output of G ₁₁ is applied to the filter circuit FC ₂ and the data
Outputs analog variable voltage V corresponding to D _SET . In addition, ORGATE G ₁₁ , ANDGATE G ₁₀ ,
Inverter _G9 etc. are energized with voltage ±E. The microprocessor CPU sends 2-bit loop switching signals LS ₁ and LS ₂ to lines 14 and 15 via output port QP, thereby selecting the positive feedback circuit. Next, FIGS. 1 and 2 configured as described above will be explained.
The operation of the embodiment shown in the figure will be explained. First, the operation based on the overall configuration shown in FIG. 1 will be explained using the waveform diagram shown in FIG. 3. The loop switching signals LS ₁ and LS ₂ (Fig. 3 E and F) from the microcomputer μCOM open and close the AND gate G ₇ or G ₈ in a complementary manner, and the capacitance increases.
Either the loop on the C ₁ side or the C ₂ side is selected, and the output terminals of the AND gates G ₇ and G ₈ are
The voltage shown in D is output. With either of these positive feedback loops selected, when the output level of buffer gate _G5 changes as shown in Figure 3B, AND gate _G7 or
Positive or negative voltage changes e ₁ (=e′ ₁ ) and e ₂ (=e′ ₂ ) are applied to the input terminal of the buffer gate G ₅ via G ₈ as the third
This occurs as shown in Figure A. The voltage changes e ₁ and e ₂ that occur in this case are as shown in the following equation when considering charge transfer to the input terminal of the buffer gate G ₅ via each capacitor. e ₁ = C ₁ (EV) + C _s1・2E−C _s2・2E/C ₁ +C ₂ +
C _s +C _s1 +C _s2 (6) e ₂ =C ₂ (E+V) +C _s1・2E−C _s2・2E/C ₁ +C ₂ +
C _s +C _s1 +C _s2 (7) These voltage changes e ₁ and e ₂ are applied to the input terminal of buffer gate G ₅ via inverter G ₆ and constant current limiter CC ₁ by constant current i as shown in Fig. 3A. Negative feedback takes time t ₁ (=t' ₁ ) and t ₂ (=t' ₂ ) at a constant slope and is pulled back to the threshold level of buffer gate G ₅ . From the above explanation, the times t ₁ and t ₂ in this case are as shown in the following equation. t ₁ = e ₁ (C ₁ + C ₂ + C _s + C _s1 + C _s2 )/i (8) t ₂ = e ₂ (C ₁ + C ₂ + C _s + C _s1 + C _s2 )/i (9) Here, on line 13 Each capacitance C ₁ generated in
The microcomputer μCOM controls to apply the variable voltage V to the AND gates _G7 and _G8 so that the frequency signals _f1 and _f2 corresponding to _C2 match.
This means that t ₁ = t ₂ , so the following equation is obtained using equations (6) to (9) and the condition that t ₁ = t ₂ . V = C ₁ - C ₂ / C ₁ + C ₂ E (10) Here, the capacitances C ₁ and C ₂ are as follows, with C ₀ as the capacitance when the differential pressure ΔP is zero, and K ₁ as a constant. It is shown by the formula. C ₁ = C ₀ 1/1-K ₁ ΔP (11) C ₂ = C ₀ 1/1-K ₁ ΔP (12) Substituting these equations into equation (10), V=K ₁ E・ΔP (13) The variable voltage V is proportional to the differential pressure ΔP. Moreover, this equation (13) does not include the distributed capacitances C _s1 and C _s2 between the moving electrode 10 and the conversion circuit, and the influence of these distributed capacitances is removed. In addition, Figure 3 (b) shows the output waveform of the buffer gate.
FIG. 3 shows the output waveforms of inverter _G6 . Next, the microcomputer μCOM shown in Figure 2
and its surrounding operations will be explained using waveform diagrams shown in FIGS. 4 and 5. Either the positive feedback circuit on the capacitance C ₁ side or C ₂ side is selected by the loop switching signal LS ₁ or LS ₂ , and the frequency signal f ₁ or f ₂ (Figure 4 A) is selected.
is input to the synchronization circuit SYC and the internal clock CLK ₂
(Figure 4 B) is synchronized with the integration counter.
It is input to the input terminal CL of CT ₂ (Fig. 4 C). The respective outputs shown in FIG. 4 are generated at the output terminals Q ₁ , Q ₂ -Q ₈ of each bit of the integration counter CT ₂ in response to the CL input. The respective outputs generated at the output terminals Q ₁ , Q ₂ -Q ₈ of the integration counter CT ₂ in this manner are read by the microprocessor CPU at the timing indicated by the clock signal CLK ₃ shown in FIG. If this reading is repeated 20 times for each frequency signal f ₁ or f ₂ , sufficient resolution can be obtained by treating the signal frequency of 100 KHz as a numerical value of 2000. A microprocessor CPU that outputs a variable voltage V whose values match the read frequency signals f ₁ and f ₂ from an analog-to-digital converter DAC.
calculates and outputs digital data D _SET to inverter G ₉ and rate multiplier RM via output port OP. FIG. 5 shows waveforms at various parts of the analog-to-digital converter DAC. In particular, in this case D ₁₁ ~
The waveforms of various parts are shown when data _D12 changes from 0 to 1 in a state where all bits of _D1 are 1. _D12 determines the sign of digital data _DSET . As shown in FIG. 5B, when the data _D12 is zero, the clock signal _CLK2 is output as is to the output terminal of the AND gate _G10 (FIG. 5C).
At the output terminal OUT of the rate multiplier RM, an output obtained by inverting the phase of the clock signal _CLK2 is obtained as shown in FIG. 5D. Therefore, orgate
Since the clock signal _CLK2 and its inverted clock signal are applied to each input terminal of _G11 , a voltage of +E is generated at its output terminal. When data D ₁₂ is inverted to 1 level, the output of AND gate G ₁₀ is maintained at 0 level (Figure 5 C), and the output of OR gate G ₁₁ is the output of rate multiplier RM (Figure 5 D). occurs as is (Fig. 5, E).
Therefore, +E and -E voltages are generated alternately, and their average value is approximately zero. Based on the above points, the relationship between the binary representation of the values of data D ₁₂ to _{D 1} and the average voltage V of the output of OR gate G ₁₁ is as follows.

[Table] In other words, the variable voltage V is proportional to the value obtained by multiplying the digital data of D ₁₂ to _{D 1} by the energizing voltage value E.
If K ₂ is a constant (=1/2 ¹¹ ), then V=D _SET・E・K ₂ (14). From equations (13) and (14), D _SET =K ₁ /K ₂ ΔP (15), and the differential pressure ΔP is obtained in the microcomputer μCOM as digital data. This data D _SET is output on line 16 via the output circuit OC. <Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the distributed capacitance formed between the moving electrode and the conversion circuit can be removed, and the output proportional to the change in differential pressure can be generated. It can be digitized and output, making it possible to create a highly accurate capacitive differential pressure transmitter.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention;
2 is a block diagram showing the configuration of the microcomputer and its surroundings in FIG. 1; FIG. 3 is a waveform diagram showing waveforms of various parts of the embodiment shown in FIG. 1;
Figure 4 is a waveform diagram showing waveforms at the input section in Figure 2, Figure 5 is a waveform diagram showing waveforms at various parts of the analog-to-digital converter in Figure 2, and Figure 6 is a conventional capacitive differential pressure transmission. FIG. 7 is a waveform diagram showing the waveforms of each part in FIG. 6. 10... Moving electrode, 11, 12... Fixed electrode,
G ₅ ... Buffer gate, G ₆ ... Inverter, G ₇ ,
G ₈ ...AND gate, CC ₁ ... Constant value current limit circuit, C ₁ , C ₂ ... Capacitance, C _s , C _s1 , C _s2 ... Distributed capacitance, μCOM ... Microcomputer, DAC
...Digital-to-analog converter, OC...Output circuit.

Claims (1)

[Claims] 1. First and second sensor capacitors that change according to the differential pressure, and an input end connected to a common connection point to which each end of the sensor capacitors are connected, and in response to a change in input voltage that exceeds a predetermined threshold. detection gate means for changing the output level; negative feedback means for supplying a negative feedback current to the common connection point in response to changes in the output level of the detection gate means; and a microcontroller for reading changes in the output level of the detection gate means. a computer, one of which is selected by the microcomputer, transmits a change in the output level of the detection gate means to the first and second sensor capacitors, and excites the other end of each of the first and second sensor capacitors; 1
and a second excitation gate, which converts the digital signal from the microcomputer into a voltage signal, transmits the voltage signal to the first and second excitation gates, and modulates the excitation amplitude for the first and second sensor capacitors. and a transmission means for transmitting a signal from the microcomputer to the outside; Changes in the related first and second output levels are read and the digital output level is adjusted so that these read values match.
A capacitive differential pressure transmitter, characterized in that the digital signal to the analog converter is manipulated to supply a corresponding digital signal to the transmission means.