JPH04313896A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize a semiconductor storage device such as an EEPROM which tries to reduce write time. CONSTITUTION:The output of an X decoder 9 is connected to a word line WL of a memory cell array 1 through X latches 31 and 32 and the output of a Y decoder 10 is given to a write driver circuit 7 through an input latch 34 which is provided for each of the Y decoder 10 outputs. And a timer output signal S17 of a timer circuit 17 as a control signal, the first portion external write cycle in the write-in operation of the (I+1) cycle (I>=1) and an internal write cycle in the I cycle write operation are executed in parallel without interfering each other. A shorter write period is realized because the two cycles are executed in parallel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that performs a write operation of an EEPROM or the like using an external write cycle and an internal write cycle.

0002

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a conventional EEPROM. As shown in the figure, memory cells 2 are arranged in a matrix in a memory cell array 1 (one memory cell is shown in FIG. 5). The memory cell 2 is configured by a series connection of a selection transistor SQ and a memory transistor MQ that performs non-volatile storage, the drain of the selection transistor SQ is connected to the bit line BL, and the memory transistor M
The source of Q is grounded via source transistor 3. The control gate of the memory transistor MQ is connected to the control gate line CGL via the byte selection transistor T1 (FIG. 5 shows a 1 byte 1 bit configuration). Further, a word line WL is connected to the gate of the byte selection transistor T1 and the gate of the selection transistor SQ.

[0003] Bit line BL, control gate line CG
One end of each L is connected to a column latch 4 (including a high voltage switch function). The column latch 4 has one latch portion corresponding to one control gate line CGL and one bit line, respectively. The other end of the control gate line CGL is connected to the control gate circuit 6 via the Y gate transistor YG1 in the Y gate circuit 5, and the other end of the bit line BL is connected to the control gate circuit 6 via the Y gate transistor YG2 in the Y gate circuit 5. Connected to write driver circuit 7 and sense amplifier 8.

One end of word line WL is connected to X decoder 9, and the other end is connected to high voltage switch 18. Also,
A Y gate line YL of a Y decoder 10 is connected to the gates of the Y gate transistors YG1 and YG2, and a write circuit 15 and a read circuit 16 are connected to the gates of the source transistor 3. X decoder 9 selectively sets word line WL to H level based on the row address taken in from address buffer 12. Based on the column address fetched from the address buffer 12, the Y decoder 10
The Y gate line YL is selectively set to H level to selectively turn on the Y gate transistors YG (YG1, YG2).

A control signal buffer circuit 13 buffers external control signals such as a chip enable signal CE, a write enable signal WE, and an output enable signal OE. Based on the external control signal buffered by the control signal buffer circuit 13, the (write, read) standby control circuit 14:
Address buffer 12, X decoder 9, Y decoder 10
, the write circuit 15, the read circuit 16, and the input buffer 20, respectively.

When the write circuit 15 receives a control signal instructing startup from the standby control circuit 14, it provides a write control signal to the control gate circuit 6, write driver circuit 7, and timer circuit (boosting circuit) 17, respectively, and also outputs an H A level signal is applied to the gate of the source transistor 3. When the timer circuit 17 receives a write control signal instructing an internal write cycle to be described later,
Column decoder 4 outputs high voltage pulses that are in a high voltage state for a predetermined period of time.
and outputs to the high voltage switch 18, and then outputs L for a predetermined period of time.
level. On the other hand, when the readout circuit 16 receives the readout control signal, it gives a readout instruction to the control gate circuit 6 and the sense amplifier 8, and also gives an H level signal to the gate of the source transistor 3.

In addition, external input/output data is taken in to the write driver circuit 7 via the input/output buffer 19 and input buffer 20, while the output of the sense amplifier 8 is taken in via the output buffer 21 and the input/output buffer 19. , is output to the outside as external read data.

In such a configuration, data writing operation to memory transistor MQ is performed as shown below. First, by applying an external control signal instructing write to the control signal buffer circuit 13, the write circuit 15 is activated by the control signal of the standby control circuit 14. Memory transistor M to be written at the same time
A row address and a column address defining Q are given to an X decoder 9 and a Y decoder 10, respectively, via an address buffer 6, and write data is given to an input/output buffer 19 from the outside.

Then, the X decoder 9 selectively sets the word line WL to H level, and the Y decoder 10 sets the Y gate line YL to the H level.
is selectively set to H level to selectively turn on Y gate transistors YG1 and YG2. Then, from the control gate circuit 19, the on-state Y gate transistor Y
H-level write control data instructing the column latch 4 to write is latched via G1 and the control gate line CGL connected thereto. At the same time, an output signal from the write driver circuit 7 based on the write data is stored in the column latch 4 via the on-state Y gate transistor YG2 and the bit line BL connected thereto. In this way, one byte of data is written.

Furthermore, when writing data to other memory transistors connected to the same word line (
Below, this write is called "multi-byte data write".
Say. ) keeps the row address fixed, changes only the column address, changes the output of the Y decoder 10, turns on the Y gate transistors YG1 and YG2, which are different from the previous one, and writes new write data from the outside to the input/output buffer 19. give. Then, write control data is stored in the column latch 4 from the control gate circuit 19 via the Y gate transistor YG1 in the on state and the control gate line CGL connected thereto. At the same time, an output signal from the write driver circuit 7 based on the new write data is stored in the column latch 4 via the on-state Y gate transistor YG2 and the bit line BL connected thereto. By repeating this operation, multiple bytes of data are written.

In this way, the control gate line CGL and bit line BL sequentially selected by the Y decoder 10
Write control data and write data are respectively stored in column latches 4 corresponding to .

As described above, the operation until the column latch 4 latches a predetermined number of bytes of write data obtained from the outside is an external write cycle. When this external write cycle ends, the process moves to an internal write cycle.

When entering the internal write cycle, the timer circuit (boosting circuit) 17 generates a high voltage pulse for a predetermined period of time, activating the high voltage switch in the column latch 4 and the high voltage switch 18. In this state, the column latch 4 fixes all the bit lines BL to the L level and sets the control gate line CGL connected to the latch portion storing the H level to the high voltage VPP. At the same time, the high voltage switch 18 raises the H level word line WL to the high voltage VPP.

As a result, the threshold voltage of the selected memory transistor MQ is increased by being connected to the word line WL and the control gate line CGL to which the high voltage VPP is applied, and the memory transistor MQ is brought into an erased state ("1" written). Ru.

Next, the column latch 4 fixes all the control gate lines CGL to the L level, and sets the bit line BL connected to the latch portion storing the H level to the high voltage VPP. At this time, the high voltage switch 18 maintains the high voltage VPP of the word line WL.

As a result, the threshold voltage of the memory transistor MQ connected to the word line WL and bit line BL to which the high voltage VPP is applied is lowered, and the write state (“0”
written).

As described above, the cycle in which the threshold voltage for the selected memory transistor MQ is changed based on the data stored in the column latch 4 is an internal write cycle.

As described above, the conventional EEPROM executes a write operation using an external write cycle and an internal write cycle.

Next, the read operation will be explained. First, a control signal instructing readout is applied to the control signal buffer circuit 13, and the readout circuit 16 is activated by a control signal from the standby control circuit 14. At the same time, a row address and a column address defining the memory transistor MQ to be read are given to the X decoder 9 and Y decoder 10, respectively, via the address buffer 6.

Then, the X decoder 9 selectively sets the word line WL to H level, and the Y decoder 10 sets the Y gate line YL to the H level.
is selectively set to H level to selectively turn on Y gate transistors YG1 and YG2. Then, from the control gate circuit 19, the on-state Y gate transistor Y
H level is applied to G1 and the control gate line CGL, the selected memory transistor MQ is turned on/off based on its threshold voltage, this on/off is detected by the sense amplifier 8, and read data is read based on the detection result. , output to the outside via the output buffer 21 and the input/output buffer 19.

[0021]

[Problem to be Solved by the Invention] Conventional semiconductor storage devices such as EEPROMs are configured as described above, and write operations are performed in the sequence of performing an external write cycle and then performing an internal write cycle. There is. Therefore, since the write operation is performed in two cycles, there is a problem in that writing takes a long time.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device in which write time is shortened.

[0023]

[Means for Solving the Problems] A semiconductor memory device according to the present invention has memory cells arranged in a matrix, and has an external writing method for storing external data in a first latch designated by the output of a column decoder. cycle and the first memory cell indicated by the output of the row decoder.
A write operation is performed by an internal write cycle that writes data based on the data stored in the latch of
The external write cycle is a first partial external write cycle in which external data is stored in a second latch indicated by the output of a column decoder, and the data stored in the second latch is stored in the second latch. A second partial external write cycle is transferred to the first latch, and when the write operation is executed continuously, the first partial external write cycle in the write operation of the (I+1)th cycle (I≧1) is performed. A write cycle and the internal write cycle in the I-th cycle write operation are executed in parallel without affecting each other.

[0024]

[Operation] In this invention, when writing operations are executed continuously, the first partial external write cycle and the I-th cycle in the write operation of the (I+1)th cycle (I≧1)
In order to execute the internal write cycle in the write operation of the cycle in parallel without affecting each other, in the write operation after the second cycle, the (I+
1) The first partial external write cycle in the write operation of the cycle and the internal write cycle in the write operation of the I-th cycle are performed in parallel;
+1) The actual execution time of an external write cycle in a cycle write operation is reduced.

[0025]

[Embodiment] Fig. 1 shows an EEPRO which is an embodiment of this invention.
FIG. 2 is a block diagram showing the configuration of M. As shown in the figure,
The output of the X decoder 9 is connected to the word line WL of the memory cell array 1 via two stages of X latches 31 and 32 connected in series, and the output of the Y decoder 10 is also connected to the Y latch 33.
It is connected to the Y gate line YL via. Further, the output of the input buffer 20 is also provided to the write driver circuit 7 via the input latch 34. The input latch 34 is provided corresponding to each output of the Y decoder 10 (that is, the Y gate line YL), and as will be described in detail later, the input latch 34
The Y decoder 10 corresponding to each input latch 34 controls electrical connection/cutoff between the input buffer 20 and the input buffer 20.
This is done based on the output of

Then, the (write, read) standby control circuit 30 controls the address buffers 12,
The control signal S30A is given to the decoder 9, the Y decoder 10, and the input buffer 20, and the control signal S30A is given to the write circuit 15 and the read circuit 16, respectively.
Give B. Note that the other configurations are the same as the conventional example shown in FIG. 5, so explanations will be omitted.

FIG. 2 shows the X latches 31 and 32 shown in FIG.
FIG. 2 is a circuit diagram showing the internal configuration of. As shown in the figure, the X latch 31 is
The X latch 32 is configured by loop-connecting inverters 43 and 44. Between the X latch 31 and the X latch 32, a P channel transistor 45 whose gate is applied with the timer output signal S17 of the timer circuit 17 is provided.
is inserted. Note that the same figure shows a pair of X latches 31 and 32 provided for each output of one X decoder 9 (that is, word line WL), and in reality, one set of X latches 31 and 32 is provided for each output of one X latches 31 and 32 shown in are provided.

FIG. 3 shows the standby control circuit 3 shown in FIG.
FIG. 2 is a circuit diagram showing the internal configuration of 0. As shown in the figure,
The standby control circuit 30 includes a standby control section 35 and a read/write control section 36.

The standby control section 35 corresponds to the conventional standby control circuit 14 shown in FIG. 10 and the input buffer 20, respectively, with a control signal S30A.
give.

The read/write control unit 36 includes inverters 46 and 50, NOR gates 47 and 48, a P-channel transistor 49, and a delay circuit 51 (delay time TD1), and takes in the control signal S30A as an input signal to the inverter 46. Then, the output of the inverter 46 is taken in as one input of the NOR gate 47, and the NOR
The output of the gate 47 becomes one input of the NOR gate 48, and the control signal S is sent via the P-channel transistor 49.
It is output as 30B. NOR gate 48 takes in the output of inverter 59 as the other input, and the output is fed back as the other input of NOR gate 47. Therefore, the latch section 37 is constituted by the NOR gates 47 and 48. Furthermore, a signal from the timer output signal S17 of the timer circuit 17 via the delay circuit 51 is applied as an input to the inverter 50.

The latch section 37 having the above structure is connected to the inverter 5.
When the output of NOR gate 48 is H, a reset is applied and the output of NOR gate 48 is set to L level. On the other hand, when the output of the inverter 50 is L, it becomes active, and the inverter 46
When the output of is H, L is latched at node N1, and this L
The level will be held until reset.

FIG. 4 is a circuit diagram showing the internal structure of Y latch 33 and input latch 34 shown in FIG. 1. As shown in the figure, the Y latch 33 includes NOR gates 52, 53, P
Consisting of a channel transistor 54, an inverter 55, and a delay circuit 56 (delay time TD2), the Y decoder 1
The output of 0 becomes one input of the NOR gate 52, and this
The output of the OR gate 52 becomes one input of the NOR gate 53.

The output of the inverter 55 is applied as the other input of the NOR gate 53, and the output is applied to the Y gate line YL via the P channel transistor 54, and is fed back as the other input of the NOR gate 52. Therefore, the latch section 3
8 is composed. Also, as an input to the inverter 55,
Timer output signal S17 is applied via delay circuit 56.

The latch section 38 having the above structure is connected to the inverter 5.
When the output of node N2 is H, a reset is applied and the potential of node N2 is set to L level. On the other hand, when the output of the inverter 55 is L, it becomes active, and when the output of the Y decoder 10 is H, H is latched at the node N2, and this H level is held until a reset is applied.

On the other hand, the input buffer 34 is constituted by an N-channel transistor 57, inverters 58, 59, and a P-channel transistor 60 connected in series, and a latch section 39 is constituted by a loop connection of the inverters 58, 59. The output of the corresponding Y decoder 10 is applied to the gate of the N-channel transistor 57, and the timer output signal S17 is applied to the gate of the P-channel transistor 60.
will be granted.

Note that in FIG. 4, one Y decoder 10 has a
In reality, each output line of the Y decoder 10 is provided with the Y latch 33 and input latch 34 shown in FIG.

In such a configuration, data writing to a plurality of memory transistors MQ connected to different word lines is performed as shown below. Hereinafter, for convenience of explanation, after performing the first cycle write operation to the memory transistor MQ connected to the first word line WL1, the write operation is sequentially performed to the memory transistor MQ connected to the second word line WL2. An example will be described in which a write operation in the second cycle is performed.

First, by applying an external control signal instructing write to the control signal buffer circuit 13, the write circuit 15 is activated by the control signal S30B from the standby control circuit 30. At the same time, the row address and column address that define the memory transistor MQ to be written are given to the X decoder 9 and the Y decoder 10, respectively, via the address buffer 6, and the write data is given from the outside to the input/output buffer 19. enter the cycle.

At this time, the timer output signal S17 of the timer circuit 17 is at L level, and the P channel transistor 45 between the X latches 31 and 32, the P channel transistor 49 in the standby control circuit 30, and the P channel transistor in the Y latch 33 Since the transistor 54 and the P-channel transistor 60 in the input latch 34 are all on, the X decoder 9 sets the word line WL1 to H level, as in the conventional case.
The Y decoder 10 selectively brings the Y gate line YL to H level and selectively turns on the Y gate transistors YG1 and YG2. The column latch 4 is then connected from the control gate circuit 19 to the on-state Y gate transistor YG1 and the control gate line CGL connected thereto.
H-level write control data that instructs writing is stored. At the same time, an output signal from the write driver circuit 7 based on the write data is stored in the column latch 4 via the on-state Y gate transistor YG2 and the bit line BL connected thereto. In this way, one byte of data is written.

Furthermore, when data is written to other memory transistors connected to the first word line WL1 (hereinafter, this writing is referred to as "multi-byte data writing"), the column address is fixed while the row address is fixed. Only the address is changed, the output of the Y decoder 10 is changed, Y gate transistors YG1 and YG2, which are different from the previous one, are turned on, and new write data is given to the input/output buffer 19 from the outside. Then, control gate circuit 1
9, write control data is stored in the column latch 4 via the Y gate transistor YG1 in the on state and the control gate line CGL connected thereto. at the same time,
The output signal from the write driver circuit 7 based on the new write data is transmitted to the on-state Y gate transistor YG.
2 and the bit line BL connected thereto, the data is stored in the column latch 4. By repeating this operation, multiple bytes of data are written.

In this way, write control data and write data are respectively stored in the column latches 4 corresponding to all the control gate lines CGL and bit lines BL selected by the Y decoder 10.

As described above, the operation up to latching a predetermined number of bytes of write data obtained from the outside into the column latch 4 is an external write cycle. In the first cycle write operation, when the external write cycle ends, the internal write cycle begins.

When the internal write cycle begins, the timer output signal S17 of the timer circuit (boosting circuit) 17 generates a high voltage pulse, thereby activating the high voltage switch in the column latch 4 and the high voltage switch 18.

At the same time, the P channel transistor 45 between the X latches 31 and 32, the P channel transistor 49 in the standby control circuit 30, the P channel transistor 54 in the Y latch 33, and the P channel transistor 60 in the input latch 34 are all turned off. state.

Column latch 4 fixes all bit lines BL to L level and sets control gate line CGL connected to the latch portion storing H level to high voltage VPP. At the same time, the high voltage switch 18
The level word line WL is raised to a high voltage VPP.

As a result, the threshold voltage of the selected memory transistor MQ is increased by being connected to the word line WL and the control gate line CGL to which the high voltage VPP is applied, and the selected memory transistor MQ is brought into the erased state (“1” writing). Ru.

Next, the column latch 4 fixes all the control gate lines CGL to the L level, and sets the bit line BL connected to the latch portion storing the H level to the high voltage VPP. At this time, the high voltage switch 18 maintains the high voltage VPP of the word line WL.

As a result, the threshold voltage of the memory transistor MQ connected to the word line WL and bit line BL to which the high voltage VPP is applied is lowered, and the write state (“0”
written).

As described above, the cycle in which the threshold voltage for the selected memory transistor MQ is changed based on the data stored in the column latch 4 is an internal write cycle.

During the internal write cycle in the first cycle write operation, an external control signal instructing the control signal buffer circuit 13 to write is applied, and the row address and column specifying the memory transistor MQ to be written next are applied. By giving addresses to the X decoder 9 and Y decoder 10 via the address buffer 6, and by giving write data from the outside to the input/output buffer 19, the first partial external write cycle in the write operation of the second cycle is performed in parallel. and do it.

During this period, the internal write cycle in the first cycle write operation is being executed, and the timer circuit 1
7, the timer output signal S17 is at L level, and the P channel transistor 45 between the X latches 31 and 32, the P channel transistor 49 in the standby control circuit 30, the P channel transistor 54 in the Y latch 33, and the Since all the P channel transistors 60 are in the off state, the voltage between the X latches 31 and 32, the Y latches 33
The Y gate circuit 5, the input latch 34, and the write driver circuit 7 are electrically disconnected. Therefore, the outputs of the X decoder 9, Y decoder 10, and input buffer 20 do not affect the internal write cycle in the first cycle write operation.

Under this situation, the output of the X decoder 9 is latched in the X latch 31, and at the same time, the output of the
A control signal S30B instructing the write circuit 15 to start is latched in the latch section 37 (active state) inside the write circuit 15. Then, the output of the Y decoder 10 at H level (selected state) is latched in the latch section 38 (active state) of the Y latch 33, and the H level output of the Y decoder 10 is applied to the N channel transistor 57. The output of the input buffer 20 is latched in the latch unit 39 of the input buffer 20 .

Furthermore, when writing multiple bytes of data, new write data is input from the outside to the input/output buffer 19 while keeping the row address fixed and changing only the column address to change the output of the Y decoder 10. As a result, the H level output of the Y decoder 10 is latched to the latch section 38 of the Y latch 33 different from the previous one, and the H level output of the Y decoder 10 is applied to the N channel transistor 57 at the latch section of the input latch 34. 3
9, an input buffer 20 based on new write data
The output of is latched.

By repeating this operation, multiple bytes of data are written, and during this period, multiple bytes of external write data are written to the latch sections 3 of the input latches 34 selected by the output of the Y decoder 10.
It is latched to 9.

When the internal write cycle of the first cycle and the first partial external write cycle of the second cycle are completed, the timer output signal S17 becomes L level for a minute period, and the second partial external write cycle in the write operation of the second cycle is completed. Go to cycle.

In the second partial write cycle, X
P-channel transistor 45 between latches 31 and 32, P-channel transistor 49 in standby control circuit 30
, the P-channel transistor 54 in the Y latch 33 and the P-channel transistor 60 in the input latch 34 are all turned on, so the word line WL2 is set to H level by the latch data of the X latch 31, and the latch data of the Y latch 33 is turned on. Based on this, the Y gate line YL is selectively set to H level, and the Y gate transistor Y uses this as the gate input.
G1 and YG2 are turned on. Then, based on the control signal S30B, which is the latch data of the latch unit 37 of the standby control circuit 30, the write circuit 15 gives a write instruction to the control gate circuit 19, so that the control gate circuit 19 outputs the on-state Y gate transistor YG1 and H that instructs the column latch 4 to write via the control gate line CGL connected to it.
Level write control data is stored. At the same time, an output signal from the write driver circuit 7 based on the latch data stored in the latch section 39 of the input buffer 34 is stored in the column latch 4 via the Y gate transistor YG2 in the on state and the bit line BL connected thereto. .

Then, the delay time TD1 of the delay circuit 51 starts from the time TL when the timer output signal S17 changes to the L level.
After passing, in the standby control circuit 30, NO
The output of inverter 50, which is the other input of R gate 48, becomes H level, and latch section 37 is reset. Similarly, in the Y latch 33, the delay circuit 5
After the delay time TD2 of 6 has elapsed, the output of the inverter 55, which is the other input of the NOR gate 53, becomes H level, and the latch section 38 is reset. Note that the second partial external write cycle is simply an operation of transferring the latch data of each of the latches 31, 33, and 34 and the latch data S30B of the standby control circuit 30 to the column latch 4, and can be performed in a short time. 51 and delay circuit 56
The respective delay times TD1 and TD2 may also be short. .

Thereafter, in order to shift to the internal write cycle of the second cycle write operation, the timer output signal S
17 becomes a high voltage level again, and the internal write cycle in the second cycle write operation is performed in the same manner as the internal write cycle in the first cycle write operation. At this time, the P channel transistor 45 between the X latches 31 and 32, the P channel transistor 49 in the standby control circuit 30, the P channel transistor 54 in the Y latch 33, and the P channel transistor 60 in the input latch 34 are all in the off state. Therefore, even if the next cycle is a write operation or a read operation, the internal write cycle in the write operation of the second cycle is not affected. Further, the H level of the word line WL is maintained by the latch data of the X latch 32.

As described above, in the EEPROM of this embodiment, during the execution of the internal write cycle in the write operation of the I-th cycle (I≧1), the first write cycle, which occupies most of the time of the external write cycle of the (I+1)-th cycle, Since the partial external write cycles of
The first part of the cycle performs an external write cycle,
Since the time required for a write operation can be reduced compared to the conventional method, the write time can be shortened.

Note that during the read operation, since the timer output signal S17 is always at the L level, the X latch 31
, 32, P-channel transistor 49 in the standby control circuit 30, P-channel transistor 54 in the Y latch 33, and input latch 3.
Since the P-channel transistor 60 in 4 is always on and the circuit is equivalent to the circuit shown in FIG. 5, a read operation similar to the conventional one is performed.

In this embodiment, an EEPROM is taken as an example, but the EEPROM is not limited to this. It has memory cells arranged in a matrix, and external data is stored in the first latch designated by the output of the column decoder. For all semiconductor memory devices in which a write operation is performed by an external write cycle for storing data and an internal write cycle for writing data based on data stored in the first latch into a memory cell instructed by the output of a row decoder. On the other hand, this invention is applicable.

[0062]

[Effect of the invention] As explained above, according to this invention,
When writing operations are executed consecutively, the first partial external write cycle in the (I+1)th cycle (I≧1) write operation and the internal write cycle in the I-th cycle write operation are performed without affecting each other. Because they are executed in parallel, in the write operations after the second cycle, the first partial external write cycle in the write operation in the (I+1)th cycle and the internal write cycle in the write operation in the I-th cycle are performed in parallel. The write time can be shortened by shortening the actual execution time of the external write cycle in the write operation of the (I+1)th cycle by minutes.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an EEPROM that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the internal configuration of the X latch shown in FIG. 1;

FIG. 3 is a circuit diagram showing the internal configuration of the standby control circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing the internal configuration of the Y latch and input latch shown in FIG. 1;

FIG. 5 is a block diagram showing the configuration of a conventional EEPROM.

[Explanation of symbols]

1 Memory cell array 4 Column latch 5 Y gate circuit 6 Control gate circuit 7. Light driver circuit 9 X decoder 10 Y decoder 17 Timer circuit 30 Standby control circuit 31 X latch 32 X latch 33 Y latch 34 Input latch

Claims (1)

[Claims] 1. An external write cycle comprising memory cells arranged in a matrix, storing external data in a first latch designated by the output of a column decoder, and memory cells designated by the output of a row decoder. In a semiconductor memory device in which a write operation is performed by an internal write cycle in which data is written based on data stored in the first latch, the external write cycle is performed in a second latch instructed by an output of a column decoder. a first partial external write cycle for storing external data in the second latch, and a second partial external write cycle for transferring data stored in the second latch to the first latch corresponding to the second latch. , when the write operations are executed successively, the first partial external write cycle in the write operation of the (I+1)th cycle (I≧1) and the internal write cycle in the write operation of the I-th cycle influence each other. A semiconductor memory device characterized by being able to execute operations in parallel without affecting the performance.