JPH0431402B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock signal that forms the basis of operation, such as a microprogram control circuit in a microcomputer, and which restarts after stopping the generation of a clock signal. Regarding the signal restart method.

[Conventional technology]

Conventionally, in microprogram control circuits in microcomputers that operate according to microprograms, stopping part or all of the clock signal has rarely been done.
As a result of efforts to reduce power consumption, a method is being used in which the clock signal is stopped after a series of programs are completed. In the conventional method of restarting the clock signal, the clock signal is restarted only at a fixed timing after the clock signal has stopped, and control using a microprogram or masking is not possible. This figure shows the clock signal restart circuit. 1 is an oscillation circuit, 2 is a frequency dividing circuit, 3 and 4 are AND gates, 5 is an OR gate, 6
is a key input control circuit. A clock signal restart signal is output from the OR gate 6 in response to a key input or a periodic signal from the frequency dividing circuit 2. In the conventional method, the signal given from the frequency divider circuit 2 to the AND gate 3 was fixed at 1 second or 1/10 second, and it was impossible to select it. Therefore, in microprogram control circuits that require processing every 1/10 seconds, the clock signal is always activated at a clock timing of 1/10 seconds, and therefore processing is required every 1/10 seconds. Even in the non-program processing mode (Fig. 3), the clock signal is restarted every 1/10 second signal, which is a major obstacle to reducing power consumption.

Needless to say, it would be a bigger disadvantage if the clock signal restart timing was fixed at 1/100 seconds instead of 1/10 seconds. Conversely, if the clock restart timing is fixed at 1 second,
Even if processing every 1/10 seconds or 1/100 seconds is sufficient, 1
It is impossible to stop the clock signal for a second, and the microprogram control circuit continues to operate, resulting in increased power consumption.

Figure 4 shows the power consumption when the clock restart timing is fixed at 1 second and processing is executed every 1/10 second. In Figures 2 to 4, 7 indicates the power effectively consumed by the microprogram control circuit by executing the program, and 8 indicates the power consumed ineffectively by the microprogram control circuit without processing the program. . As described above, the conventional clock signal restart circuit has a fixed clock restart timing, which poses a major problem in terms of reducing power consumption.

[Problem to be solved by the invention]

The present invention improves the conventional fixed clock signal restart timing method as described above, and provides a clock signal restart method that enables the clock signal to be restarted at any timing after the generation of the clock signal is prohibited. The purpose is to provide a method.

[Means to solve the problem]

A clock signal restart method according to the present invention is a clock signal restart method in which a clock signal restart signal is output after a clock signal is stopped to restart the clock signal. After the restart timing signal generation means generates a plurality of restart timing signals based on the signal, the restart timing selection means selects an arbitrary restart timing signal from among the plurality of restart timing signals as a restart timing. The feature is that the selection is made according to a selection instruction.

〔Example〕

The present invention will be explained in detail below based on Examples.

FIG. 5 is an embodiment of a clock signal restart circuit using the clock signal restart method according to the present invention. 1 is an oscillation circuit, 2 is a frequency dividing circuit, 3 and 4 are AND gates, 5 is an OR gate, 6 is a key input control circuit, 9 is a clock signal restart control circuit which is the key point of the present invention, and FIG. A detailed circuit diagram of the clock signal restart control circuit 9 is shown. Frequency divider circuit 2
When a plurality of types of frequency-divided signals 12 from restart timing signal) is output from the mask 10,
The signal is input to a programmable logic array (hereinafter abbreviated as PLA) 11. The PLA 11 (restart timing selection means) selects any signal from among the several types of signals 13 input from the mask 10 according to the microinstruction 14 (restart timing selection command), and sends the selected signal to the AND gate 3. Output.
The signal passing through ANDade 3 and OR gate 5 becomes a clock signal restart signal and restarts the clock signal.

By changing the mask 10 according to the purpose of use, various restart timings can be created according to the purpose. Then, it becomes possible to select one of various restart timings using microinstructions. In other words, it is possible to change the clock signal restart timing as necessary even when the microcomputer is in operation.

FIG. 7 shows a flowchart of an example in which a microcomputer is applied to a clock, taking advantage of the advantage of the present invention that the clock signal restart timing can be arbitrarily set. S-1 is a clock signal restart terminal, and S-2 checks the clock signal restart timing mode. As a result of the check, if the timing processing mode requires restarting every second,
It is processed by S-3 and is a 1 second restart microinstruction.
The clock signal is stopped by executing RST-1 (S-4). After the clock signal stops, it is restarted from S-1 by key input or a 1 second signal.

When performing 2Hz display flashing that requires 1/2 second control, processing is performed in S-5, and the clock signal is stopped by executing RST-2 (S-6), which is a 1/2 second restart microinstruction. Restarting after stopping the clock signal is performed by key input or a 1/2 second signal, similar to the 1 second restart described above.

In the case of 8Hz alarm processing, it is processed in the same way in S-7, and the clock signal is stopped by executing the RST-3 (S-8) command, and then the clock signal is stopped by key input or 1/
Restart with 8 seconds signal.

In this application example, the clock signal stop time is 1
Although an example using three types of seconds, 1/2 seconds, and 1/8 seconds has been shown, it is easy to set other arbitrary times and increase the number of selectable times by changing the mask 10.

[Effects of the Invention] As explained above, according to the clock signal restart method of the present invention, the clock signal restart timing can be arbitrarily set or changed depending on the situation while the microcomputer is operating, so there is no need to operate the clock signal. In some cases, the clock signal can be stopped to significantly reduce power consumption. Therefore, it becomes easy to utilize microcomputers in watches and other fields that require low power consumption.

[Brief explanation of drawings]

Fig. 1 is a diagram of a conventional clock signal restart circuit, and Fig. 2 is a diagram showing power consumption during execution of processing every 1/10 second. FIG. 3 is a diagram showing the power consumption when processing is executed every second in a microprogram control circuit that restarts the clock signal every 1/10 seconds. Fourth
The figure shows the power consumption when processing is executed every 1/10 seconds in a microprogram control circuit that restarts the clock signal every 1 second. FIG. 5 is a clock signal restart circuit diagram using the clock signal restart method according to the present invention. FIG. 6 is a detailed circuit diagram of a clock signal restart control circuit which is a main part of the present invention. FIG. 7 is a flowchart of program processing by a microcomputer using the clock signal restart method according to the present invention. 1... Oscillator circuit, 2... Frequency dividing circuit, 3, 4...
AND gate, 5... OR gate, 6... Key input control circuit, 9... Clock signal restart control circuit, 10... Mask (restart timing generation means), 11... PLA (restart timing selection means), 12... Plural frequency divided signals, 13... Plural restart timing signals, 14... Microinstruction (restart timing selection command).

Claims (1)

[Claims] 1. In a clock signal restart method for restarting the clock signal by outputting a clock signal restart signal after the clock signal is stopped, the clock signal is restarted based on a plurality of divided signals input from a frequency dividing circuit. After the restart timing signal generation means generates a plurality of restart timing signals, the restart timing selection means selects a restart timing signal from among the plurality of restart timing signals with a restart timing selection command. A method for restarting a clock signal, characterized in that the clock signal is restarted by selecting according to the following or by an output of a key input control circuit.