JPH04314116A - Microcomputer - Google Patents

Abstract

PURPOSE:To eliminate the counting time of a counter to be dead time during the operation of an external clock. CONSTITUTION:In the case that a self-exciting oscillator 1 is reset by a reset control means 11, 12, 15, 16 at the time when a reset signal 30 is active, and an external clock signal is inputted through oscillation terminals 17, 18 during this reset period, it is detected by a system clock control means 3, 4, 5, 20, 32, and after the lapse of prescribed time, the former clock signal 28 bypassing the counter 2 is outputted as an internal reset signal 25, and the reset of a system clock generation circuit 7 is canceled, and a system clock signal 31 is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer constructed on a semiconductor substrate, and more particularly to a microcomputer incorporating a self-exciting oscillator and a counter for counting the time until oscillation stabilizes.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing the main parts of an example of a conventional microcomputer.

This conventional example includes a self-excited oscillator 46, a counter 40 for counting the oscillation stabilization time, and a system clock generation circuit 7 for operating the central processing unit. In addition, 8 is a Schmitt trigger buffer, 1
3 is a P-channel MOS transistor, 14 is an N-channel MOS transistor, 17 and 18 are oscillation terminals, 42
is a flip-flop, 44 is a feedback circuit, and 45 is an additional circuit.

FIG. 5 is a timing chart showing the operation of FIG.

In FIG. 4, when the original clock signal 47 to the system clock generation circuit 7 is obtained by self-oscillation, a feedback circuit 44 including an oscillator is connected to the oscillation terminals 17 and 18 of the oscillator 46. In addition, the original clock signal 47 to the system clock generation circuit 7 is converted to an external clock signal 48.
In this case, an additional circuit 45 is provided and connected to the oscillation terminals 17 and 18 so that the input signal to the oscillation terminal 17 of the oscillator 46 has the opposite phase to the input signal to the oscillation terminal 18.

When self-oscillation is performed, the waveform of the original clock signal 47 from the oscillator 46 requires a certain amount of time until the oscillation becomes stable, as shown in FIG. If the original clock signal 47 is used as a clock supply source to the system clock generation circuit 7 during a period when oscillation is unstable, a stable system clock signal 49 cannot be generated, and the microcomputer may malfunction. Therefore, during the period until the oscillation stabilizes, the system clock generation circuit 7 is set to a reset state by the reset signal 50 input from the reset terminal 26, and the system clock signal 49 is not generated.
A counter 40 counts the time until the oscillation becomes sufficiently stable, and an RS type flip-flop 42 is activated by an overflow signal 41 as a first control signal from the counter 40.
The system clock generation circuit 7 is released from being reset by inverting the internal reset signal 43 from the internal reset signal 43 . With the above configuration, the original clock signal 47 whose oscillation has been sufficiently stabilized can be used as a clock supply source to the system clock generation circuit 7, so that a stable system clock signal 49 is provided. The above-described operation is the same even if the external clock signal 48 is used instead of self-oscillation.

[0007]

[Problems to be Solved by the Invention] As mentioned above, in conventional microcomputers, when operating with the external clock signal 48 without self-oscillation, it is necessary to use the original clock signal whose amplitude and signal width are stable from the beginning. 47 is supplied, the counter 40 is originally unnecessary. However, since the microcomputer cannot determine whether to perform self-oscillation or to be supplied with an external clock signal, the central processing unit cannot operate even when the external clock is operating until the overflow signal 41 from the counter 40 is output. figure,
This period had the disadvantage that it was a complete waste of time for the microcomputer.

An object of the present invention is to provide a microcomputer that can operate without wasting time when operating with an external clock by eliminating the above-mentioned drawbacks.

[0009]

[Means for Solving the Problems] The present invention provides an oscillation means for generating an original clock signal, which is the source of a system clock signal, by self-excited oscillation or an external clock signal, and a self-excited oscillation output from the oscillation means. A counter that inputs the original clock signal, counts the time until the original clock signal stabilizes, and outputs a first control signal; and a system clock that inputs the original clock signal and a reset signal and according to the first control signal. a system clock generation means for outputting a signal, a reset control means for controlling the oscillation means to a reset state by the reset signal; and a system clock generation means for controlling the oscillation means to a reset state when the oscillation means is in the reset state The present invention is characterized by comprising system clock control means for detecting input of an external clock signal and outputting a second control signal for controlling generation of the system clock signal in the system clock generation means.

0010

[Operation] When the reset signal is active, the oscillation means is brought into a reset state by the reset control means. and,
If an external clock signal is input during this reset period, the system clock control means detects this and replaces the first control signal from the counter with an original signal generated based on the external clock signal that does not pass through the counter. Control is performed using the clock signal so that an internal reset signal is input to the system clock generation circuit.

[0011] Therefore, when the external clock is operated, there is no need to count by the counter, and it becomes possible to operate the system without wasting time.

0012

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a first embodiment of the present invention. Note that in FIG. 1, the feedback circuit 44 and additional circuit 45 in FIG. 4 are omitted for simplicity.

In the first embodiment, the system clock signal 3
The oscillator 1 serves as an oscillation means for generating the original clock signal 27 of 1 by self-excited oscillation or an external clock signal (not shown), and the original clock signal 27 during self-excited oscillation output from this oscillator 1 is inputted and the original clock signal 27 is generated by self-excited oscillation or an external clock signal (not shown). A counter 2 that counts the time until the signal 27 stabilizes and outputs an overflow signal 21 as a first control signal, and a reset signal 30 from the original clock signal 27 and the reset terminal 26.
The overflow signal 21 and the reset signal 3 serve as a system clock generation means that inputs the input signal and outputs the system clock signal 31 according to the overflow signal 21.
The present invention is characterized in a microcomputer equipped with an RS type flip-flop 6 which inputs 0 and outputs an internal reset signal 25, and a system clock generation circuit 7 which outputs a system clock signal 31 in accordance with the internal reset signal 25. However, the P-channel MOS transistor 11 and the resistor 12 serve as reset control means for controlling the oscillator 1 to the reset state by the reset signal 30.
and a control circuit including inverters 15 and 16;
When the oscillation means 1 is in the reset state, the input of the external clock signal 48 (FIG. 4) to the oscillator 1 via the oscillation terminals 17 and 18 is detected, and the system clock generation circuit 7 generates the system clock signal 31. As a second control signal to control the Schmitt trigger buffer 8
A counter 3, a one-shot pulse generation circuit 4, an RS type flip-flop 5, an AND circuit 32, and a logic gate circuit 20 as a system clock control means that directly outputs the original clock signal 28 without passing through the counter 2. and a control circuit including.

Oscillator 1 includes P-channel MOS transistors 9 and 13 and N-channel MOS transistors 10 and 14, and logic gate circuit 20 includes two AND circuits and one OR circuit.

Next, the operation of the first embodiment will be explained with reference to the timing chart shown in FIG.

The oscillator 1 has a configuration in which the P-channel MOS transistor 9 and the N-channel MOS transistor 10 are turned off while the reset signal 30 is active, so that the oscillator 1 does not oscillate even if a feedback circuit 44 (FIG. 4) including a resonator is connected. It has become. The resistor 12 is a resistor of about 1 [MΩ] and is a P-channel MOS while the reset signal 30 is active.
By turning on the transistor 11, the input of the Schmitt trigger buffer 8 having hysteresis characteristics is fixed at the power supply potential. Further, since the resistor 12 has a high resistance value, it can receive input of the external clock signal 48 (FIG. 4) even while the reset signal 30 is active.

The counter 2 has N frequency dividers 19 connected in N stages.
The counter 3 is an M-bit counter in which M stages of frequency dividers 19 are connected. In this first embodiment, M
=2, the overflow signal 22 becomes active at the fourth input clock to the counter 3.

The one-shot pulse generating circuit 4 detects the edge of the reset signal 30 input to the reset terminal 26 when it changes from a non-active level to an active level, generates a one-shot pulse signal 29, and outputs a one-shot pulse signal 29 to the counter 3 and The flip-flop 5 is reset. The output signal timing of the one-shot pulse generation circuit 4 is shown in FIG. 25 is an internal reset signal of the microcomputer controlled by the flip-flop 6, and the system clock generation circuit 7 is a system for operating the central processing unit using self-excited oscillation or the original clock signal 27 inputted from the outside as a supply source. clock signal 31
generate. During the period when the internal reset signal 25 is active, the system clock signal 31 is not generated and the central processing unit does not operate.

The logic gate circuit 20 is a flip-flop 5
output of flip-flop 5, Q1 (inverted output of Q0) = "1", Q0 = "0"
”, the overflow signal 21 of the counter 2 is selected, and the output of the flip-flop 5 Q1 = “0”, Q0
= "1", the original clock signal 28 bypassing the counter 2 is selected.

When a feedback circuit 44 (FIG. 4) including a vibrator is connected to the oscillation terminals 17 and 18 and an active level reset signal 30 is input to the reset terminal 26, each circuit is initialized as shown in FIG. . Further, as described above, P channel MOS transistor 9 and N channel MOS transistor 9
OS transistor 10 is "off" and reset signal 30
does not oscillate while active. Furthermore, P channel MO
Since the S transistor 11 is turned on, the input of the Schmitt trigger buffer 8 is fixed at the power supply potential. When the reset is released, P channel MOS transistor 9 and N channel MOS transistor 10 are turned on, and P
Channel MOS transistor 11 is turned off and starts oscillating. Since the logic gate 20 selects the overflow signal 21 of the counter 2, after the counter 2 counts a sufficient oscillation stabilization time, the flip-flop 6 is reset and the internal reset signal 25 is released. As a result, the system clock signal 31 is generated by the system clock generation circuit 7, and the operation of the central processing unit is started.

On the other hand, when an external clock signal is supplied to the oscillation terminals 17 and 18, the clock input can be accepted even when the reset signal 30 is active. If a certain number of clocks are input while the reset signal 30 is active, the counter 3 activates the overflow signal 22 and sets the flip-flop 5. In the first embodiment, the flip-flop 5 is set if four or more clocks are input while the reset signal 30 is active. This allows logic gate 2
0 selects the original clock signal 28 that bypasses the counter 2, resets the flip-flop 6 immediately after releasing the external reset signal 30, and resets the internal reset signal 2.
5 is released, the central processing unit starts operating.

As explained above, in the first embodiment, when operating a microcomputer by self-excited oscillation, the operation is started after waiting for the oscillation to become sufficiently stable as in the conventional case, and the operation is started after the external clock signal is input. When operating the microcomputer, the internal reset signal 25 can be canceled immediately after the external reset signal is canceled, and the central processing unit can be operated.

FIG. 3 is a block diagram showing a second embodiment of the present invention. In the second embodiment, the oscillator 1, inverter 15, P channel MOS transistor 11, and resistor 12 in the first embodiment of FIG. 1 are omitted for simplicity.

In the second embodiment, the counter 2 in FIG.
A counter 30 is provided in place of 3 and 3, and the counter 30 also serves as a two-stage frequency divider, the first stage and the next stage, as the counter 3 in FIG. This results in
The number of stages of the counter 30 is the same as that of the conventional microcomputer, and there is an advantage that the present invention can be implemented without requiring significant circuit changes compared to conventional microcomputers.

[0026]

As explained above, the present invention has a means for determining whether a clock signal is supplied to a microcomputer by self-oscillation or by external clock signal input while a reset signal is active. By bypassing the counter that counts the oscillation stabilization time when an external clock signal is input, it is possible to significantly shorten the time required to start up the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing main parts of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation.

FIG. 3 is a block configuration diagram showing main parts of a second embodiment of the present invention.

FIG. 4 is a block configuration diagram showing the main parts of a conventional example.

FIG. 5 is a timing chart showing the operation.

[Explanation of symbols]

1, 46 Oscillator 2, 3, 30, 40 Counter 4 One-shot pulse generation circuit 5, 6, 42
Flip-flop 7 System clock generation circuit 8 Schmitt trigger buffers 9, 11, 13 P-channel MOS transistors 10, 14 N-channel MOS transistor 12
Resistors 15, 16 Inverters 17, 18 Oscillation terminal 19 Frequency divider 20 Logic gate circuits 21, 22, 41 Overflow signals 23, 2
4 Control signals 25, 43 Internal reset signal 26 Reset terminals 27, 28, 47 Original clock signal 29
One shot pulse signal 30, 50 Reset signal 31, 49 System clock signal 32
AND circuit 44 Feedback circuit 45 Additional circuit 48 External clock signal

Claims (1)

[Claims] 1. Oscillator means for generating an original clock signal, which is the source of a system clock signal, by self-excited oscillation or an external clock signal, and an input device for inputting the original clock signal during self-excited oscillation output from the oscillating means. a counter that counts the time until the original clock signal becomes stable and outputs a first control signal; and a system clock generation means that receives the original clock signal and the reset signal and outputs a system clock signal according to the first control signal. a microcomputer comprising: reset control means for controlling the oscillation means to a reset state by the reset signal; and detecting input of the external clock signal to the oscillation means when the oscillation means is in the reset state; ,
A microcomputer comprising system clock control means for outputting a second control signal for controlling generation of a system clock signal in the system clock generation means.