JPH04314131A - Central processing unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a central processing unit, and more particularly, to a central processing unit that processes immediate data.
The present invention relates to a central processing unit in which a) can be placed in a program memory.

0002

BACKGROUND OF THE INVENTION An instruction can generally specify zero to three operands and zero to one next instruction. When executing an instruction, the CPU needs to determine the location of the operand and the next instruction, that is, the address, according to these specifications. In addition, if the operand part of an instruction is the operand itself, this is immediate value data (hereinafter referred to as immediate value).
and is used as a constant operand. A conventional CPU consists of an instruction operand and a small amount of numerical data (operand) to specify the memory, and a large amount of data is stored in an external ROM in an addressing circuit separate from the addressing space of the CPU's program memory. Powered by. The CPU individually controls external addressing circuits using instructions, and data from the external ROM is stored in the arithmetic RAM through a predetermined bus.

[0003] Assuming that the program memory is a fixed-length, fixed-cycle instruction that outputs an opcode, operand 1, and operand 2 digital code to one address, if an immediate value is used only once during an operation, it must be included in the above instruction. be able to. For example, <mov R0 50
H> (Storing the immediate value 50H in a part of RAM called R0) When an instruction is output from the program memory, the operation code of the instruction is decoded through the operation decoder, and the operation decoder outputs a signal for mov (move) control. As well as being output, operand 1
specifies the storage address of RAM through the RAM address control circuit, and operand 2 directly inputs the immediate value of predetermined bits (for example, 8 bits) to the data input of the calculation RAM through the bus, selector, and ALU.
An immediate value of 50H is input into a predetermined area R0 of M. In this example, since it exists in the instruction, only the immediate value for control is used. Generally, data memory (frequency tables, accompaniment data, etc. when used in electronic musical instruments, etc.) is a large amount, so as mentioned above, it cannot be stored as immediate data in the program memory; ) to retrieve data from this data memory.

0004

[Problem to be Solved by the Invention] However, such conventional central processing units have a configuration in which data is fetched from an external data memory, so a dedicated data memory and its addressing circuit are required. Not only that, but it takes a very long time to store the data in the calculation RAM, so there is a problem that high-speed processing cannot be performed. That is, the data memory is given an address by storing address data from the calculation RAM in an output latch in response to an instruction from the program memory, and only then is data read from the data memory. The calculated data is stored in the calculation RAM through a predetermined selector and ALU. All conventional custom CPUs for electronic musical instruments use this method to access data memory by setting 16 to 22 bits of address on the board. For this reason,
Conventionally, (I) a data memory and its addressing circuit are required separately, (II) immediate values cannot be obtained quickly and the processing time is too long, and (III) large-scale data processing becomes difficult; Necessary CP for electronic musical instruments
It is becoming a bottleneck for speed as U, (IV
) There is a tendency for large amounts of data to be processed as the memory unit decreases, and the above-mentioned problems are becoming more widespread. Therefore, the present invention makes it possible to arrange a data memory area in the program memory area, thereby eliminating the need for a dedicated data memory and its addressing circuit, and
It is an object of the present invention to provide a central processing unit that can significantly improve processing speed.

[0005]

[Means for solving the problem] The invention according to claim 1 includes:
A program storage means for storing a predetermined program, an addressing means for addressing the program storage means, an operation data storage means capable of writing and reading operation data, and an operation code included in an instruction output from the program storage means. an instruction decoding means for decoding, an arithmetic data addressing means for addressing the arithmetic data storage means using an operand included in an instruction output from the program storage means, and an arithmetic data storage means according to the decoding result of the instruction decoding means. in the central processing unit, the addressing means specifies an address to be branched on the premise of return to a part of the program storage means based on the immediate value data of the operand. a changing means; an address storage means for temporarily storing an address after the return; and an address storage means for reading out the address of an instruction following the branch instruction from the address storage means as a post-return address by a first return instruction after the branch, and storing the address in the program storage means. a control means for setting the address; and a data storage means for storing the read data by providing a second return instruction for reading and storing the operands included in the instruction after the return.
Equipped with: The invention according to claim 2 provides an addressing means for addressing the program storage means, an arithmetic data storage means capable of writing and reading arithmetic data, and an instruction for decoding an operation code included in an instruction output from the program storage means. decoding means; arithmetic data addressing means for addressing the arithmetic data storage means using operands included in instructions output from the program storage means; a first subroutine branch instruction for branching on the premise of return; a second subroutine branch instruction for causing the branch decoding means to output a predetermined control signal; a delay means for delaying the control signal and outputting a delayed control signal; and a storage means for reading and storing immediate value data output from the program storage means after branching based on the delay control signal output from the delay means. After reading, the program returns to process the instruction immediately after the branch.

[0006]

According to the first aspect of the invention, a part of the program storage means is provided with a data memory area in addition to the program area. Based on the immediate value data of the operand of the program storage means, the address changing means specifies an address to be branched on the premise of return to a part of the program storage means, and the address after return is temporarily stored in the address storage means. After the branch, a first return instruction reads the post-return address from the address storage means to the instruction next to the branch instruction and returns again, and a second return that reads and stores the operands included in the instruction after the return. The read data is stored according to the command. Therefore, it is possible to provide a data area in a part of the program storage means, eliminating the need for a dedicated data memory and its addressing circuit, and also
Compared to M access, there is no need to process address latch data, and an immediate value can be obtained very quickly. In the invention according to claim 2, the first branch is performed on the premise of return.
A subroutine branch instruction is provided, and a second subroutine branch instruction that causes the branch decoding means to output a predetermined control signal is provided separately from the first subroutine branch instruction. The control signal is delayed by the delay means, and the immediate data output from the program storage means after the branch is read by the delayed control signal output from the delay means, and then the program returns to process the instruction immediately after the branch. Therefore, it is possible to forcefully and automatically return to the program execution address without providing a return instruction, and it is possible to use the data area 100% effectively.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. Explanation of Principle First, the basic principle of the present invention will be explained. 1 and 2 are diagrams showing the flow of a program memory. FIG. 1 shows a conventional subroutine call, and FIG. 2 shows a subroutine call of a central processing unit according to the present invention. Here, the program shown in Figure 1 uses a program that performs the same processing that is used multiple times as a subprogram, and when called from the main routine by a subroutine call, moves the program address to the subprogram and processes the subprogram (here, mov processing ). When the processing is completed, the program address is returned and the main routine is returned to, thereby making it possible to use the program multiple times. In this case, the subroutine returns to the main routine by a RET (return) command.

On the other hand, as shown in FIG. 2, a data memory area is provided in a part of the same address space as the program area, and the RET' instruction (as described above) is written as an operation code corresponding to the address D0 of this data memory area. The RET command performs different operations), and data 0 and data 1 are placed in operand 1 and operand 2. The above RET' command is used in addition to the conventional RET processing when returning from a subroutine to the main routine.
Before processing (that is, while the RET instruction is being processed by the instruction decoder), data 0 and data 1 stored in operand 1 and operand 2 are stored in a predetermined latch LM (described later).
This is an instruction that performs an operation to transfer data to. In other words, a data memory area is provided below the program area, and conventional RET
The data to be used in the operation RAM is set in the operand 1 and operand 2 parts that were not used in the instruction.

In the above configuration, the operation of reading a portion of data from the data memory during processing in the main routine is as follows. First, as shown in Figure 2, <cal
l Execute the D0> (subroutine call to address D0 in the main routine) instruction. Then, processing similar to a conventional subroutine call is performed in the addressing circuit section (described later), and the program address is moved to address D0 of the program memory. This makes <RET' d0 d dependent on address D0
The opcode 1>, operand 1, and operand 2 are output from the program memory. Then, the data d1 and d2 of operand 1 and operand 2 are latched into the latch LM (described later), and the operation code is decoded by the instruction decoder as a RET command, and the same return process as before is performed. instructions are executed. For example, this <call
D0> command is followed by <movR0 LM> (latch LM)
By programming an instruction (to store the contents of the data at address R0 in the memory), it becomes possible to read the immediate value of the data memory area in the program area into the memory. Similarly, when the <call D1> (subroutine call to address D1) instruction is executed, the program address is <RET' which exists at address D1.
The operation code d2 d3>, operand 1, and operand 2 are output. In this way, it has become possible to have a data memory area in a part of the program memory, which not only eliminates the need for a dedicated data memory and its addressing circuit, but also allows the data to be stored directly in the program memory, which is different from the conventional method. This eliminates the process of reading data from an external data memory, dramatically improving processing speed.

First Embodiment Hereinafter, embodiments will be explained based on the above basic principle. Figure 3
- FIG. 6 is a diagram showing a first embodiment of a central processing unit according to the present invention, and is an example applied to a central processing unit that executes fixed-length fixed-cycle instructions.

First, the configuration will be explained. FIG. 3 is an overall configuration diagram of the central processing unit. In FIG. 3, 11 is a central processing unit (CPU) capable of executing fixed-length cycle instructions.
), 12 is an external data memory that supplies data to the CPU 11, and the CPU 11 uses basic clocks CK1, CK
Clock signals P1, P2, P3, P4, P5, P6 that control each part based on 2 and control signals OP1, OP2, M
(see FIG. 5); a program memory 22 that stores a program based on a fixed-length fixed-cycle instruction in which an opcode, operand 1, and operand 2 are present at one address; and instructions output from the program memory 22. An operation (instruction) to decode the operation code A1 included in the code and output control signals OP1, OP2, M, C1, C3 (see Figure 5) to each part.
A decoder 23, an arithmetic RAM 24 capable of writing and reading data for an arithmetic operation, and an arithmetic RAM address control circuit 25 that addresses the arithmetic RAM 24 using an operand A2 included in an instruction output from the program memory 22; An arithmetic circuit 26 executes an operation on the arithmetic RAM 24 according to the decoding result of the operation decoder 23, an addressing circuit 27 addresses the program memory 22, and temporarily stores data included as operand 1 and operand 2 in a return instruction from a branch. latches (LM0) 28, (LM1) that hold
29 and a latch (L3) 30 that latches the address data output to the data memory 12, and each of these parts is connected to a bus 3 having gate circuits 31 to 35.
6.

The arithmetic circuit 26 has latches (L1) 41, (2) that latch the arithmetic data read out from the arithmetic RAM 24.
L2) 42, data input through the output of latch (L2) 42 and bus 36 (e.g., latches LM0, LM
a selector (S1) 43 that selects the data to be returned to the return command stored in the data memory 12 and the data read from the data memory 12 according to the control signal C3; and a latch (L1) 4.
1 and the output selected by the selector (S1) 43, an ALU (arithmet
ic logical unit) 44.

The addressing circuit 27 also includes a program counter (PC) 51 that holds the address of the memory containing the next instruction to be read and increments it by +1 as the instruction is executed, and a stack counter 52 that stores a branch instruction by increasing or decreasing the address of the stack counter 52. The stack memory (ST) 53 stores the address of the next instruction (address after return), the address stored in the program counter (PC) 51, the address stored in the stack memory 53, and the address from the program memory 22. A selector (S2) 54 that selects one of the operand 1 and 2 addresses according to control signals OP1 and OP2, and an address latch that latches the selected address at the timing of the clock signal P1 and outputs it to the program memory 22. (AL)5
It consists of 5.

Next, the operation of this embodiment will be explained. Example of arithmetic instruction To explain the specific operations of each part of the central processing unit 11 shown in FIG. 3, first, with reference to the timing chart of FIG.
The operation in rd1 05H> will be described. When this instruction is executed, the program memory 22 outputs a 22-bit code, bits 0-7/bits 8-15/bit
Operand 2/operand 1/t16 to t21 respectively
It's called an opcode. For example, as shown in Figure 4, in the above instruction, the opcode/operand 1/operand 2 is
0105'' digital code, <operation code> 06H (H is HEX expression, the same applies hereinafter) is input to the operation decoder 23, and its output control line is (1) input/output operation of the ALU 44 as C= A+B
A control code such as is given to the ALU 44. (2) Turn on C1 that connects the output of operand 2 to the 8-bit bus line. (3) Connect the selector (S1) 43 input of the B input of the ALU 44 to the bus 36. (4) Perform read/write control of the calculation RAM 24 (described later). <Operand 1> is given 01H directly to the arithmetic RAM 24 through the RAM address control circuit 25. <Operand 2> is connected to ALU4 through C1 to bus 36.
4 is given. The CPU 11 executes the above operations in three timings in one cycle. At this timing, the L1 control uses the output of the operation decoder 23 to control the operation RAM 2.
This is a control signal for the latch (L1) 41 that latches the output data of 4. Similarly, the RAM write signal is an output of the operation decoder 23 and is a pulse for writing into the calculation RAM 24, and when this signal is LOW, the data at the address given to the RAM 24 continues to be output.

As described above, the contents of the cell (3H in this case) selected by the address given to the RAM 24 at T1 are latched into L1 at the center of T1. At T2, the data given to the two inputs of the ALU at T1 are added. Then, at T3, the contents are written to rd1 again. Therefore,
rd1←rd1+05H, 3+5=8 is stored in rd, and the calculation ends. Similarly, ADD rd1
In the case of rd2, T1 sends r to L2 at the timing of T2.
Latch the contents of d2 and set the selector (S1) 43 to the ALU
By setting B input to L2 output, rd2←rd1
+dr2 operation is executed.

Operation of each part of the CPU 11 Next, the operation of each part of the CPU 11 will be explained with reference to the timing charts of FIGS. 5 and 6. The CPU 11 is
As shown in Figure 5, 1 in 3 cycles of basic clock CK2.
Instructions are executed (exceptions include one instruction in six cycles). First, when a predetermined address is specified by the addressing circuit 27, 22-bit fixed length data is output from the program memory 22. Specifically, the upper 6 bits are sent to the operation decoder 23 as an operation code (A1), and the next 8 bits are sent to the operation decoder 23 as the operand 1 ( A2),
The lower 8 bits serve as operand 3 (A3) and are sent to the RAM address control circuit 25 and selector (S2) through the bus 36.
) 54 respectively. The operation decoder 23 decodes the operation code included in the instruction output from the program memory 22, and supplies control signals OP1, OP2, M, C1, and C3 to each circuit based on the decoding result. The arithmetic circuit 26 executes an arithmetic operation on the arithmetic RAM 24 according to the decoding result of the operation decoder 23,
The calculation result is output to the calculation RAM 24. In such a case, by addressing <CallADu
When the ADo> instruction is executed, the program memory 22
Based on this instruction, Call, ADu, and ADo are output as operation code A1 and operands A2 and A3. Here, Call is an instruction command, and ADu and ADo are data specifying an address. The operation code A1 is analyzed by the operation decoder 23, and as a result, the operation decoder 23 outputs C
Command OP1 indicating an all statement is output to selector (S2) 54. The selector (S2) 54 has a program counter (PC) 51 output, a stack memory 53 output STR,
Operand 1 and operand 2 are input, and when command OP1 is input to selector (S2) 54, operand A2, which is the address of the JUMP destination by the Call instruction, is input.
Select A3. Here, O for one instruction (3 cycles)
Since P1 is being output, data D0 of operands 1 and 2 is selected during that time as shown in S2 of FIG.

The output of the selector (S2) 54 is input to the address latch (AL) 55, and the address latch (AL)
55 is output data D of the selector (S2) 54 that is output in response to the clock signal P1 that is output in response to the first cycle of the basic clock CK1, as shown in FIG.
Latch 0. Note that OP1 is set in the selector (S2) 54.
When is not input, the address output PC of the program counter (PC) 51, which is incremented by +1, is latched in the address latch (AL).

At the same time as the above-mentioned latching of operand 1 and 2 data D0 is carried out, stack processing for a subroutine call is executed. In other words, the program counter (P
C) 51 return destination address data is stack counter 5
Stack memory (ST
) 53, thereby starting the processing of the subprogram. Then, at the end of the subprogram, RET(
When the return) instruction is executed, the return destination address of the main routine stored in the stack memory 53 is changed to the selector (
S2) 54 is selected, and processing is executed from the command following the call command.

This process will be explained in detail. As shown in FIG. 3, the stack memory (ST) 53 receives the clock signal P2 shown in FIG. Evacuate. The state at this time is shown in STK in Figure 5, where the program counter (PC
)51 (PC+1) is stored in the stack memory 53 in synchronization with P2. Program counter (PC) 5
A clock signal P3 is inputted to 1, which is incremented by 1 by this P3 input, and D0+1 is output. Then, the value D0 of the address latch (AL) 55 is output to the program memory 22, and the read D0 reads data 0 and data 1 using D0 as an address as shown in FIG. That is, when address D0 is specified on the program memory 22 shown in FIG. 2, data 0 is specified in the next cycle.
, data 1 will be output. At this time, the RET command is also output from the program memory 22 to the operation decoder 23 as part of the command, so the operation decoder 23 decodes this and sends the command OP2 to the selector (S
2) Output to 54. When OP2 is input, (PC+1) that was in the program counter (PC) 51 is selected from the selector (S2) 54 and the address latch (A
L) 55. In this state, the address latch (A
L) When the clock signal P1 that rises in synchronization with the first cycle of the basic clock CK1 is input to 55, the signal shown in FIG.
As shown by L, address data (PC+1) is latched in the address latch (AL) 55. Furthermore, the program counter (PC) 51 becomes (PC+2) due to the input of the clock signal P3.

On the other hand, as shown in FIG. 3, the bus 36 is provided with latches (LM0) 28 and (LM1) 29 for supplying the address to the arithmetic circuit 26 as data output. That is, operand 1 is retrieved from program memory 22.
, Operand 2 is data specifying an address, and since this cannot be directly supplied to the arithmetic circuit 26, the latches (LM0) 28 and (LM1
) 29 is provided to temporarily save address data. Latch (LM0) 28, (LM1) 29
At RET (when OP2 is output), a clock signal P rises in synchronization with one cycle of the basic clock CK1.
4 is input, and by inputting this P4, data D0 and D1 are respectively latched as shown in FIG. 5LM0 and LM1.

The data latched in the latches (LM0) 28 and (LM1) 29 are transferred to the arithmetic circuit 26 in the following manner. That is, as shown in FIGS. 5A1, A2, and A3, an instruction is issued to move the latched data D0 and D1 by <mov>, and then the latched data D0 and D1 are moved by <RD0>.
Gate (C2-1) 3 between LM0) 28 and bus 36
2 and open the gate (C2-2) 33 by <LM0>.
open. At the same time, the gate (C1) 31 for preventing data collision on the bus 36 is closed. At this time, (PC+2) is latched in the address latch (AL) 55 by the clock signal P1, and this data (
PC+2) is data for reading the next RD1 and LM1, and the address latch (AL) 55 is preparing the data to be read next.

In order to read the data latched by the latches (LM0) 28 and (LM1) 29 into the arithmetic circuit 26, it is first necessary to control the control signal C3 input to the selector (S1) 43 of the arithmetic circuit 26. be. Specifically, Figure 5
As shown in C1 and C3, by lowering the control signal C1 input to the gate (C1) 31 and raising the control signal C3, the latches (LM0) 28, (LM1)
29 is selected by a selector (S1) 43. Also, the instruction using operand A1 is <mo
v>, when the control signal M is input, the ALU 44 selects the selector (S1
) 43 (ignoring the data input to the input terminal A) and outputting it to the calculation RAM 24. The flow of data at this time is shown in FIG. 5L1, and passing the data corresponds to outputting "0" from the latch (L1) 41. In addition, the selector (S1) 43
The data output from the ALU 44 is shown in FIG. 5S1.

FIG. 6 is a diagram showing the timing in the ALU 44. As shown in this figure, the ALU 44 has data D
1, D1 is output to the calculation RAM 24 as is. Then, as shown in FIG. 6P6, the calculation RAM 2
4, address D0 is sent to RD0 specified by operand 1 at timing P6. The data extraction operation from the latch (LM0) 28 and latch (LM1) 29 described above is actually performed by 8-bit processing, so the same processing is performed twice for LM0 and LM1.

FIG. 6RD1 shows an RA for calculation by similar processing.
This shows that D1 has been read into RD1 of M24.

The operations of each part of the CPU 11 have been explained above according to the timing charts of FIGS. 5 and 6.
The characteristics of the operation of the entire 11 are as follows. When the mnemonic instruction <Call D0> is executed, a digital code “823451”H, for example, is output from the program memory 22. At this time,
The operation code 82 is input to the operation (instruction) decoder 23, and its output is output to each section to perform the following operations. (1) Operands 1 and 2 are latched by the address latch (AL) 55 through the selector (S2) 54 and used as the address for the next cycle. (2) The next address of CALL SUB1, that is, the current value of the program counter (PC) 51, is input to the stack memory (TS) 53, and the stack counter 52 is incremented by 1.

As a result, D0 (=3456H) is applied to the address latch (AL) 55, and the instruction at address 3456 is executed in the next cycle. At this address 3456, as shown in Figure 2, <Ret' data0, data1>
For example, data "83789AH" is output from the program memory 22. At this time, opcode 83 is given to the instruction decoder, and in addition to the conventional Ret (return) operation, operand 1,
2, 16 bit data of 789AH
The latch LM (LM0 and LM1 are names in 8-bit units) is caused to perform a storing operation. Further, in the conventional Ret operation, after decrementing the stack counter 51 by 1, the stacked RET address is passed through the selector (S2) 54 and latched into the address latch (AL) 55. As a result of the above, after returning, 16-bit data will be stored in the LM. And <mov rd0 LM0><m
By executing ov rd1 LM1>,
789AH will be stored in rd0,1 of AM24.

As explained above, according to the present embodiment, a data memory is provided in the program area so that the address can be changed to output data, and then the program execution address can be returned again. That is, since the data area is temporarily accessed using a subroutine call and RET, and the operand data is read using the RET statement at that time, it is possible to provide a data area in a part of the program memory 22, and a dedicated Data memory and its addressing circuit can be made unnecessary. Furthermore, the number of circuits required to achieve the above-mentioned functions is extremely small, and it can be applied to conventional custom CPUs very easily.

Furthermore, since there is no need to take in data from the external data memory 12, it is possible to obtain an immediate value very quickly, especially compared to the conventional separate data ROM access, since there is no need to process address latch data. This makes it possible to dramatically improve processing speed. Furthermore, since data is directly stored in the general-purpose RAM, there is no need for transfer commands from the LM and transfer time, further improving program memory savings and high-speed processing.

In this embodiment, when the RET' command is executed, immediate value data is stored in the latch LM, but at the time of the RET' command, the RAM address control circuit 25 is controlled to control the input/output of the bus, etc. It is also possible to directly store immediate value data in a specific RAM area. In this way, versatility can be further improved.

Furthermore, in this embodiment, the CPU 11 has fixed-length fixed instructions, but any CPU that can store data in the program memory may be used, and the instruction length does not have to be fixed and the instruction execution Needless to say, the cycle is also arbitrary.

Second Embodiment By the way, in the CPU 11 of the first embodiment, CALL/
Even though the program memory length is 22 bits because RET is used as is, the upper 6 bits must be the opcode of the RET instruction, and it is possible to further improve memory efficiency in this respect. This will be explained as an example. Note that, in reality, the upper 6 bits used as the operation code are 6 bits and difficult to use, so the CPU 11 of the first embodiment is also very effective.

FIGS. 7 to 12 are diagrams showing a second embodiment of the central processing unit according to the present invention, and like the first embodiment,
This is an example applied to a central processing unit that executes fixed-length fixed-cycle instructions. In describing this embodiment, the same numbers and symbols are given to the same components as in the first embodiment, and the explanation of the overlapping parts will be omitted.

First, the configuration will be explained. FIG. 7 is an overall configuration diagram of the central processing unit. In Figure 7, 100 is 2
The CPU 100 is a central processing unit (CPU) capable of executing 4-bit fixed length cycle instructions, and the CPU 100 uses clock signals P1, P2, P3, P
4, P5, and P6 (see FIGS. 10 and 11); and a program memory 22 that stores a program based on a fixed-length fixed-cycle instruction in which an opcode, operand 1, and operand 2 are present at one address.
Then, the operation code A1 included in the instruction output from the program memory 22 is decoded and control signals M, C1,
An operation (instruction) decoder 102 that outputs C3 (see FIGS. 10 and 11), and controls subroutine branching and return of the entire CPU 100 based on the output from the operation decoder 102 and a branch instruction signal CALL1 applied from the outside. Command signal CA to perform
A branch delay circuit 103 that outputs LL and RET (see FIG. 8), an arithmetic RAM 24 capable of writing and reading data for an arithmetic operation, and an operand A2 included in an instruction output from the program memory 22 are used to perform an arithmetic operation. RAM24
Arithmetic RAM address control circuit 2 for addressing
5, and an arithmetic circuit 2 that executes an arithmetic operation on the arithmetic RAM 24 according to the decoding result of the operation decoder 102.
6, an addressing circuit 27 that addresses the program memory 22, and latches (LM0) 104, (LM1) 105, that temporarily hold data when branching.
(LM2) 106 and a latch (L3) 30 that latches the address data output to the data memory 12, and each of these parts consists of gate circuits 31, 34,
35, 107-109 by a bus 110.

[0034] The above latches (LM0) 104, (LM1)
105 and (LM2) 106 are the names of 8-bit units of latch LM, and LM latches 3 bytes (24 bits) of data from data 0 to data 2 in the instruction cycle when a branch occurs (see FIG. 11).

FIG. 8 is a circuit diagram of the branch delay circuit 103. In this figure, a branch delay circuit 103 includes an OR gate 111 that logically ORs a conventional normal subroutine branch command signal CALL1 and a subroutine branch command signal CALL2 unique to this embodiment, and a CALL2 signal as shown in FIG.
A delay latch 112 that latches in synchronization with clocks CK1 and CK2 and outputs it as a delayed signal DCALL2 as shown in FIG. gate 113.

In the above configuration, when a subroutine branch instruction called CALL2 unique to this embodiment is executed, the program branches to the address labeled D0 as shown in FIG. When branching, 3b of DATA0 to DATA2 in that instruction cycle
yte data is stored in a latch called LM (LM0, LM1, L
M2). Then, in this cycle, the RET command is automatically executed. In the next cycle, a return process is performed to the next address of CALL2, and control is transferred to the program area controlled by the program. At this time, for example, <mov R012 LM> (the contents of LM are transferred to the memory Ro
12), it becomes possible to read the immediate value of the data memory area.

The actual circuit operation will be explained below with reference to the timing charts of FIGS. 10 to 12.

FIGS. 10 and 11 are timing charts of each part of the CPU 100, and correspond to FIG. 5 of the first embodiment. The differences from FIG. 5 are as follows. That is, in FIG. 5, operation code A1 indicates that the instruction following the CALL instruction is a RET instruction, and operands 1 and 2 are
are the data D0 and D1, but in this embodiment, the data also enters the operation code A1, so the operation code, operand 1, and operand 2 in the data memory area are
DATA1 to DATA3 are entered in this order. Note that the above DATA1 to DATA3 indicate the order of data (first to third), and in FIG. 9, the above DATA1 to DATA
TA3 is D0-D2, D3-D5 or Dn-Dn+
Corresponds to 2. Further, a clock signal P6 is inputted to the calculation RAM 26 as a timing for reading the above-mentioned DATA1 to DATA3. In addition, in this embodiment, OP of FIG.
1, CAL by branch delay circuit 103 instead of OP2
L and RET are used, and in addition to this, DCALL shown in FIG. 10 is output.

The operation decoder 102 inputs into the branch delay circuit 103 a conventional subroutine branch command signal CALL1, a CALL2 unique to this embodiment, and a subroutine return command signal RET. A CALL signal and a RET signal for controlling subroutine branching and return of each part of the entire CPU are output from the terminal.

[CALL D0] Currently being programmed
When the instruction is output from the program memory 22, the instruction is decoded by the operation decoder 102 and the CALL2 terminal of the branch delay circuit 103 is given an “H” level. Then, the "H" level is output from the CALLOUT terminal, the conventional CALL command processing is performed, and the program memory address is <label D0 address>.
Move to. Further, "H" of CALL2 is input to the internal delay latch.

In the next cycle, the program memory 22 will be at the label address D0, so as shown in FIG.
A3 is output. At this time, as shown in FIG.
Since the ALL2 signal becomes “H”, DATA1~DAT
A3 is controlled to be connected to the input of latch LM,
Stored in LM. In addition, the DCALL2 signal is
Since it is ORed with the RET OUT signal, which has the same meaning as the ET command signal, the entire CPU 100 can be controlled to return to the next command cycle.

In the next cycle, a return is made and the instruction immediately following the subroutine branch instruction is executed. By the above-described operation, the immediate data in the data area is stored in the latch LM. In this way, in the first embodiment, data could not be stored in the area used as the opcode, and 8-bit data was provided for operands 1 and 2, but in this embodiment, the area used for storing the opcode is It also allows data to be stored. In order to realize this, the CPU 100 of this embodiment is provided with a branch delay circuit 103, and outputs a DCALL2 instruction that is slightly different from the normal CALL instruction (normal CALL
(Also outputs the L instruction) RET should be omitted. That is, when the command CALL2 is input, the branch delay circuit 103 outputs DCALL2 and a RET command signal to force a return. In addition, in conjunction with this, three latches (LM0
) 104, (LM1) 105, and (LM2) 106 are provided.

As described above, in this embodiment, the subroutine is branched from the program area to the data area, and the program can be executed no matter what value the entire bit field of the data area has (although in the first embodiment there was a restriction that the opcode was RET). Since it is possible to automatically return to the address, in addition to the effects of the first embodiment, it is possible to use the data area 100% effectively.

In each of the above embodiments, the fixed cycle instructions are applied to a CPU with three cycle instructions, but it goes without saying that other cycle instructions may be used. In addition, the above C
It goes without saying that the number and types of components constituting the PU 11, CPU 100, branch delay circuit 103, etc. are not limited to those in the above-described embodiments, and for example, the number of registers or the like may be increased.

[0045]

According to the present invention as claimed in claim 1, since the address is changed from the program area to the data area, data is output at that time, and the program execution address can be returned again after that, the program memory can be changed. It is possible to provide a data area in a part, eliminating the need for a dedicated data memory and its addressing circuit, and compared to the conventional method of accessing a separate data ROM, there is no need to process latch data for addresses, making it very easy to use. Get instant value quickly. According to the invention of claim 2, in addition to the effect of the invention of claim 1, since the RET command is no longer required, data can be stored in the data area that was used as an operation code, further improving memory efficiency. can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the flow of a program memory of a central processing unit.

FIG. 2 is a diagram showing the flow of a program memory of a central processing unit.

FIG. 3 is an overall configuration diagram of a central processing unit.

FIG. 4 is a timing chart for explaining an example of an 8-bit operation instruction of the central processing unit.

FIG. 5 is a timing chart of the central processing unit.

FIG. 6 is a timing chart of the arithmetic circuit of the central processing unit.

FIG. 7 is an overall configuration diagram of a central processing unit.

FIG. 8 is a circuit diagram of a branch delay circuit of the central processing unit.

FIG. 9 is a diagram showing the flow of a program memory of the central processing unit.

FIG. 10 is a timing chart of the central processing unit.

FIG. 11 is a timing chart of the central processing unit.

FIG. 12 is a timing chart of a branch delay circuit of the central processing unit.

[Explanation of symbols]

11 CPU 12 Data memory 21 Clock circuit 22 Program memory 23 Operation decoder 24 Arithmetic RAM 25 Arithmetic RAM address control circuit 26 Arithmetic circuit 27 Addressing circuit 28 Latch (LM0) 29 Latch (LM1) 30 Latch (L1) 31 to 35 Gate Circuit 41 Latch (L1) 42 Latch (L2) 43 Selector (S1) 44 ALU 51 Program counter 52 Stack counter 53 Stack memory 54 Selector (S2) 55 Address latch (AL) 103 Branch delay circuit 104 Latch (LM0) 105 Latch ( LM1) 106 Latch (LM2) 111, 113 OR gate 112 Delay latch

Claims (2)

[Claims] 1. Program storage means for storing a predetermined program, addressing means for addressing the program storage means, calculation data storage means capable of writing and reading calculation data, and instructions output from the program storage means. an instruction decoding means for decoding an operation code included in the instruction; an arithmetic data addressing means for addressing the arithmetic data storage means using operands included in the instruction output from the program storage means; and according to the decoding result of the instruction decoding means. and a calculation means for executing an operation on the calculation data storage means, wherein the addressing means causes a part of the program storage means to branch on the premise of return based on the immediate value data of the operand. address changing means for specifying an address; address storage means for temporarily storing the address after return;
control means for reading an address of an instruction next to the branch instruction from the address storage means as a post-return address in response to a return instruction of the program storage means; and a second control means for reading and storing an operand included in the instruction after the return. 1. A central processing unit comprising: data storage means for storing read data; and data storage means for storing read data. 2. Program storage means for storing a predetermined program, addressing means for addressing the program storage means, calculation data storage means capable of writing and reading calculation data, and instructions output from the program storage means. an instruction decoding means for decoding an operation code included in the instruction; an arithmetic data addressing means for addressing the arithmetic data storage means using operands included in the instruction output from the program storage means; and according to the decoding result of the instruction decoding means. a central processing unit comprising: arithmetic means for executing an arithmetic operation on the arithmetic data storage means; a first subroutine branch instruction for branching on the premise of return; and a predetermined control signal output from the branch decoding means. a second subroutine branch instruction, a delay means for delaying the control signal and outputting a delayed control signal, and a delay control signal output from the delay means to output immediate data output from the program storage means after branching. What is claimed is: 1. A central processing unit comprising a storage means for reading and storing information, and returning after reading to process an instruction immediately after a branch.