JPH04314183A - Image processing device - Google Patents

Abstract

PURPOSE:To solve roughness without impairing the sharpness of an image especially in a mode part by detecting the direction of the concentration gradient of an aimed picture element, and applying the smoothing processing of the image in a direction orthogonal to a detected concentration gradient. CONSTITUTION:It is detected whether the aimed picture element is a character area or non-character area at the area processing circuits 115-11, 115-21, of a feature extraction circuit 115. Meanwhile, a picture element correction circuit 122 detects the direction of the concentration gradient of the aimed picture element, and performs the smoothing of the aimed picture element in the direction orthogonal to the direction of the detected concentration gradient. Thence, smoothed image data is outputted as it is. Or, for example, when it is judged that the aimed picture element is the character area by the area processing circuits 115-11, 115-21, the smoothed data is outputted, and when it is judged that the aimed picture element is the non-character area, picture element correction or original picture element correction circuit 122 input data is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, for example, an image processing apparatus that processes full-color images.

0002

2. Description of the Related Art Conventionally, devices have been devised that read full-color images, process them as electrical signals, and output them. For example, Canon CLC-1, CLC-500, CLC
-200 etc. Furthermore, full-color images can be
A method of encoding and decoding each pixel block of 4 has been proposed (= block coding, for example,
41826), a copying machine that outputs a read full-color image after temporarily storing it in a memory is also known.

0003

However, in the example of block encoding described above, image encoding and decoding processing is performed using, for example, 4x4 pixel blocks, and a non-information preserving encoding method ( For example, vector quantization), in principle an encoding error occurs for each pixel block. As a result, image roughness occurs in pixel block units,
In particular, there was a problem in that the image quality deteriorated significantly in the text portion of the manuscript.

That is, when an image having a density pattern as shown in FIG. 23(a) is encoded/decoded by block encoding, an image as shown in FIG. 23(b) is obtained. However, it was noticeable in 4x4 units.

[0005]

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and has the following configuration as a means for solving the above-mentioned problems. That is, a detection means for detecting the direction of a density gradient in a pixel of interest of image data having shading, and a smoothing means for smoothing the image data having shading in a direction orthogonal to the direction of the density gradient detected by the detection means. Equipped with.

[0006]

[Operation] In the above configuration, by detecting the direction of the density gradient of the pixel of interest and performing image smoothing processing in the direction orthogonal to the detected density gradient, the sharpness of the image is lost, especially in the mode part. You can eliminate roughness without any problem.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. [First Example] Hereinafter, as an example according to the present invention,
An example applied to a full-color copying machine will be explained in detail.

FIG. 1 shows an overview of an apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 201 denotes a document table glass, on which a document 202 to be read is placed. The original 202 is illuminated by a light 203, and the reflected light is reflected by a mirror 2.
CC through the action of optical system 207 through 04, 205, 206
An image is formed on D208. Furthermore, the mirror unit 21 including the mirror 204 and the illumination 203 is driven by the motor 209.
0 is mechanically driven to scan the lower part of the document table glass 201 at a speed V. At the same time, the second mirror unit 211 including mirrors 205 and 206 is also driven at a speed (V/2), and the entire surface of the original 202 is scanned.

Reference numeral 212 denotes an image processing circuit section, which processes read image information as an electrical signal and outputs it as a print signal. Semiconductor lasers 213 to 216 are turned on and off according to drive data for each color from the image processing circuit 212, and the laser light emitted by each semiconductor laser is transmitted to polygon mirrors 217 to 216.
220, latent images are formed on photosensitive drums 225-228. 221 to 224 are black (Bk), respectively.
A developing device that develops a latent image using yellow (Y), cyan (C), and magenta (M) toners.The developed toners of each color are transferred to paper and a full-color printout is made. Ru.

Paper fed from one of the paper cassettes 229, 230, 231 and the manual feed tray 232 passes through registration rollers 223, is attracted onto a transfer belt 234, and is conveyed. Toner of each color is developed in advance on the photosensitive drums 228227, 226, and 225 in synchronization with the timing of paper feeding, and the toner is transferred onto the paper as the paper is conveyed.

[0011] The paper to which each color of toner has been transferred is separated/
The paper is transported, toner is fixed on the paper by a fixing device 235, and the paper is discharged onto a paper discharge tray 236. The detailed configuration of the image processing circuit 212 shown in FIG. 1 is shown in FIGS. 2 and 3. 2 and 3, 101, 102, and 103 are CCD sensors that read red (R), green (G), and blue (B), respectively, and the CCD sensor 208 in FIG.
corresponds to Analog data read from the CCD sensors 101 to 103 is sent to analog amplifiers 104 to 106.
and converted into corresponding digital signals by A/D converters 107 to 109, respectively. 110
, 111 is a delay memory, which corrects the spatial deviation between the three CCD sensors 101, 102, 103.

112 is a color space converter, which converts R, G, B
For example, as shown in (Sho 63-141826), the signals are converted into a lightness signal L* and a chromaticity signal a* using equations (1) and (2).
, b*.

[0013]

[Formula 1] however,

[0014]

[Formula 2] αij, βij, X0, Y0
, Z0 are constants.

FIG. 4 shows the detailed configuration of the encoder for the lightness component L* of the color space converter. In FIG. 4, 711 to 71
3 is a line memory providing one line delay. 71
4 is a 4×4 block extraction circuit, and 715 is a vector quantization circuit that performs vector quantization. As shown in Fig. 5, the data is cut out in units of 4x4 blocks.
-141826 etc.)
15, the brightness information is quantized in units of blocks.

FIG. 6 shows a block diagram of an encoder for chromaticity components a* and b*. 721, 722, 723, 725
, 726, 727 are line memories similar to 711, 722, 713, and 724, 728 are block extraction means similar to 714, which extract the a* and b* signals in blocks, respectively. 729 is a known vector quantizer, which quantizes the chromaticity information in units of blocks.

As will be described later, XPHS and YPHS are 2-bit counter values in the main scanning/sub-scanning directions, respectively.
Synchronize in block units of ×4. On the other hand, 115 in FIG.
is a feature extraction circuit, and a black pixel detection circuit 115- outputs a determination signal K1' indicating whether or not the pixel is a black pixel.
1. A 4x4 area processing circuit 115-11 which inputs the K1' signal and outputs a K1 signal indicating whether or not the inside of the 4x4 pixel block is a black pixel area; A character pixel detection circuit 115-2 outputs a determination signal K2' indicating whether or not the above K2' signal is input, and outputs a K2 signal indicating whether or not the inside of the 4×4 pixel block is a character pixel area. 4×4 area processing circuit 1
Consists of 15-21.

Regarding the black pixel detection circuit 115-1 and the character pixel detection circuit 115-2, their circuit configurations and determination criteria are well known and will not be described here. A memory 116 stores an L-code signal that is a code for brightness information, an AB-code signal that is a code for chromaticity information, and judgment signals K1 and K2 that are the results of feature extraction.

141 to 144 are respectively magenta (M)
, cyan (C), yellow (Y), and black (Bk), and since each color has almost the same configuration, only magenta is shown. In the density signal generation circuit 141, 117 is a lightness information decoder, and L-cod
The L* signal is decoded by the e signal, and 118 is a chromaticity information decoder, which decodes the a* and b* signals by the ab-code signal.

119 is a color converter, and the decoded L
*, a*, b* signals are used to convert the toner development colors into magenta (M), cyan (C), yellow (Y), and black (Bk) color components. 7 and 8 show detailed block diagrams of the color conversion means 119. In the figure, 501 is means for converting L*, a*, b* signals into R, G, B signals, and the conversion is performed according to the following equation.

[0021]

[Formula 3] however,

[0022]

[Formula 4] (αij') is the inverse matrix (βij) of (αij) in equation (1)
' is the inverse matrix of (βij) in equation (2). 502, 503, and 504 are brightness/density converters, respectively, and conversion as shown in equation (6) is performed.

[0023]

[Formula 6] 503 is a black extraction circuit, Bk1 = min (C1, M1, Y1)
A black signal Bk is generated as shown in (7).

504 to 507 are multipliers,
After predetermined coefficients a1, a2, a3, a4 are added to each signal of C1, M1, Y1, Bk1,
By adding the signals in the adder 508, a sum product operation is performed (Equation (8)). (Output)=a1 C1 +a2 +M1 +a3
Y1 +a4 Bk1) (8) 509-51
3 is a register, and 119 has a11 and a2, respectively.
1, a31, a41, 0, 120 has a12, a22
, a32, a42, 0, and 121 has a13, a23,
a33, a43, 0, 122 has a14, a24, a
34, a44, a24' are set.

530, 532, 533 are gate signals, 5
32 is a "2 to 1" selector. 520 is N
This is an AND gate, and as a result, it is determined whether or not the pixel is in a black character area by the AND of the black pixel determination signal K1 and the character area determination signal K2, and a1 is determined as shown in FIG.
, a2, a3, and a1 are selected and processed, and the black text portion is developed in units of black, making it possible to obtain a sharp output.

FIGS. 10 and 11 show detailed block diagrams of the spatial filter 121. In the figure, 801 and 802 are line memories, which provide one line of delay. 810,81
1 is an adder, and 812, 813, and 814 are multipliers, on which coefficients b1, b0, and b2 are placed, and 81
An adder 5 performs a sum-product operation. On the other hand, 816-82
1 are registers in which values b11 to b22 are held in advance, and selectors 822, 823, 824
According to the character determination signal K2, b1, b0, b
The value is set to 2.

FIG. 12 shows K2, b0, b1, b2
shows the relationship between the values of For example, b01=(4/8), b1
1=(1/8), b21=(1/8), b02=(12
/8), b12=-(1/8), b22=-(1/8)
If the values are written in registers 816 to 821 in advance, K2 = 0, as shown in FIG. can.

On the other hand, when K2=1, that is, in a character portion, the sharpness of the character portion can be corrected by forming an edge emphasis filter. Furthermore, 122 in FIG. 3 is a pixel correction circuit, which corrects decoded image data. 13 and 14 show detailed configurations of the pixel correction circuit.

In the figure, CLK is a pixel synchronization signal to be described later, and HSYNC is a horizontal synchronization signal to be described later. 401
, 402 are line memories that provide one line of delay. Flip-flops 403 to 410 each provide a delay of one pixel. As a result, as shown in FIG. 15, eight neighboring pixels X11, X12, X13, X21, X23, X31,
Outputs X32 and X33.

Reference numerals 411 to 414 denote pixel edge detection circuits, which output a value of |A-2B+C|/2 in response to four inputs A, B, and C, as shown in FIG. The B inputs of the four pixel edge detection circuits are all connected to the target pixel X.
22 has been input. X12 and X32 are input to the A input and C input of the edge detection circuit 411, respectively, and as a result, |X12-2X22+X32|/2 is output, which is 2 in the sub-scanning direction shown in This becomes the absolute value of the second differential amount, and outputs the edge strength in the sub-scanning direction shown in (■) in FIG.

X11 and X33 are input to the A input and C input of the edge detection circuit 412, respectively, and as a result,
|X11 - 2X22 + Output. X21 and X23 are input to the A input and C input of the edge detection circuit 413, respectively, and as a result, |X21-2X22+X23|/2 is output.
This becomes the absolute value of the second-order differential amount in the main scanning direction shown in ``■'' in FIG. 15, and outputs the edge strength in the main scanning direction shown in ``■'' in FIG.

X31 and X23 are input to the A input and C input of the edge detection circuit 414, respectively, and as a result,
|X31 - 2X22 + Output. 415 in FIG. 14 is a maximum value detection circuit, which determines which input signal has the maximum value among the four input signals a, b, c, and d, and outputs a 2-bit determination result y. . Details of this maximum value detection circuit 415 are shown in FIG.

In FIG. 17, 421 is a comparator, and the comparison result of a and b is "1" only when a>b.
422 is a 2 to 1 selector, which inputs a and b to two input signals A and B, and outputs a selector signal S.
By inputting the comparison result of the comparator 421 to , the maximum max (a, b) of a and b is output as a result. Similarly, from the comparator 423 and selector 424, c
The comparison result of and d and the maximum value max(C, d) of c and d are output.

Furthermore, the maximum value max (a, b) of a, b and the maximum value max (c, d) of c, d are compared by a comparator 425, respectively, and a y1 signal is output. As a result, the y1 signal is the maximum value ma of a, b, c, d
“1” when the value of x (a, b, c, d) is a or b
becomes. (maximum value max(a, b,
c, d) is “0” when the value is c or d. )4
26, 427, and 429 are NAND gates with two inputs, and 428 is an inverter. As a result, the y0 signal is such that the maximum value max (a, b, c, d) of a, b, c, d is a or c. Sometimes it becomes “1”. Also, a, b, c
, d becomes "0" when the value of the maximum value max (a, b, c, d) is b or d.

That is, the maximum value max(a
, b, c, d), the 2-bit outputs y0, y1 of the maximum value detection circuit are as follows. When max (a, b, c, d) = a
y0 =1 y1 =1 max(a,b
, c, d) = b when y0 = 0
y1 = 1 max (a, b, c, d) = c
When y0 =1 y1 =0
When max (a, b, c, d) = d
y0 =0 y1 =0 416 to 419 in Figure 14
are smoothing circuits, and as shown in FIG.
For the three inputs A, B, and C, the value (A+2B+C)/4 is output. The pixel of interest X22 is input to the B inputs of all four smoothing circuits.

X12 and X32 are respectively input to the A input and C input of the smoothing circuit 413 in FIG. 14, and as a result, (X12+2X22+X32)/4 is output. Smoothing processing in the sub-scanning direction shown in is performed and output. X11 and X33 are respectively input to the A input and C input of the smoothing circuit 417, and as a result, (X11+2X22+X33)/4 is output. is subjected to smoothing processing and output.

X21 and X23 are input to the A input and C input of the smoothing circuit 418, respectively, and as a result, (X
21+2X22+X23)/4 is output, but this is subjected to the smoothing process in the main scanning direction shown in (■) in FIG. 15 and then output. X31 and X13 are input to the A input and C input of the smoothing circuit 419, respectively, and as a result,
(X31 + 2X22 +

420 is a 4 to 1 selector,
It operates according to the following logic for four input signals A, B, C, and D and a 2-bit selector signal S. When S=00, output B input (Y←
B) When S=01, output A input (
Y←A) When S=10, output the D input (Y←D) When S=11, output the C input (Y←C) Therefore, the final output of the pixel correction circuit 122 is as follows. Become.

That is, considering the case of FIG. 15, when the edge amount in the {circle around (2)} direction is the maximum, smoothing is performed in the {circle over (2)} direction. When the edge amount in the ■ direction is maximum, smoothing is performed in the ■ direction. When the edge amount in the ■ direction is maximum, smoothing is performed in the ■ direction. When the edge amount in the ■ direction is maximum, smoothing is performed in the ■ direction.

The operation of this embodiment having each of the above configurations is as follows.
This will be explained below with reference to the timing chart of FIG. The START signal in FIG. 19 is a signal indicating the start of the document reading operation in this embodiment. While the WPE signal is being output, this is a period during which the document reading mechanism reads the document, performs encoding processing, and memory writing processing. Therefore, this WPE
When the period ends, the recording preparation is completed.

The ITOP signal is a signal indicating the start of a print operation, the MPE is a section signal for driving the magenta semiconductor laser 216 in FIG.
YPE is a section signal for driving the cyan semiconductor laser 215 in FIG.
14, and BPE is a section signal that drives the black semiconductor laser 213 in FIG.

As shown in FIG. 19, CPE, YPE, BP
E are delayed by t1, t2, t3 with respect to MPE, respectively, which corresponds to d1, d2, d3 in Fig. 1.
For, t1 = d1 /ν, t2 = d2 /ν,
It is controlled to have the following relationship: t3 = d3 /v (v is the paper feed speed). In addition, the lower part of FIG. 19 shows the specific processing timing of recorded image data, and HSYN
The C signal is a main scanning synchronization signal, and the CLK signal is a pixel synchronization signal. YPHS is a count value of a 2-bit sub-scanning counter, and XPHS is a count value of a 2-bit main-scanning counter. As shown in FIG. 20, the inverter 10
01 and 2 bit counters 1002 and 1003.

[0043] The BLK signal is a synchronization signal for each 4×4 pixel block, and the 4×4 pixel block is synchronized at the timing indicated by BDATA.
Processing is performed in units of 4 blocks. Next, area processing circuits 115-11 and 115 shown in FIG. 2 perform area processing.
-21 is shown in FIG. 21. The area processing circuit of this embodiment executes 4×4 area processing.

In the figure, CLK is a pixel synchronization signal, HSYNC
indicates the main scanning synchronization signal. 901 to 903 are line memories that provide one line of delay; X1, X2, X
3 are delayed by 1 line, 2 lines, and 3 lines, respectively, with respect to the input signal X in the sub-scanning direction. 9
04 is an adder, which counts the number of pixels that are "1" among X, X1, X2, and X3 corresponding to the four pixels of the binary signal X in the sub-scanning direction.

Flip-flops 905 to 908 each provide a delay of one pixel. 909 is an adder, and as a result, 4×4 blocks (
The number of pixels that are "1" within 16 pixels) is counted. 910 is a “2 to 1” selector, 911 is N
OR gate 912 is a flip-flop, XPH
Generate a BLK signal from S(0) and XPHS(1),
The number of pixels C1, where X=1, is calculated in units of ×4 blocks. This calculated value is compared with C2 preset in register 913 by comparator 914. The output y of the comparator 914 is 1 only when C1 > C2, and the output y is 0 otherwise. This output y is output at the timing indicated by BDATA in the timing chart shown in FIG.

Here, what is characteristic is that the image signals L-code and ab-code signals obtained by encoding and the feature signals K1 and K extracted by the feature extraction circuit
2 are output in a one-to-one correspondence in units of 4×4 blocks as shown in FIG. That is, an image code and a feature signal are extracted for each 4×4 block, and stored in the memory at the same address or an address calculated from the same address, and when read out, they are read out in correspondence with each other.

A specific example of the character pixel detection process in the area processing circuits 115-11 and 115-21 of this embodiment described above will be described below using the case of FIG. 22 as an example. For example, for a document as shown in 1201 in this embodiment, 1
Assume that in the portion shown in 201-1, it is determined whether each pixel is a character pixel or not. As a result of this determination, for example, as shown in 1202, the part indicated by ○ is K1'
= 1, and the other portions are determined to be K1' = 0, in the above-mentioned area processing circuit 115-11, for example, C
By setting 2 = 4, it corresponds to 4x4 block,
A noise-free signal as shown in 1203 can be obtained.

Similarly, the judgment result K2 of the black pixel detection circuit
'A similar circuit (115-21 in Figures 2 and 3)
), it is possible to obtain a signal K2 corresponding to a 4×4 block. The image correction results of this example described above are shown in FIG. 23(c). When an image with a density pattern as shown in FIG. 23(a) is encoded/decoded by block encoding, (b)
As shown in FIG. 2, roughness may appear in 4×4 units due to encoding errors. Therefore, by applying the smoothing process described above in this embodiment to (b), (
As shown in c), a high-quality processed image with reduced roughness is obtained. For example, the pixel shown in A in (b) is (
Since it is decoded to a higher density than the pixel corresponding to A in a), it becomes a cause of image roughness.

However, in the case of pixel A in (b), as shown in FIG.
Since the amount of edge (density gradient) in the direction of ``2'' shown in 5 is larger than the edge amount in the other directions, in this embodiment, smoothing is performed in the direction of ``2'' orthogonal to ``2'', and the density is corrected to be lower. Similar corrections are made for each of the other pixels, and the overall roughness is reduced as shown in (c). Furthermore, since the smoothing process is performed in the direction perpendicular to the density gradient, the sharpness of the character portion is not impaired.

By executing the above-described processing and storing image information and feature (attribute) information in correspondence at the same address in memory or an address calculated from the same address, for example, when reading and writing from memory, the address can be changed. It is possible to share and simplify the control circuit. Further, even when editing processing such as scaling and rotation is performed on the memory, it can be performed with simple processing, and the system can be optimized.

[Second Embodiment] In the first embodiment described above, an example has been described in which pixel correction is performed on all decoded images, especially in order to correct roughness in character portions. However, the present invention is not limited to the above example, and it also falls within the scope of the present invention to change the processing depending on the type of image to be processed.

For example, the sharpness of the image may be lost due to the smoothing process for parts other than text, especially for manuscripts such as silver halide photographs. Therefore, if control is performed to perform pixel correction on the text area portion of the document, a high-quality processed image can be obtained even if the document includes both photographic areas and text areas. A second embodiment of the present invention in which the processing is changed according to the type of image to be processed will be described below.

The second embodiment also has a general configuration similar to that of the first embodiment described above, but the second embodiment differs in part in the configuration of the pixel correction circuit 122 shown in FIG. 3. FIG. 14 of the pixel correction circuit 122 in the second embodiment according to the present invention
FIG. 24 shows the detailed configuration of the parts that are different from the first embodiment shown in FIG. In the second embodiment, the portion shown in FIG. 13 of the first embodiment has exactly the same configuration, and illustration thereof is omitted. Further, in FIG. 24, the same components as those in FIG. 14 in the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, instead of using the output of the 4 to 1 selector 420 as the output of the pixel correction circuit 122, the output of the 2 to 1 selector 1401
input to the B input of On the other hand, selector 1 of 2 to 1
The signal X23 before correction is input to the A input of 401, and the output signal from the selector 420 after correction and the signal before correction are determined by the character area determination signal K2 indicating that the pixel X23 is in the character area. The signal X23 is switched and output.

As a result, when the pixel of interest X23 with K2="1" is located in the character area, a signal without pixel correction, that is, X23 itself is output. On the other hand, K2
If the pixel X23 is not in the character area, which is ="0", a pixel-corrected signal is output. As a result, the roughness in the text portion is corrected, while the other portions do not lose their sharpness.

[Third Embodiment] Furthermore, instead of performing pixel correction on all decoded images in the first embodiment, control is performed to perform smoothing processing on only a part of the processing block. Therefore, even if the image types are different, image processing can be performed without losing sharpness. A third embodiment of the present invention in which smoothing processing is performed on only a portion of a processing block will be described below.

The third embodiment also has a general configuration similar to that of the first embodiment described above, but the third embodiment differs in part in the configuration of the pixel correction circuit 122 shown in FIG. 3. FIG. 14 of the pixel correction circuit 122 in the third embodiment according to the present invention
FIG. 25 shows the detailed configuration of the parts that are different from the first embodiment shown in FIG. In the third embodiment as well, like the second embodiment, the portion shown in FIG. 13 of the first embodiment has exactly the same configuration, and illustration thereof is omitted. Further, in FIG. 25, the same components as those in FIG. 14 in the first embodiment described above are given the same reference numerals, and detailed description thereof will be omitted.

In FIG. 25, 1501 is 2 to 1
selector, 1502 is an AND gate, 1503, 15
04 is an exclusive OR gate. In the third embodiment, instead of directly using the output of the 4 to 1 selector 420 as the output of the pixel correction circuit 122, the output of the 4 to 1 selector 420 is
1 to the B input of selector 1501. On the other hand, 2
The signal X23 before correction is input to the A input of the selector 1401 of to 1, and the output signal from the selector 420 after correction and the signal X23 before correction are switched and outputted by the signal from the AND gate 1502. .

In the configuration consisting of the AND gate 1502 and the exclusive OR gates 1503 and 1504, the timing of XPHS="0" or "3" and YPHS="0" or "3" in the timing chart shown in FIG. At the timing of ``, the output of the AND gate 1502 is set to ``0'', and the output of the selector 1401 outputs the corrected output signal from the selector 420, and in other cases, the output of the AND gate 1502 is set to ``1''. The signal X23 before correction is output.

As a result, as shown by diagonal lines in FIG.
The result of performing the smoothing correction process only on the four corners of the pixel block No. 4 is output. This is the encoding
This study focuses on the fact that the roughness of the text area caused by decoding is largely due to encoding errors at the four corners of a 4x4 pixel block, and smoothing processing reduces the sharpness of the image outside of the text area. It has the effect of preventing damage to the

[Fourth Embodiment] Furthermore, in the above embodiments, pixel correction was performed on encoded/decoded images for the purpose of correcting image quality deterioration due to encoding/decoding. The present invention is not limited to the above examples. In other words, it is effective for correcting roughness in character parts due to various causes such as noise entering the sensor, and is also effective for digital image processing devices that do not have image memory. .

Note that the present invention may be applied to a system composed of a plurality of devices, or to an apparatus composed of one device. It goes without saying that the present invention can also be applied to cases where the present invention is achieved by supplying a program to a system or device.

[0063]

As explained above, according to the present invention, by detecting the direction of the density gradient of the pixel and performing image smoothing processing in the direction orthogonal to the detected density gradient, the image is smoothed, especially in text areas. It is possible to eliminate roughness in pixel block units without impairing the sharpness of the image.

[Brief explanation of the drawing]

FIG. 1 is an external view of an apparatus according to an embodiment of the present invention.

[Figure 2] and

FIG. 3 is a diagram showing the detailed configuration of the image processing circuit of this embodiment.

FIG. 4 is a diagram showing a detailed configuration of a lightness component L* encoder according to the present embodiment.

FIG. 5 is a diagram for explaining an example of data extraction by the encoder of this embodiment.

FIG. 6 is a diagram showing a detailed configuration of an encoder for brightness components a* and b* in this embodiment.

[Figure 7] and

FIG. 8 is a diagram showing a detailed configuration of the color conversion circuit of this embodiment.

FIG. 9 is a diagram illustrating masking coefficients of this embodiment.

[Figure 10] and

FIG. 11 is a diagram showing the detailed configuration of the spatial filter of this embodiment.

FIG. 12 is a diagram illustrating each signal relationship of the spatial filter of this embodiment.

[Figure 13] and

FIG. 14 is a block diagram showing the detailed configuration of the pixel correction circuit of this embodiment.

FIG. 15 is a diagram for explaining the processing of the pixel correction circuit of this embodiment.

16 is a diagram showing a detailed configuration of the pixel edge circuit shown in FIG. 14. FIG.

FIG. 17 is a diagram showing the detailed configuration of the maximum value detection circuit of this embodiment.

18 is a diagram showing a detailed configuration of the smoothing circuit shown in FIG. 14. FIG.

FIG. 19 is an image processing timing chart of this embodiment.

FIG. 20 is a diagram showing a generation circuit for XPHS and YPHS signals.

FIG. 21 is a diagram showing a detailed configuration of an area processing circuit.

FIG. 22 is a diagram illustrating area processing in character pixel detection in this embodiment.

FIG. 23 is a diagram showing the results of pixel correction.

FIG. 24 is a diagram showing a part of a pixel correction circuit according to a second embodiment of the present invention.

FIG. 25 is a diagram showing a part of a pixel correction circuit according to a third embodiment of the present invention.

FIG. 26 is a diagram illustrating a smoothing circuit in a third embodiment.

[Explanation of symbols]

101~103,208 CCD104~106
Analog amplifier 107-109 A/D
Converter 112 Color space converter 115 Feature extraction circuit 115-1 Black pixel detection circuit 115-11, 115-21 4×4 area processing circuit 115-2 Character pixel detection circuit 116 Memory 117, 118 Decoder 119 Color converter 141-144 Concentration signal generation circuit 201
Document table glass 202 Document 203 Illumination 204-206 Mirror 207 Optical system 210 Mirror unit 211 Second mirror unit 212 Image processing circuit section 213-216 Semiconductor laser 217-220 Polygon mirror 225-228
Photosensitive drums 221 to 224 Developing units 411 to 414 Pixel edge detection circuit 415
Maximum value detection circuits 416 to 419 Smoothing circuits 421, 423, 425 Comparator 422,
424 Selector 714, 724, 728 4×4 block extraction circuit 715 Vector quantization circuit 729 Vector quantizer

Claims (6)

[Claims] 1. Detecting means for detecting the direction of a density gradient in a pixel of interest of image data having shading, and smoothing the image data having shading in a direction perpendicular to the direction of the density gradient detected by the detecting means. An image processing device comprising: smoothing means. 2. The image data smoothed by the smoothing means is obtained by encoding/decoding each pixel block of m×n (m and n are integers of 2 or more) pixels. The image processing device according to claim 1. 3. The image processing apparatus according to claim 1, wherein the image data smoothed by the smoothing means is color-separated full-color image data. 4. The image processing apparatus according to claim 2, wherein the smoothing means smoothes only specific pixels in the m×n pixel block. 5. A storage means for reading and encoding a full-color original and storing the encoded data; and a storage means for reading and decoding the stored encoded data of the storage means to generate image data having shading and transmitting the encoded data to the detection means. 4. The image processing apparatus according to claim 2, further comprising: a generating means for outputting the data, and an image outputting means for outputting the smoothed data by the smoothing means. 6. The pixel of interest is characterized by comprising a determining means for determining whether or not the pixel of interest is a character part of the document, and the smoothing means performs smoothing only when the determining means determines that the pixel is a character part. An image processing apparatus according to any one of claims 1 to 5.