JPH04314230A - Bit correlation deciding circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] For example, in a receiving device for frame-based data communication, bit correlation is used to correlate the received data and frame synchronization code as two data sequences when determining the frame synchronization position of the received data. A decision circuit is used. The present invention relates to a bit correlation determination circuit that determines the correlation between such two data sequences.

0002

2. Description of the Related Art Generally, a conventional circuit used as a bit correlation determination circuit for determining the correlation between two data series has a configuration in which a counter counts the correlation output of 1 bit corresponding to each bit. FIG. 5 is a block diagram showing an example of a conventional correlation determination circuit. In the figure, 51 is an N-bit exclusive OR (EX-OR) gate, which inputs N-bit input data as one data series and reference data as the other data series, and inputs these two data series. N 1-bit correlation signals E1, E2, ..., each representing coincidence or mismatch corresponding to each bit of the sequence;
It is an N-bit correlator that outputs EN. 52 is a parallel/serial conversion shift register, and N of the EX-OR gate 51
1-bit correlation outputs E1, E2, ..., EN
is stored once, converted to serial data using a clock that is N times the input speed, and output. 53 is a parallel/serial conversion shift register 5
This is a counter that inputs the output of No. 2, that is, the number of matching and non-matching bits, and counts one of the numbers. A comparator 54 compares the count value counted by the counter 53 with a predetermined tolerance value, performs a correlation determination, and outputs the determination result.

0003

[Problems to be Solved by the Invention] However, in the conventional circuit described above, the N-bit EX-OR gate output is set in parallel and serially shifted every time two data series are newly input. The serial shift and counting operations must be completed with a clock having a frequency N times the rate of change of the series, and the need to operate with a high frequency clock increases the circuit scale and increases power consumption. In particular, there is a drawback that when the rate of change of the input data series becomes large, the processing speed cannot keep up with it. An object of the present invention is to provide a bit correlation determination circuit that can simultaneously support high-speed operation and reduce power consumption by solving the above problems of circuit scale and power consumption.

0004

[Means for Solving the Problems] The bit correlation determination circuit of the present invention determines the correlation between two N-bit (N is a natural number) data series and obtains the determination result. an N-bit correlator that outputs in parallel N correlation signals indicating coincidence "L" or mismatch "H" of each corresponding bit each time it is input; and the N correlation signals from the N-bit correlator. and N cascade-connected correlation determination units each receiving a signal, determining the relationship with the relay input signal from the previous stage, and outputting the relay output signal to the next stage, each of the correlation determination units comprising a set of The status output is set to “L” (set) or “H” (
The relay input signal from the previous stage, the correlation signal, and the state output of the flip-flop circuit are combined and provided to a correlation determination unit in the next stage in synchronization with a predetermined test pulse signal. It consists of a combinational circuit that controls the output of the relay output signal and the output of the set signal applied to the flip-flop circuit, and the relay input signal of the combinational circuit in the first stage is always "L".
, all of the N flip-flop circuits are initially set to the reset state "H" by the reset signal, and when the relay input signal from the correlation determination unit in the previous stage is "H", the correlation signal is always Regardless of the polarity of the state output from the flip-flop circuit and the polarity of the status output from the flip-flop circuit, "H" is output as a relay output signal to the next stage, and the set signal to the flip-flop circuit is stopped, and the correlation determination unit of the previous stage The relay input signal from
”, when the correlation signal is “H” or “L” at reset, “H” or “L” is output as a relay output signal to the next stage, and after reset, the test pulse signal is When the correlation signal is "H" and the state output of the flip-flop circuit is in a reset state "H", a set signal synchronized with the test pulse is given to the flip-flop circuit each time the correlation signal is "H". By setting the flip-flop circuit in the set state "L", a relay output signal of "L" is output, and if the state output of the flip-flop circuit is in the set state "L", it is output as a relay output signal to the next stage. "L" is output, and when the correlation signal is "L", control is performed to output "L" as a relay output signal to the next stage, regardless of the polarity of the status output from the flip-flop circuit. The present invention is characterized in that the relay output signal from the correlation determination unit at the final stage is configured to provide the desired correlation determination result.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The bit correlation determination circuit of the present invention determines the correlation between two N-bit (N is a natural number) data series and outputs the determination result. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 4 is an N-bit correlator, for example, an N-bit EX-OR gate. Two N-bit (N is a natural number) data series, such as input data and reference data, are input to this N-bit correlator 4, and N 1-bit correlation signals E1, E2, . . . are generated at each input data update timing. EN is output in parallel. These N 1-bit correlation signals E1, E2,...E
N is a signal indicating whether each bit of the two N-bit data series matches "L" (low level) or mismatches "H" (high level). 3 is a correlation determination unit, N
N correlation determining units 3 each receiving 1-bit correlation signals E1, E2, . . . EN are connected in cascade. The relay signal output of each correlation determination unit 3 serves as the relay signal input of the correlation determination unit 3 at the next stage. FIG. 2 is a block diagram showing an example of the configuration of the correlation determination unit 3, which is a main part of the present invention shown in FIG.
It is composed of a flip-flop circuit 1 and a combinational circuit 2. The flip-flop circuit 1 is reset or set by an external reset signal or a set signal from the combinational circuit 2, and outputs the resulting state. The external reset signal is used to initialize the flip-flop circuits of all correlation determination units 3 to a reset state at each update timing of the input data series. The combinational circuit 2 receives and combines the 1-bit correlation signal, the state output of the flip-flop circuit 1, and the 1-bit relay input signal from the previous stage, and operates the flip-flop according to a predetermined test pulse (clock) supplied from the outside. Output of set signal to circuit 1 and correlation determination unit 3 in the next stage
Controls the output of relay output signals to.

[0006]

[Operation] The operation of the present invention based on the embodiment shown in FIGS. 1 and 2 will now be described. First, the correlation determination unit 3 is initialized (reset) by a reset signal at every update timing of the input data series, and outputs a relay output signal according to the test pulse signal inputted after the reset. It is assumed that the binary state output of the flip-flop circuit 1 represents a reset state as "H" and a set state as "L". Further, a relay input signal and a relay output signal are also expressed as "L" or "H", respectively. Further, the relay input signal of the first-stage correlation determining unit 3 is always set to "L".

First, the case where the relay input signal to any correlation determination unit 3 from the second stage onward is "H", that is, the case where the relay output signal from the previous stage is "H" will be described. In this case, regardless of the polarity ("L" or "H") of the current stage's correlation signal input to the correlation determination unit 3 and the state output of the flip-flop circuit 1, "H" is output as the relay output signal, and In the correlation determination unit 3, output of the set signal synchronized with the test pulse signal by the combinational circuit 2 to the flip-flop circuit 1 is stopped, and the output of the set signal to the flip-flop circuit 1 is stopped.
is maintained in the reset state “H”.

Next, the case where the relay input signal to the correlation determination unit 3, ie, the relay output signal of the previous stage, is "L" will be explained. When the correlation signal input to the current stage is "H", one of the following two operations is performed according to the status output of the flip-flop circuit 1. That is, (Operation ■) If the state output of the flip-flop circuit 1 is "H", that is, in the reset state, "H" is output as the relay output signal, and a set signal synchronized with the test pulse signal is input to the flip-flop circuit 1. and the flip-flop circuit 1 is in the set state “L”.
”, so “L” is output as the relay output signal. (
Operation (2) If the status output of the flip-flop circuit 1 is "L", that is, in the set state, "L" is output as the relay output signal. On the other hand, when the correlation signal input to the current stage is "L", "L" is output as the relay output signal regardless of the polarity of the state output of the flip-flop circuit 1 input to the combinational circuit 2.

FIG. 4 is a circuit diagram showing a more detailed embodiment of the correlation determination unit 3 shown in FIG. 2. In FIG. In the figure, 41
43 is a NAND gate, 44 and 45 are inverters, and 46 is a D type flip-flop. In the figure, a signal fed back from a D-type flip-flop 46 is input to one input of a first NAND gate 41, and a correlation signal is input to the other input. The output of this first NAND gate 41 is connected to the second NAND gate 42.
and is output to one input of the first inverter 44 . The second NAND gate 42 is the first NAND gate 41
The signal from the inverter 45 is input to one side, and the inverted output obtained by inverting the relay input signal by the second inverter 45 is input to the other input, and a relay output signal is output. The output of the first inverter 44, the output of the second inverter 45, and a clock (test pulse signal) are input to the third NAND gate 43, and controls the clock output to the D-type flip-flop 46. It is clear that the operation of the correlation determining unit 3 made up of the flip-flop 1 and the combinational circuit 2 shown in FIG. 2 is carried out by such a configuration.

The above series of operations is performed at the time of reset and every time a test pulse signal is input thereafter. That is, first, the relay output signal of the final stage unit clearly outputs "L" when all the bits of the two series data match ("L"). Next, if there is a mismatched bit, the correlation signal corresponding to the mismatched bit is “
Therefore, in the configuration of FIG. 1, all the relay output signals on the right side from the leftmost unit to which the correlation signal "H" indicating a mismatch is input from the N-bit correlator 4 are "H". ” becomes.

In order to facilitate understanding, an example of correlation determination operation in the case of N=6 (6-bit correlation) will be described below with reference to FIG. FIG. 3 shows each correlation determination unit 31 according to the present invention.
It is an explanatory diagram showing a change of the output signal of -36. In the figure, reference numerals 31 to 36 are correlation determination units connected in cascade in six stages, which determine the state of the relay output signal at each time point of the initial state (reset) and the first input and second input of the test pulse signal after reset. are shown at the bottom of the correlation determination unit. In this example, a correlation signal of "H" indicating a mismatch is input to units 32 and 35, and a correlation signal of "L" indicating a match is input to the other units. First, in the initial state (reset), the relay output signal of the first stage unit 31 is always "L", so among the units to which the correlation signal "H" is input from the correlator 4, the leftmost unit 32 and the right side are the final The relay output signal becomes "H" until it reaches the stage unit 36. Next, when the first test pulse signal after reset is input to all the correlation determination units 31 to 36, the unit 32 determines that the relay input signal from the previous stage is "L" and that the input correlation of the current stage is "L". Since the signal is "H" and the state output of the flip-flop circuit 1 is "H", a set signal is given to the flip-flop circuit 1 and the flip-flop circuit 1 is
is set (“L”). As a result, the relay input signal from the previous stage is "L", the input correlation signal of the current stage is "H",
Since the state output from the flip-flop circuit 1 becomes "L", the relay output signal is inverted to "L". However, in unit 35, since the relay input signal from the previous stage is "H", the relay output signal is not inverted.
The output of No. 6 remains at "H". Next, when the second test pulse signal is input to all the correlation determination units 31 to 36, the output of the relay output signal of the unit 35 is inverted to "L" as in the case of the unit 32 at the time of the first input. Therefore, "L" is output from the final stage unit 36. In this way, among the correlation determination units whose correlation signal input is in the "H" state every time the test pulse signal after reset is input, the unit whose relay output signal is inverted from "H" to "L" is the final stage. In the end, the number of test pulse signals (second time) is the same as the number of mismatched bits (in this case, 2).
The final stage reaches a state where it outputs "L" for the first time when it is input. Therefore, if the allowable number of error bits in correlation determination is m, then by inputting the m-th test pulse signal, a relay output signal indicating the result of correlation determination between two series of data is obtained from the final stage unit. From the above, in the configuration according to the present invention, if the allowable number of error bits in correlation determination is m, the speed (clock frequency) of the test pulse signal required for correlation determination may be approximately m/N times that of the conventional method, and generally the correlation signal length is N. Since the number m of allowable error bits is set to be small with respect to bits, it is clear that the configuration of the present invention operates with a lower frequency operating clock than the conventional configuration.

0012

[Effects of the Invention] As explained in detail above, by implementing the present invention, it is possible to determine the correlation between two N-bit data series using an operating clock with a lower frequency than in the conventional example. Therefore, high-speed operation can be followed, and power consumption can be reduced. Also,
This eliminates the need for parallel-serial shift registers and counters that were required in the conventional configuration, and the circuit scale can be reduced, which has a great practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Fig. 2] Block diagram showing details of main parts of the present invention

FIG. 3 is an explanatory diagram showing changes in the output signal of each correlation determination unit according to the present invention.

[Fig. 4] An example circuit diagram of the main part of the present invention

[Fig. 5] Diagram of a configuration example of a conventional correlation determination circuit

[Explanation of symbols]

1 Flip-flop circuit 2 Combinational circuit 3, 31-36 Correlation determination unit 4 N-bit correlator 41-43 NAND gate 44, 45 Inverter 46 D type flip-flop 51 N-bit correlator 52 Parallel-serial conversion shift register 53 Counter 54 Comparator

Claims (1)

[Claims] [Claim 1] In order to determine the correlation between two N-bit (N is a natural number) data series and obtain the determination result,
an N-bit correlator that outputs N correlation signals in parallel each time the two data sequences are input, indicating a match "L" or a mismatch "H" of each corresponding bit; and the N-bit correlator. and N cascade-connected correlation determination units each receiving the N correlation signals, determining the relationship with the relay input signal from the previous stage, and outputting the relay output signal to the next stage; Each of the units includes a flip-flop circuit that outputs a status output "L" (set) or "H" (reset) in response to a reset signal given each time a set signal or the data series is input, and a flip-flop circuit that outputs a status output "L" (set) or "H" (reset), and The input signal, the correlation signal, and the state output of the flip-flop circuit are combined, and the output of the relay output signal is provided to the next stage correlation determination unit in synchronization with a predetermined test pulse signal, and the set is provided to the flip-flop circuit. The relay input signal of the combinational circuit in the first stage is always set to "L", and the reset signal causes the N
All flip-flop circuits are in reset state “H”
When the relay input signal from the correlation determination unit in the previous stage is "H", the relay input signal from the correlation determination unit in the previous stage is always set to "H", regardless of the polarity of the correlation signal and the polarity of the status output from the flip-flop circuit. It outputs "H" as a relay output signal and stops the set signal to the flip-flop circuit, and when the relay input signal from the correlation determination unit in the previous stage is "L", the correlation signal becomes "H" at the time of reset. ” or “L”, outputs “H” or “L” as a relay output signal to the next stage, and every time the test pulse signal is given to the combinational circuit after reset, the correlation signal becomes “H”. ”, if the state output of the flip-flop circuit is in the reset state “H”, a set signal synchronized with the test pulse is given to the flip-flop circuit to bring the flip-flop circuit into the set state “L”. outputs "L" as the relay output signal, and the state output of the flip-flop circuit becomes set state "
If the correlation signal is "L", it outputs "L" as a relay output signal to the next stage, and when the correlation signal is "L", it is output to the next stage regardless of the polarity of the status output from the flip-flop circuit. A bit correlation determination circuit configured to be controlled to output "L" as a relay output signal and configured such that the relay output signal from the correlation determination unit at the final stage becomes the desired correlation determination result.