JPH04314337A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH04314337A JPH04314337A JP3079374A JP7937491A JPH04314337A JP H04314337 A JPH04314337 A JP H04314337A JP 3079374 A JP3079374 A JP 3079374A JP 7937491 A JP7937491 A JP 7937491A JP H04314337 A JPH04314337 A JP H04314337A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- solder
- electrode
- wiring
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、複数の半導体素子がそ
の電極端子と回路基板上の配線端子とをろう付けするこ
とによって回路基板上に搭載される半導体装置およびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor elements are mounted on a circuit board by brazing their electrode terminals to wiring terminals on the circuit board, and a method for manufacturing the same.
【0002】0002
【従来の技術】近年、半導体素子を多数個, 微細ピッ
チで基板上に搭載する装置や機器の開発が盛んである。
例えば、メモリカード, 液晶,エレクトロルミネセン
ス (EL)あるいはプラズマディスプレイパネル等が
ある。
これらは、いずれも多数の入出力 (電源, 信号,
制御) 端子電極を有する駆動用ICを用い、このIC
を一定の面積を有するパネル基板に、高密度でしかも薄
型に搭載しなければならない。[Prior Art] In recent years, there has been an active development of devices and equipment that mount a large number of semiconductor elements on a substrate at a fine pitch. Examples include memory cards, liquid crystal, electroluminescent (EL), or plasma display panels. These all have a large number of inputs and outputs (power, signals,
Control) Using a driving IC with terminal electrodes, this IC
must be mounted in a thin and high-density manner on a panel substrate having a certain area.
【0003】このような半導体装置における半導体素子
の従来行われている搭載方式として、(a) Auから
なる金属突起電極 (Auバンプ) を相互に加圧接触
させて接続する方式、あるいは(b) はんだからなる
金属突起電極 (はんだバンプ) を加熱, 溶融させ
て接続する方式があるが、このうち(b) の方式を図
2(a), (b)を引用してエレクトロルミネセンス
(EL) 表示パネルの例について説明する。Conventional mounting methods for semiconductor elements in such semiconductor devices include (a) a method in which metal protruding electrodes (Au bumps) made of Au are brought into pressure contact with each other, or (b) There is a method of connecting by heating and melting metal protruding electrodes (solder bumps) made of solder, but method (b) is called electroluminescence (EL), referring to Figures 2(a) and (b). An example of a display panel will be explained.
【0004】このディスプレイ基板において、ICチッ
プ1の一面には、絶縁保護膜2のコンタクトホールで露
出する図示しないAl電極パッドの上に金属電極41が
設けられ、その上にはんだバンプ5が形成されている。
一方、ELディスプレイ基板は、ガラス基板6の上に発
光層をはんだで形成されたITO電極配線およびAl電
極配線の端部よりなる端子8を有する。端子部ではIT
O配線の上にAl層が積層されており、Al配線はその
まま端子として利用されている。そして、ICチップ1
のはんだバンプ5とディスプレイ基板6の上の端子8と
を位置合わせし、加熱してはんだバンプ5をリフローさ
せることにより電気的に接続する。このあと、ICチッ
プ1と基板6の間の空隙を封止樹脂9で埋め接続部を保
護すると共に、ICチップ1と基板6との接続強度を増
大させる。In this display substrate, a metal electrode 41 is provided on one surface of the IC chip 1 on an Al electrode pad (not shown) exposed through a contact hole in an insulating protective film 2, and a solder bump 5 is formed on the metal electrode 41. ing. On the other hand, the EL display substrate has terminals 8 made of ends of ITO electrode wiring and Al electrode wiring formed by soldering a light emitting layer on the glass substrate 6. IT at the terminal section
An Al layer is laminated on the O wiring, and the Al wiring is used as it is as a terminal. And IC chip 1
The solder bumps 5 and the terminals 8 on the display substrate 6 are aligned, and electrically connected by heating and reflowing the solder bumps 5. Thereafter, the gap between the IC chip 1 and the substrate 6 is filled with a sealing resin 9 to protect the connection portion and to increase the connection strength between the IC chip 1 and the substrate 6.
【0005】[0005]
【発明が解決しようとする課題】しかし、図2に示した
ELディスプレイ装置においては、ICチップ1とガラ
ス基板6との熱膨脹係数が異なるため、はんだバンプ5
のリフローのための加熱温度からの冷却の際に接続部に
応力が生じ、剥離が発生することがある。また、はんだ
リフローの際に金属電極41のはんだ喰われの現象が起
こるおそれがある。そこで応力緩和およびはんだ喰われ
の防止のため、金属電極41には、例えばCr/Cu/
Au, Ti/Pd/Au, Ti/W/Auあるいは
Ti/Pt/Auなどの多層積層構造が採用される。こ
の結果、接続部の接続強度は1mm2 当たり数百gの
値が得られている。しかし、ICチップの電極パッドの
積層数が多いことはコスト高を招くという欠点があった
。However, in the EL display device shown in FIG. 2, since the IC chip 1 and the glass substrate 6 have different thermal expansion coefficients, the solder bumps 5
During cooling from the heating temperature for reflow, stress is generated in the connection, which may cause peeling. Furthermore, there is a possibility that the metal electrode 41 may be eaten away by the solder during solder reflow. Therefore, in order to relieve stress and prevent solder from being eaten away, the metal electrode 41 is made of, for example, Cr/Cu/
A multilayer structure such as Au, Ti/Pd/Au, Ti/W/Au or Ti/Pt/Au is adopted. As a result, the connection strength of the connection portion is several hundred grams per mm2. However, the large number of layers of electrode pads on an IC chip has the disadvantage of increasing costs.
【0006】本発明の目的は、上記の欠点を除き、積層
数を減少させた電極パッドを有するICチップを回路基
板の配線端子と接続してなる低コストの半導体装置およ
びその製造方法を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a low-cost semiconductor device in which an IC chip having electrode pads with a reduced number of laminated layers is connected to wiring terminals of a circuit board, and a method for manufacturing the same. There is a particular thing.
【0007】[0007]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、半導体素子の電極端子と回路基板の配
線端子がはんだ付けされ、半導体素子と回路基板の間の
空隙に樹脂が充填される半導体装置において、半導体素
子の電極端子および回路基板の配線端子はいずれもはん
だに接する側にニッケル層を有し、かつそのニッケル層
の下にアルミニウム層を有するものとする。そして、半
導体装置がEL表示装置であって、回路基板がガラスよ
りなり、Al層と回路基板の間にCr層が介在すること
が有効である。また、本発明の製造方法は、半導体素子
の半導体基板の一面上に表面がNi層、その下がAl層
からなる電極端子を形成し、その上にはんだからなるバ
ンプを固着し、一方回路基板上に表面がNi層、その下
がAl層からなる配線端子を形成し、この配線端子と前
記はんだバンプを接触させた状態で加熱してはんだを溶
融させたのち凝固させ、次いで半導体基板と回路基板の
間の空隙に樹脂を充填し、硬化させるものとする。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method in which electrode terminals of a semiconductor element and wiring terminals of a circuit board are soldered, and a resin is filled in a gap between the semiconductor element and the circuit board. In the semiconductor device to be filled, the electrode terminals of the semiconductor element and the wiring terminals of the circuit board both have a nickel layer on the side in contact with the solder, and have an aluminum layer below the nickel layer. Further, it is effective that the semiconductor device is an EL display device, that the circuit board is made of glass, and that a Cr layer is interposed between the Al layer and the circuit board. Further, in the manufacturing method of the present invention, an electrode terminal is formed on one surface of a semiconductor substrate of a semiconductor element, the surface of which is a Ni layer and the bottom of which is an Al layer, a bump made of solder is fixed thereon, and a circuit board is A wiring terminal is formed with a Ni layer on top and an Al layer on the bottom, and the wiring terminal and the solder bump are heated in contact with each other to melt and solidify the solder, and then the semiconductor substrate and the circuit are bonded. The gap between the substrates is filled with resin and cured.
【0008】[0008]
【作用】本発明は、半導体素子と回路基板との接続強度
に、素子の電極端子と回路基板の配線端子とのはんだ付
け強度ばかりでなく、半導体素子と回路基板との間の空
隙に充填される樹脂の接着強度も加わるので、はんだ付
け強度の幾分低くても構わないという考え方に基づく。
従って、従来のような多層金属電極構造を必要とせず、
Al層とその上のはんだ付け性の良いNi層との2層が
存在すれば十分である。同時にはんだの両側に同一のN
i/Al層構造が存在することにより、応力分布の均衡
が得られ、接続の信頼性が確保される。[Operation] The present invention improves the connection strength between the semiconductor element and the circuit board, not only by increasing the soldering strength between the electrode terminal of the element and the wiring terminal of the circuit board, but also by increasing the strength of the soldering between the semiconductor element and the circuit board. This is based on the idea that since the adhesive strength of the resin is also added, it does not matter if the soldering strength is somewhat lower. Therefore, there is no need for a conventional multilayer metal electrode structure,
It is sufficient to have two layers: an Al layer and a Ni layer with good solderability thereon. Same N on both sides of the solder at the same time.
The presence of the i/Al layer structure provides a balanced stress distribution and ensures connection reliability.
【0009】[0009]
【実施例】図1(a), (b)は本発明の一実施例を
示し、図2と共通の部分には同一の符号が付されている
。ICチップ1はELディスプレイ基板上の表示素子を
駆動するための、例えば高耐圧Bi−CMOSである。
図3はこのICチップの一部を拡大して示し、チップ1
の一面上に電子ビーム (EB) 蒸着法で被着した厚
さ4000Å程度のAl薄膜をフォトプロセスでパター
ニングし、その一部を電極端子としてのAl電極パッド
3にする。次いで表面に絶縁保護膜としての厚さ300
0Å程度のSiO2膜2を形成し、フォトプロセスで電
極パッド3の周縁部に重なるSiO2 膜を残してコン
タクトホールを開ける。このあと、厚さ4000Å程度
のNi薄膜を全面に蒸着し、フォトプロセスでAl電極
パッド3上にNi電極パッド4を形成する。別の方法と
しては、ICチップ1上にAl薄膜, Ni薄膜を積層
し、フォトプロセスでNi薄膜を、次いでAi薄膜をエ
ッチングして電極パッドを形成し、そのあとで絶縁保護
膜の成膜, コンタクトホール開けを行ってもよい。以
上のようにしてできたICチップ1の電極パッド3,
4の上に、蒸着やめっきにより20〜100 μmの厚
さのはんだパンプ5を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1(a) and 1(b) show an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. The IC chip 1 is, for example, a high voltage Bi-CMOS for driving a display element on an EL display substrate. FIG. 3 shows a part of this IC chip in an enlarged manner, and shows chip 1.
An Al thin film with a thickness of about 4000 Å is deposited on one surface by electron beam (EB) evaporation and patterned by a photo process, and part of it is made into an Al electrode pad 3 as an electrode terminal. Next, a 300 mm thick insulating protective film is applied to the surface.
A SiO2 film 2 having a thickness of approximately 0 Å is formed, and a contact hole is formed by photoprocessing, leaving the SiO2 film overlapping the peripheral edge of the electrode pad 3. Thereafter, a Ni thin film with a thickness of about 4000 Å is deposited on the entire surface, and a Ni electrode pad 4 is formed on the Al electrode pad 3 by a photo process. Another method is to stack an Al thin film and a Ni thin film on the IC chip 1, and then use a photo process to etch the Ni thin film and then the Al thin film to form electrode pads, and then form an insulating protective film. Contact holes may also be made. The electrode pad 3 of the IC chip 1 made as above,
4, a solder pump 5 having a thickness of 20 to 100 μm is formed by vapor deposition or plating.
【0010】一方、EL表示パネルにおいては、図4に
示すようにガラス基板6の上にITO薄膜を2000Å
程度の厚さに形成し、これをフォトプロセスでエッチン
グによりデータ側の電極配線7とする。次に図示しない
が蒸着やスパッタ法により3000〜4000Åの厚さ
の第一絶縁層, 5000〜12000 Åの厚さのZ
nS:Mnからなる発光層、さらに3000〜4000
Åの厚さの第二絶縁層を積層する。次にEB蒸着により
、それぞれ4000Å程度の厚さのAl薄膜81, N
i薄膜82を積層し、フォトプロセスにより、先ずNi
薄膜82, 次いでAl薄膜81を一部がITO配線7
に重なるようにエッチング加工し、ガラス基板6に接す
る部分をデータ側のAl/Ni配線端子8とする。第二
絶縁層上に設けられる走査側の背面電極は、Al単層あ
るいはAl/Ni2層構造とし、Al単層の場合も、ガ
ラス基板上まで延長された部分ではNi薄膜を積層する
ことにより、図5に示すようにそれぞれ厚さ3000Å
程度のAl薄膜81, Ni薄膜82の2層構造となる
。あるいは、Al薄膜の下に厚さ2000Å程度のCr
薄膜を介在させてガラス基板6との密着強度を向上させ
てもよい。いずれの場合も端部は配線端子8となる。On the other hand, in an EL display panel, as shown in FIG.
This is formed to a certain thickness and is etched using a photo process to form the electrode wiring 7 on the data side. Next, although not shown, a first insulating layer with a thickness of 3000 to 4000 Å and a Z layer with a thickness of 5000 to 12000 Å are formed by vapor deposition or sputtering.
nS: a light emitting layer made of Mn, further 3000 to 4000
A second insulating layer with a thickness of Å is deposited. Next, by EB evaporation, thin Al films 81 and N thin films of approximately 4000 Å thick were formed.
The i thin film 82 is laminated, and then Ni is first deposited by a photo process.
The thin film 82 and then the Al thin film 81 are partially covered with the ITO wiring 7.
An etching process is performed so as to overlap with the glass substrate 6, and the portion in contact with the glass substrate 6 is used as the data side Al/Ni wiring terminal 8. The back electrode on the scanning side provided on the second insulating layer has an Al single layer or Al/Ni double layer structure, and even in the case of an Al single layer, a Ni thin film is laminated on the part extending to the glass substrate. Each thickness is 3000 Å as shown in Figure 5.
It has a two-layer structure of an Al thin film 81 and a Ni thin film 82 of about 100 mL. Alternatively, a Cr layer with a thickness of about 2000 Å is placed under the Al thin film.
A thin film may be interposed to improve the adhesion strength to the glass substrate 6. In either case, the end portion becomes the wiring terminal 8.
【0011】ICチップ1の電極パッド3, 4および
はんだバンプ5は、図1(b) に示すようにチップの
4辺を使用することにより、高密度端子の形成を行うこ
とができる。しかし、図6(a), (b)に示すよう
に電極パッド3, 4およびはんだパンプ5をICチッ
プ1の全面に、あるいは図7(a), (b)に示すよ
うに電極パッド3, 4およびはんだバンプ5をICチ
ップ1の長辺方向の2辺に配置する例もある。By using the electrode pads 3, 4 and solder bumps 5 of the IC chip 1 on the four sides of the chip as shown in FIG. 1(b), high-density terminals can be formed. However, as shown in FIGS. 6(a) and 6(b), the electrode pads 3 and 4 and the solder bumps 5 are placed on the entire surface of the IC chip 1, or as shown in FIGS. 7(a) and 7(b), the electrode pads 3, There is also an example in which the solder bumps 4 and 5 are arranged on two sides of the IC chip 1 in the long side direction.
【0012】ICチップ1上のはんだバンプ5と回路基
板6の配線端子8とは相対する位置に設けられており、
図1(a) に示すようにICチップ1を回路基板6上
に乗せ、目視で位置合わせを行う。次にガラス基板6を
通じての赤外線スポットではんだバンプ5上をスキャン
するか、ラインスポットで1辺上のはんだバンプ5全部
に、あるいは4辺上のはんだバンプ5全部に照射するこ
とにより、はんだを加熱,リフローさせる。そのような
照射のために、赤外線ランプに予め反射板や遮蔽板がセ
ットされている。リフロー後凝固させることにより、は
んだ5がICチップ1の電極パッド3, 4と基板上の
配線端子8を接続する。The solder bumps 5 on the IC chip 1 and the wiring terminals 8 on the circuit board 6 are provided at opposing positions,
As shown in FIG. 1(a), an IC chip 1 is placed on a circuit board 6, and alignment is performed visually. Next, the solder is heated by scanning the solder bumps 5 with an infrared spot through the glass substrate 6, or by irradiating all the solder bumps 5 on one side or all the solder bumps 5 on four sides with a line spot. , Reflow. For such irradiation, a reflector or a shielding plate is set in advance on the infrared lamp. By solidifying after reflow, the solder 5 connects the electrode pads 3 and 4 of the IC chip 1 to the wiring terminals 8 on the substrate.
【0013】このあと、ICチップ1の信頼性を確保す
るため、ICチップ1と回路基板6の間の空隙にエポキ
シ系熱硬化樹脂9を注入し、150 〜200 ℃で熱
硬化して使用環境下の耐湿性を強化する。封止樹脂9と
しては、例えばポリエステルアクリレートあるいはエポ
キシアクリレート等のUV硬化樹脂のような光硬化重合
樹脂を充填し、光硬化してもよい。はんだ付け後のIC
チップ1とディスプレイ基板6との接続強度が100
〜200 g/mm2 であるが、封止樹脂9で空隙を
埋めることにより、接続強度はさらに増大する。[0013] After this, in order to ensure the reliability of the IC chip 1, an epoxy thermosetting resin 9 is injected into the gap between the IC chip 1 and the circuit board 6, and is heat cured at 150 to 200°C to maintain the usage environment. Strengthen the moisture resistance of the bottom. As the sealing resin 9, a photocurable polymer resin such as a UV cured resin such as polyester acrylate or epoxy acrylate may be filled and photocured. IC after soldering
The connection strength between chip 1 and display board 6 is 100
~200 g/mm2, but by filling the void with the sealing resin 9, the connection strength is further increased.
【0014】上記の実施例はELディスプレイ装置につ
いて述べたが、液晶パネルの場合には従来用いられてい
るITO電極配線, ITO/Cr電極配線あるいはI
TO/Mo電極配線の上あるいはその端部上にAl薄膜
を重ね、さらに端子部においてNi薄膜を重ねることに
より本発明を実施することができる。Although the above embodiments have been described with respect to an EL display device, in the case of a liquid crystal panel, conventionally used ITO electrode wiring, ITO/Cr electrode wiring or ITO electrode wiring may be used.
The present invention can be carried out by overlaying an Al thin film on the TO/Mo electrode wiring or its end, and further overlapping a Ni thin film at the terminal portion.
【0015】[0015]
【発明の効果】本発明によれば、はんだで接続される半
導体素子の電極端子および回路基板上の配線端子の双方
の表面層をいずれもAl層とその上のNi層で形成し、
素子, 基板間に充填される樹脂による接着強度と合わ
せて十分な接続強度を素子, 基板間に得ることができ
た。そして、はんだの両側に存在する端子構造が同じで
あるため、経時的変化による断線等の発生がない。さら
に、Al層としては従来より半導体素子に用いられてい
るAl電極あるいは回路基板に用いられているAl配線
が利用できるので、従来の多層積層構造の電極端子を用
いた場合に比してコストを低減した半導体装置を製造す
ることができた。According to the present invention, the surface layers of both the electrode terminals of the semiconductor element connected by solder and the wiring terminals on the circuit board are formed of an Al layer and a Ni layer thereon,
Combined with the adhesive strength of the resin filled between the element and the board, we were able to obtain sufficient connection strength between the element and the board. Furthermore, since the terminal structures on both sides of the solder are the same, there is no occurrence of wire breakage due to changes over time. Furthermore, as the Al layer, it is possible to use Al electrodes conventionally used in semiconductor devices or Al wiring used in circuit boards, so the cost is lower than when using conventional multilayer laminated structure electrode terminals. It was possible to manufacture a semiconductor device with reduced cost.
【図面の簡単な説明】[Brief explanation of drawings]
【図1】本発明の一実施例のELディスプレイ装置を示
し、そのうち(a) は要部断面図、(b) はICチ
ップの平面図FIG. 1 shows an EL display device according to an embodiment of the present invention, in which (a) is a sectional view of the main part, and (b) is a plan view of an IC chip.
【図2】従来のELディスプレイ装置を示し、そのうち
(a) は断面図、(b) はICチップの平面図[Fig. 2] Shows a conventional EL display device, of which (a) is a cross-sectional view and (b) is a plan view of an IC chip.
【図
3】本発明の一実施例のELディスプレイ装置に用いら
れるICチップの要部断面図FIG. 3 is a cross-sectional view of a main part of an IC chip used in an EL display device according to an embodiment of the present invention.
【図4】本発明の一実施例のELディスプレイ装置に用
いられるディスプレイ基板のデータ側電極配線端子部の
断面図FIG. 4 is a sectional view of a data side electrode wiring terminal portion of a display substrate used in an EL display device according to an embodiment of the present invention.
【図5】本発明の一実施例のELディスプレイ装置に用
いられるディスプレイ基板の走査側電極配線端子部の断
面図FIG. 5 is a cross-sectional view of a scanning side electrode wiring terminal portion of a display substrate used in an EL display device according to an embodiment of the present invention.
【図6】本発明の別の実施例で用いられるICチップを
示し、そのうち(a) は平面図、(b) は側面図FIG. 6 shows an IC chip used in another embodiment of the present invention, of which (a) is a plan view and (b) is a side view.
【
図7】本発明のさらに別の実施例で用いられるICチッ
プを示し、そのうち(a) は平面図、(b) は側面
図[
FIG. 7 shows an IC chip used in yet another embodiment of the present invention, of which (a) is a plan view and (b) is a side view.
1 ICチップ 2 絶縁保護膜 3 Al電極パッド 4 Ni電極パッド 5 はんだバンプ 6 ELディスプレイ基板 7 電極配線 8 配線端子 81 Al薄膜 82 Ni薄膜 9 封止樹脂 1 IC chip 2 Insulating protective film 3 Al electrode pad 4 Ni electrode pad 5 Solder bump 6 EL display board 7 Electrode wiring 8 Wiring terminal 81 Al thin film 82 Ni thin film 9 Sealing resin
Claims (3)
子がはんだ付けされ、半導体素子と回路基板の間の空隙
に樹脂が充填されるものにおいて、半導体素子および回
路基板の配線端子はいずれもはんだに接する側にニッケ
ル層を有し、かつそのニッケル層の下にアルミニウム層
を有することを特徴とする半導体装置。Claim 1: In a device in which the electrode terminals of the semiconductor element and the wiring terminals of the circuit board are soldered and the gap between the semiconductor element and the circuit board is filled with resin, both the wiring terminals of the semiconductor element and the circuit board are soldered. A semiconductor device comprising a nickel layer on a side in contact with solder and an aluminum layer below the nickel layer.
、回路基板がガラスよりなり、アルミニウム層と回路基
板の間にクロム層が介在する請求項1記載の半導体装置
。2. The semiconductor device according to claim 1, which is an electroluminescent display device, wherein the circuit board is made of glass, and a chromium layer is interposed between the aluminum layer and the circuit board.
ニッケル層、その下がアルミニウム層からなる電極端子
を形成し、その上にはんだからなるバンプを固着し、一
方回路基板上に表面がニッケル層、その下がアルミニウ
ム層からなる配線端子を形成し、その配線端子と前記は
んだバンプを接触させた状態で加熱してはんだを溶融さ
せたのち凝固させ、次いで半導体基板と回路基板の間の
空隙に樹脂を充填し、硬化させることを特徴とする半導
体装置の製造方法。3. An electrode terminal having a nickel layer on the surface and an aluminum layer below is formed on one side of the semiconductor substrate of the semiconductor element, and a bump made of solder is fixed on the electrode terminal, while the surface is on the circuit board. A wiring terminal consisting of a nickel layer and an aluminum layer underneath is formed, and the wiring terminal and the solder bump are heated in contact with each other to melt and solidify the solder. A method for manufacturing a semiconductor device, characterized by filling a void with resin and curing the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3079374A JPH04314337A (en) | 1991-04-12 | 1991-04-12 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3079374A JPH04314337A (en) | 1991-04-12 | 1991-04-12 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04314337A true JPH04314337A (en) | 1992-11-05 |
Family
ID=13688099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3079374A Pending JPH04314337A (en) | 1991-04-12 | 1991-04-12 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04314337A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751204A (en) * | 2012-07-16 | 2012-10-24 | 江阴长电先进封装有限公司 | Fanout type wafer level chip packaging method |
-
1991
- 1991-04-12 JP JP3079374A patent/JPH04314337A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751204A (en) * | 2012-07-16 | 2012-10-24 | 江阴长电先进封装有限公司 | Fanout type wafer level chip packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6551918B2 (en) | Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment | |
| JP3320979B2 (en) | How to mount a device directly on a device carrier | |
| US5016986A (en) | Display device having an improvement in insulating between conductors connected to electronic components | |
| US6537854B1 (en) | Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed | |
| US7087987B2 (en) | Tape circuit substrate and semiconductor chip package using the same | |
| US8497432B2 (en) | Electronic component mounting structure | |
| US6846699B2 (en) | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument | |
| JPH027180B2 (en) | ||
| US20040084206A1 (en) | Fine pad pitch organic circuit board for flip chip joints and board to board solder joints and method | |
| US20050040504A1 (en) | Low-cost flexible film package module and method of manufacturing the same | |
| JP3506393B2 (en) | Liquid crystal display device and its manufacturing method, printer and its manufacturing method | |
| JP2000090840A (en) | Electrode terminal leading out structure of plasma display panel | |
| US7508073B2 (en) | Wiring board, semiconductor device using the same, and method for manufacturing wiring board | |
| US7206056B2 (en) | Display device having a terminal that has a transparent film on top of a high resistance conductive film | |
| JPH06291165A (en) | Flip chip connection structure | |
| US6853086B1 (en) | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument | |
| WO1994024699A1 (en) | Semiconductor device | |
| KR20140020767A (en) | Chip-type electronic component and connecting structure | |
| JPH04314337A (en) | Semiconductor device and its manufacture | |
| CN1326432C (en) | High-density circuit board without pad design and manufacturing method thereof | |
| JP2636602B2 (en) | Semiconductor device | |
| JP2001118968A (en) | Semiconductor device | |
| JPH02185051A (en) | Tape carrier for double-side protective coat type tab | |
| JP2002083841A (en) | Mounting structure and method of manufacturing the same | |
| JP3601455B2 (en) | Liquid crystal display |