JPH0431443B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a bipolar CMOS (complementary metal oxide semiconductor) integrated circuit.
Relating to state driver circuits.

[Technical Background of the Invention] Conventionally, a CMOS type three-state driver circuit is configured as shown in FIG. 7, for example.
That is, the input data signal D is input to the inverter 11
After being inverted by , it is supplied to one input terminal of the NOR circuit 12 and the NAND circuit 13 . A control signal EN is supplied to the other input terminal of the NAND circuit 13, and this control signal EN is supplied to the other input terminal of the NOR circuit 12 via an inverter 14. The output of the NOR circuit 12 is the output of the inverter 1
5 and is supplied to the gate of a P-channel MOS transistor 16 whose one end is connected to the power supply _VDD . Further, the output of the NAND circuit 13 is inverted by the inverter 17, and the output of the NAND circuit 13 is inverted by the inverter 17.
The signal is supplied to the gate of an N-channel MOS transistor 18 connected between the other end of the MOS transistor 16 and the ground. Then, an output signal OUT is output from the connection point between the MOS transistors 16 and 18.
I'm starting to get more. In addition, the final stage above
The MOS transistors 16 and 18 have a ratio of W/L (W: gate width,
L: gate length) is set large.

Next, the operation in the above configuration will be explained. When the control signal EN is at a high level, the outputs of the NOR circuit 12 and the NAND circuit 13 are the same as a simple inverter for the input data signal D, so this circuit operates as a driver. On the other hand, when the control signal EN is at a low level, the NOR circuit 12 outputs a low level, so the MOS transistor 16 is turned off, and the NAND circuit 13 outputs a high level, so the MOS transistor 18 is also turned off, and the output terminal goes high. It becomes an impedance state.

Figures 8a and b and Figures 9a and b are, respectively,
This shows simulation results when the circuit shown in FIG. 7 is operated as a driver. here,
The gate length of the N-channel type MOS transistor that constitutes each circuit is L = 1.2 μm, and the gate length of the P-channel type MOS transistor is L = 1.2 μm.
The MOS transistor is L=1.5μm, and each MOS
The gate width W of the transistor is set as shown below.

Inverter 11, 14...Wp/Wn=4.5/3 NOR circuit 12...Wp/Wn=9/6 NAND circuit...Wp/Wn=6/4 Inverter 15...Wp/Wn=27/18 Inverter 17...Wp/Wn= 18/12 MOS transistor 16...Wp=202 MOS transistor 18...Wn=135 Note that Wp is the gate width of the P channel type MOS transistor, and Wn is the gate width of the N channel type MOS transistor. Further, the unit of each gate width W is μm.

When a capacitive load of 5.0 pF is connected to the output terminal of the circuit shown in FIG. 7, the output delay due to the driver circuit is 2.5 nS for the rising edge and 2.5 nS for the falling edge, as shown in FIG. 8b and 4b. It is 3.2nS. 8a and 9a show the current flowing through the MOS transistors 16 and 18, and it can be seen that the through current is very small. In FIGS. 8a and 8b and 9a and 9b, the dashed-dotted line 21 represents the waveform of the input data signal D, the dashed line 22 represents the waveform of the output signal OUT, the dashed-dotted line 23 represents the drain current of the MOS transistor 18, and the dashed line 16 represents the waveform of the output signal OUT. is the drain current of the MOS transistor 16.

[Problems with the background technology] However, in the conventional CMOS type three-state driver circuit described above, in order to obtain a large load drive capability, a MOS with a large gate width is required in the final stage.
This method requires a transistor, and the dimensions of other inverters, NOR circuits, NAND circuits, etc. must be set large accordingly, resulting in a disadvantage that the pattern area becomes large.

[Object of the Invention] This invention was made in view of the above-mentioned circumstances, and its object is to provide a 3-state driver circuit that can obtain a large driving capacity without increasing the pattern area. That's true.

[Summary of the Invention] That is, in order to achieve the above object, the present invention configures a 3-state driver circuit using bipolar transistors that can be used in bipolar CMOS embedded integrated circuits, and the collector a first bipolar transistor connected to a power supply, a second bipolar transistor whose collector is connected to the emitter of the first bipolar transistor and whose emitter is connected to a ground point, and a second bipolar transistor whose one end is connected to the collector of the first bipolar transistor and which transmits data. a first MOS transistor of a first conductivity type whose conduction is controlled by the output of a first inverter to which an input signal is supplied; and a first MOS transistor connected between the other end of the first MOS transistor and the base of the first bipolar transistor to which a control signal is supplied. The second
a second MOS transistor of a first conductivity type whose conduction is controlled by the output of the inverter; and a third MOS transistor of a second conductivity type connected between the base of the first bipolar transistor and the ground point and whose conductivity is controlled by the output of the first inverter. a fourth MOS transistor of a second conductivity type whose one end is connected to the collector of the second bipolar transistor and whose conduction is controlled by the output of the first inverter; the other end of the fourth MOS transistor and the second bipolar transistor. a fifth MOS transistor of a second conductivity type connected between the bases and whose conduction is controlled by a control signal;
A 3-state driver circuit is constituted by a sixth MOS transistor of a second conductivity type connected between the base of the bipolar transistor and the ground point and whose conduction is controlled by the potential of the connection point of the second and third MOS transistors, The output is obtained from the connection point between the first and second bipolar transistors.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The 3-state driver circuit shown in FIG. 1 is formed on a bipolar _CMSO integrated circuit. is connected. A second bipolar transistor 33 of NPN type is connected between the emitter of this bipolar transistor 32 and the ground point.
The collector and emitter of are connected respectively. Between the collector and base of the bipolar transistor 32, a P channel type (first conductivity type) first transistor,
Second MOS transistors 34 and 35 are connected in series.

The gate of the MOS transistor 34 is connected to the first inverter 3 to which the input data signal D is supplied.
The output terminal of the second MOS transistor 6 is connected to the gate of the second MOS transistor 35, and the control signal EN is supplied to the gate of the MOS transistor 35.
The output terminal of the inverter 37 is connected. Also,
An N-channel type (second conductivity type) transistor is connected between the base of the bipolar transistor 32 and the ground point.
3MOS transistor 38 is connected, and this MOS
The inverter 3 is connected to the gate of the transistor 38.
6 output ends are connected. On the other hand, there is N between the collector and base of the bipolar transistor 33.
Channel type fourth and fifth MOS transistors 39,
40 are connected in series. The output terminal of the inverter 36 is connected to the gate of the MOS transistor 39, and the control signal EN is supplied to the gate of the MOS transistor 40. A sixth N-channel MOS transistor 41 is connected between the base of the bipolar transistor 33 and the ground point.
is connected to the gate of the MOS transistor 41, and the connection point between the MOS transistors 35 and 38 is connected to the gate of the MOS transistor 41.

Next, the operation in the above configuration will be explained. When the control signal EN is at a high level, the conduction and discharge states of the bipolar transistors 32 and 33 are controlled by the level of the input data signal D. That is, when the input data signal D is at a high level, a low level signal is input to the gate of the MOS transistor 34, so that the MOS transistor 34 is turned on. At this time, due to the high level of the control signal EN, the MOS transistor 35
Since the low level signal is also supplied to the gate of the MOS transistor 35, the MOS transistor 35 is also turned on.
A current is supplied to the base of the bipolar transistor 32, turning the bipolar transistor 32 on. At this time, a low level is also applied to the MOS transistor 39, and the MOS transistor 39 is also applied with a low level.
9 is in the off state. Therefore, bipolar transistor 33 is turned off. When the load connected to the output terminal is charged due to the on state of the bipolar transistor 32 and the off state of the bipolar transistor 33, the output signal OUT becomes high level. As a result, the base potential of the bipolar transistor 33 increases, but since the MOS transistor 41 is in the on state, the off state of the bipolar transistor 33 is maintained.

On the other hand, when the input data signal D is at a low level, the MOS transistor 39 is in the on state (at this time, the MOS transistor 40 is in the control signal
(turned on by the high level of EN), a base current is supplied to the bipolar transistor 33, and the bipolar transistor 33 is turned on. At this time, the MOS transistor 34 is in an off state.
The MOS transistor 38 is turned on and the base of the bipolar transistor 32 is set to the ground potential, so the bipolar transistor 32 is completely turned off. Therefore, the charge of the load connected to the output terminal is discharged by the bipolar transistor 33.

Also, when the control signal EN is low level,
Since the MOS transistors 35 and 40 are turned off, the bipolar transistors 32 and 33 are turned off, and the output terminal is placed in a high impedance state.

Figures 2 a, b to 5 a, b are respectively,
2 shows a simulation result of the circuit shown in FIG. 1. FIG. Here, the gate length of each N-channel type MOS transistor is L=1.2 μm, and the gate length of each P-channel type MOS transistor is L=1.5 μm. In addition, the gate width W is as follows: MOS transistors 39, 40...Wn=10 MOS transistors 34, 35...Wp=10 MOS transistors 41...Wn=3 MOS transistors 38...Wn=6 Inverter 36...Wp/Wn=4.5/3 Inverter 37...Wp/Wn=10/10 In addition, β _F of bipolar transistors 32 and 33
=85.

When a capacitive load of 5.0 pF is connected to the output terminal, the current flowing through each bipolar transistor 32, 33 is as shown in Figures 2a and 3a, and the response waveform to the input waveform is as follows. It became as shown in Figure b and Figure 3b. The delay time for both rise and fall is 3.2nS. The through current at this time is the bipolar transistor 3
Since there is no period when 2 and 33 are in the on state at the same time, the amount is negligible as shown in the figure.

In addition, in FIGS. 2a, b and 3 a, b, the one-dot chain line 51 is the waveform of the input data signal D, the broken line 52 is the waveform of the output signal OUT, and the two-dot chain line 53 is the base potential of the bipolar transistor 33, the broken line 54 is the base potential of the bipolar transistor 32, and the dashed line 55 is the bipolar transistor 33.
The dotted line 56 is the emitter current of the bipolar transistor 32.

4a, b and 5a, b are control signals
The simulation results are shown when EN is set to low level. What is shown here is the current waveform and response waveform when an output terminal set to high impedance is driven by another inverter. 4a and 4b show the case where the input data signal D is at a low level, and FIGS. 5a and 5b show the case where the input data signal D is at a high level. From these figures, it is confirmed that the output terminal is high impedance.

In addition, in FIGS. 4a and 4b and FIGS. 5a and 5b, the one-dot chain line 61 is the input waveform of the inverter that drives the output terminal, the broken line 62 is the waveform of the output terminal, and the two-dot chain line 63 is the base potential of the bipolar transistor 33. , a broken line 64 is the base potential of the bipolar transistor 32, a dashed line 65 is the emitter current of the bipolar transistor 33, and a broken line 66 is the emitter current of the bipolar transistor 32.

According to such a configuration, bipolar transistors 32 and 33 having a large driving capacity are provided in the output stage.
, a large driving capacity can be obtained with a relatively small pattern area. Furthermore, whereas the circuit shown in FIG. 7 requires 18 MOS transistors, the circuit shown in FIG. 1 requires only 12 transistors. Moreover, since the dimensions of each individual transistor can be small, the pattern area of the entire circuit can be reduced to about 1/2.

FIG. 6 shows another embodiment of the invention.
In the figure, the same components as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, the seventh and eighth N-channel type MOS transistors 42 and 4 are connected between the bases of the bipolar transistors 32 and 33 in FIG. 1 and the ground point, respectively.
3, these MOS transistors 4
2 and 43 are controlled to be conductive by the output of an inverter 37 to which a control signal EN is supplied.

According to such a configuration, when the control signal EN is at a low level, these MOS transistors 42 and 43
turns on, and bipolar transistor 3
By connecting the bases of Nos. 2 and 33 to the ground point, the off state can be ensured, and the output terminal can be set to a complete high impedance state.

[Effects of the Invention] As explained above, according to the present invention, a three-state drive circuit that can obtain a large driving capability without increasing the pattern area can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a 3-state drive circuit according to an embodiment of the present invention, FIGS. 2 to 5 are waveforms for explaining the operation of the circuit in FIG. 1, and FIG. A circuit diagram for explaining another embodiment of the present invention, FIG. 7 is a diagram showing a conventional three-state driver circuit, and FIGS. 8 and 9 each explain the operation of the circuit shown in FIG. 7. FIG. 32, 33...Bipolar transistor, 3
4, 35, 38, 39, 40, 41, 42, 43
...MOS transistor, 36,37...inverter, V _DD ...power supply, D...input data signal,
EN...Control signal, OUT...Output signal.

Claims (1)

[Scope of Claims] 1: a first bipolar transistor whose collector is connected to a power supply; a second bipolar transistor whose collector is connected to the emitter of the first bipolar transistor and whose emitter is connected to a ground point; a first MOS transistor of a first conductivity type whose conduction is controlled by the output of a first inverter whose one end is connected to the collector of the transistor and which is supplied with an input data signal; the other end of this first MOS transistor and the base of the first bipolar transistor; a second connected between and supplied with a control signal;
a second MOS transistor of a first conductivity type whose conduction is controlled by the output of the inverter; and a third MOS transistor of the second conductivity type connected between the base of the first bipolar transistor and the ground point whose conduction is controlled by the output of the first inverter. a fourth MOS transistor of a second conductivity type whose one end is connected to the collector of the second bipolar transistor and whose conduction is controlled by the output of the first inverter; a fifth MOS transistor of a second conductivity type connected between the bases and whose conduction is controlled by a control signal;
a sixth MOS transistor of a second conductivity type connected between the base of the bipolar transistor and a ground point and whose conduction is controlled by the potential of the connection point of the second and third MOS transistors; A 3-state driver circuit characterized by obtaining an output from a connection point. 2 a seventh MOS transistor of a second conductivity type connected between the base of the first bipolar transistor and a ground point and whose conduction is controlled by the output of the second inverter; and a seventh MOS transistor connected between the base of the second bipolar transistor and the ground point. 2. The three-state driver circuit according to claim 1, further comprising an eighth MOS transistor of a second conductivity type whose conduction is controlled by the output of the second inverter.