JPH04315211A - Computer system - Google Patents

Abstract

PURPOSE:To execute the initializing sequence of the H/W (hardware) of the system by a coprocessor while separating it from an application due to a main processor, to prevent a fault caused by the setting error of an initial value and to facilitate recovery from a fault processing or the fault without destroying the initial set value even when the main processor runs away. CONSTITUTION:Separately from a main processor 1 to execute the application, a coprocessor 5 is provided with an H/W configuration processing part 503 to execute the H/W initializing sequence, and an H/W configuration register 4 to set H/W configuration data to initialize a peripheral device 2 is connected to the coprocessor 5 so as to enable access from the coprocessor 5 and is not connected to the main processor 1, on the other hand, so as to disable access from the main processor 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system such as a microprocessor application system, and more particularly, to a computer system that initializes hardware at the time of system reset independently of an application by a main processor. .

0002

2. Description of the Related Art Conventionally, when initializing computer system hardware (hereinafter abbreviated as H/W), a user refers to a system manual and sets dip switches or jumpers to initial values, or Starts the initialization routine stored in the main processor
It was necessary to initialize W. Figure 10 is JP-A-63-1
1 is a block diagram of a conventional computer system disclosed in Publication No. 54705. In the figure, 1 is the main processor that controls the central processing of the system, and main processor 1
Peripheral devices 2 such as memories and peripheral LSIs are connected to the address bus and data bus. The main processor 1 further includes an address decoding section 36 and an H/H/100 decoder that output select signals for peripheral devices including a memory map setting register 46 and a ROM 56, which will be described later.
Memory map setting register 4 for initializing W, that is, for memory configuration to set the memory map.
6 and a ROM 56 that stores an initialization routine and initial values for H/W configuration when the power is turned on.
is connected.

Next, an initialization method using a conventional computer system will be explained based on a flowchart shown in FIG. When the power is turned on, the main processor 1 starts up and enters a reset state (S11). When the reset state is released, the main processor 1 accesses the ROM 56 and starts the initialization routine stored in the ROM 56 (S12). Through the initialization routine, the main processor 1 reads the initial setting values stored in the ROM 56 and sets them in the memory map setting register 46 (
S13). This setting operation (H/W configuration) is called H/W initialization. The main processor 1 and peripheral devices 2 are configured according to the initial setting values set in the memory map setting register 46 (S14). However, the ROM 56 is allocated to an area that is immediately accessed by the main processor 1 after the reset is released, and its address is fixed, so there is no need to set an address map.

[0004] When the H/W initialization operation is completed, the main processor 1 becomes ready to execute the application (S15). That is, the address decoder 36 decodes the address from the main processor 1 according to the information stored in the memory map setting register 46, and the chip select signal can be output to the peripheral device 2. Further, when the user sets a dip switch or jumper to an initial value, the setting is done before turning on the power. In this case, among the operations described above, H/W configuration (S13) for setting a memory map is not necessary.

[0005]

[Problems to be Solved by the Invention] As described above, in conventional computer systems, the user either refers to the system manual and sets dip switches and jumpers to initial values, or Since it is necessary to start the configuration routine and initialize the H/W, failures are likely to occur due to incorrect settings of dip switches and jumpers by the user, and the main processor cannot access the memory map setting registers. Therefore, if a failure occurs in the application and the main processor goes out of control, there is a risk that the H/W setting values will be changed, making it difficult to handle the failure or recover from the failure. The present invention has been made to solve these problems, and includes providing a coprocessor that executes the initialization sequence and also providing means for making it impossible for the main processor to access the initial value setting register. It is an object of the present invention to provide a computer system that can avoid failures due to setting errors during initialization by a user, and can easily handle failures or recover from failures even if the main processor goes out of control.

[0006]

[Means for Solving the Problems] The computer system of the present invention is provided with a coprocessor that operates independently of a main processor that executes an application, and this coprocessor handles the initialization sequence of H/W. It is characterized in that the main processor cannot access the initial value setting registers while executing the program.

[0007]

[Operation] In the computer system of the present invention, the coprocessor that operates independently of the main processor initializes the system's H/W by setting the initial value in the register, while the main processor that executes the application Since this register cannot be accessed, the register settings will not be destroyed even if the main processor goes out of control due to an application failure.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to figures showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a first embodiment of a computer system according to the present invention. In the figure, 1 is a main processor that controls the central processing of the system and executes applications.
A peripheral device 2 such as an SI and a peripheral device control section 3 that outputs control commands to the peripheral device 2 are connected. In addition, 5 in the figure is a coprocessor that performs a reset sequence and H/W configuration when the power is turned on, and the coprocessor 5 controls all the systems including the coprocessor 5 according to a cold reset (CRST) signal given from the system. The CRST processing unit 501 initializes the H/W, and the main processor 1 and peripheral device control unit 3 except for the coprocessor 5 and the H/W configuration register 4 according to the output of the warm reset (WRST) signal from the coprocessor 5. The WRST processing unit 502 to be initialized and the H of the peripheral device 2
/W configuration processing unit 503 that executes H/W configuration. Coprocessor 5
is the H/W configuration register 4 in which the initial value of the H/W is set via the address bus and data bus.
connected to. H/W configuration register 4 is connected to peripheral device control section 3 via a bus. That is, the H/W configuration register 4 is not connected to the main processor 1, and only the coprocessor 5 can access the H/W configuration register 4, and the main processor 1 cannot access it. .

[0009] The H/
The operation of W initialization will be explained based on the flowchart shown in FIG. The computer system is CRST and W
It is initialized by two systems of reset signals of RST. When the power is turned on, the coprocessor 5 enters the CRST state by inputting the CRST signal from the system (S21). CR
The CRST processing unit 501 is activated by the release of ST, and initializes the coprocessor 5 itself (S22). CRST
When the processing is completed, the coprocessor 5 executes the WRST processing unit 5
2 (S23), and outputs the WRST signal to the main processor 1 and peripheral device control unit 3 to initialize the main processor 1 and peripheral device control unit 3 (S24).
. The coprocessor 5 starts up the H/W configuration processing section 53 while continuously outputting the WRST signal (
S25), accesses the H/W configuration register 4 and sets the initial value of the peripheral device 2 (S25).
6). That is, with this setting, the main processor 1 transmits H/W information necessary for accessing the peripheral device 2.
It is possible to access the peripheral device 2 according to the settings obtained from the W configuration register 4.

After the settings are completed, the coprocessor 5 performs WR for the main processor 1 and the peripheral device control unit 3.
The ST is released (S27), and the main processor 1 executes an application including access to the peripheral device 2 (S28).

[0011] Furthermore, even if a failure occurs in the application of the main processor 1 and the main processor 1 goes out of control, the main processor 1 cannot access the H/W configuration register 4. will not be destroyed. Coprocessor 5
For example, when restarting the main processor 1 after detecting a runaway in the main processor 1, the WRST signal is output to the main processor 1 to perform a reset operation, but at this time the CRST signal is not generated. H
/W There is no need to perform the initial setting for the configuration register 4 again.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the computer system according to the present invention. In this embodiment, a memory map setting register for address decoding is used as the H/W configuration register in the first embodiment. In the drawings, the same or equivalent parts as in the first embodiment are given the same numbers, and the explanation thereof will be omitted. In the figure, 41 is a memory map setting register for initializing the H/W, that is, for memory configuration (setting a memory map). The memory map setting register 41 is connected to an address decoding section 31 that outputs a select signal (chip select) to the peripheral device 2 based on address data given from the main processor 1.

The memory map setting register 41 is not connected to the main processor 1, and only the coprocessor 5 can access the memory map setting register 41, and the main processor 1 cannot access it. Note that the initialization operation of the H/W and the processing operation when the main processor 1 runs out of control are the same as in the first embodiment.
A similar effect can be obtained.

FIG. 3 is a block diagram showing the configuration of a third embodiment of a computer system according to the present invention. In this embodiment, a watchdog timer (hereinafter referred to as WDT) is used as the H/W configuration register in the first embodiment.
(abbreviated as ) is used. In the drawings, the same or equivalent parts as in the first embodiment are given the same numbers, and the explanation thereof will be omitted. In the figure, 6 is a watchdog timer (hereinafter abbreviated as WDT) that monitors the runaway of the application of the main processor 1, and 42 is connected to the WDT 6, and is used to set whether to enable or disable the operation of the WDT 6. and a WDT setting register for setting the monitoring time of WDT6.

The main processor 1 is not connected to the WDT setting register 42, and only the coprocessor 5 is connected to the WDT setting register 42.
The configuration is such that the setting register 42 can be accessed, but the main processor 1 cannot. Also,
Error information at the time of a WDT error is stored in the WDT setting register 42.
It can be read by the coprocessor 5. In addition, the initialization operation of H/W and the main processor 1
The processing operation at the time of runaway is the same as in the first embodiment, and the same effects as in the first embodiment can be obtained.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of a computer system according to the present invention. In this embodiment, a register for setting the timeout time of the READY signal returned from the peripheral device to the main processor is used as the H/W configuration register in the first embodiment. In the drawings, the same or equivalent parts as in the first embodiment are given the same numbers, and the explanation thereof will be omitted. 7 in the figure is READ, which monitors the timeout of the READY signal returned from the peripheral device 2 to the main processor 1.
The Y timeout monitoring unit 43 is connected to the READY timeout monitoring unit 7, and has a READY timeout setting register for setting whether to enable or disable the operation of the READY timeout monitoring unit 7 and setting the READY timeout time. It is.

READY timeout setting register 43
is not connected to the main processor 1, and only the coprocessor 5 can access the READY timeout setting register 43, and the main processor 1 cannot access it. Further, error information in the case of a READY timeout error is stored in the READY timeout setting register 43 and can be read by the coprocessor 5. Note that the initialization operation of the H/W and the processing operation when the main processor 1 runs out of control are the same as in the first embodiment, and the same effects as in the first embodiment can be obtained.

FIG. 5 is a block diagram showing the configuration of a fifth embodiment of a computer system according to the present invention. In this embodiment, a register for setting the cache memory area, size, etc. is used as the H/W configuration register in the first embodiment. In the drawings, the same or equivalent parts as in the first embodiment are given the same numbers, and the explanation thereof will be omitted. In the figure, 8 is a cache memory, 9 is a cache control unit that controls the cache memory, and 44 is connected to the cache control unit 9, and is used to set whether to enable or disable the operation of the cache control unit 9. This is a cache setting register for setting the area and size of the cache memory 8.

The cache setting register 44 is not connected to the main processor 1, and only the coprocessor 5 can access the cache setting register 44, and the main processor 1 cannot access it. The initialization operation of the H/W and the processing operation when the main processor 1 runs out of control are the same as in the first embodiment, and the same effects as in the first embodiment can be obtained.

FIG. 6 is a block diagram showing the configuration of a sixth embodiment of a computer system according to the present invention. In the drawings, the same or equivalent parts as in the first embodiment are given the same numbers, and the explanation thereof will be omitted. In the figure, 111 to 11n represent H/W1 such as the main processor 1, memory, and setting registers.
2n and a coprocessor 5n that performs a reset sequence when the power is turned on and H/W configuration. The coprocessors 51 to 5n are CR
It includes an ST processing section, a WRST processing section, and a H/W configuration processing section. Further, reference numeral 13 in the figure includes a system initialization management program 13A that manages H/W initial values for each of the IC cards 111 to 11n, and a coprocessor 5.
The initialization management card 13 is a system initialization management card that issues initialization requests to the IC cards 111 to 11n connected via the bus 10.
Manages initialization of W121 to W12n. Further, inside the IC cards 111 to 11n, the H/W initial value setting register is not connected to the main processor 1, and only the coprocessors 51 to 5n can access the setting register. The configuration is such that the setting register cannot be accessed.

Next, regarding the H/W initialization operation according to the sixth embodiment, the system initialization management card 1 shown in FIG.
The following description will be made based on a flowchart showing the initialization request procedure according to No. 3 and a flowchart showing the initialization procedure by the coprocessors 51 to 5n built in the IC cards 111 to 11n shown in FIG. When the power is turned on, the system initialization management program 13A is executed (S31), and the IC is transferred from the system initialization management card 13 via the bus 10.
H/ to coprocessors 51 to 5n of cards 111 to 11n.
A request to initialize W is notified (S32). At this time, I
The C cards 111 to 11n receive the same CRST signal input (S4) as in the first embodiment by the coprocessors 51 to 5n.
After completing the reset sequence from 1) to outputting the WRST signal (S44), the system waits for a H/W initialization request from the system initialization management card 13 (S45). The coprocessors 51 to 5n are the system initialization management card 13
When the H/W initialization request is received from the H/W configuration section (S46), the
Initial settings are made for the corresponding H/Ws 121 to 12n (S47). When WRST is released (S48
), the main processor 1 becomes able to execute the application (S49). Note that the processing operation when the main processor 1 runs out of control inside the IC cards 111 to 11n is the same as in the above-described embodiment.

[0022] In the multiprocessor system as described above, each IC card 111 is
H/W provided in the coprocessors 51 to 5n of ~11n
Even if the configuration processing unit is not changed, the system initialization data is managed by the system initialization management program 13A of the system initialization management card 13, and when changes are made, each Since the configuration is such that the changed H/W initialization data is notified to the coprocessor of the IC card, it is possible to easily manage H/W initialization suitable for the IC card.

[0023]

As described above, the computer system according to the present invention initializes the system H/W by a coprocessor that operates independently of the main processor during the reset period of the main processor, and
By making it impossible for the main processor to access the initial value setting register, it is possible to avoid failures due to incorrect settings of dip switches, jumpers, etc., and has the excellent effect of preventing serious failures due to runaway of the main processor. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a computer system according to the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of a computer system according to the present invention.

FIG. 3 is a block diagram showing the configuration of a third embodiment of a computer system according to the present invention.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of a computer system according to the present invention.

FIG. 5 is a block diagram showing the configuration of a fifth embodiment of a computer system according to the present invention.

FIG. 6 is a block diagram showing the configuration of a sixth embodiment of a computer system according to the present invention.

FIG. 7 is a flowchart illustrating the operation of H/W initialization according to the first to fifth embodiments of the computer system according to the present invention.

FIG. 8 is a flowchart illustrating the H/W initialization operation according to the sixth embodiment of the computer system according to the present invention.

FIG. 9 is a flowchart illustrating the operation of H/W initialization according to the sixth embodiment of the computer system according to the present invention.

FIG. 10 is a block diagram showing the configuration of a conventional computer system.

FIG. 11 is a flowchart illustrating the operation of H/W initialization by a conventional computer system.

[Explanation of symbols]

1 Main processor 2 Peripheral device 3 Peripheral device control section 4 H/W configuration register 5 Coprocessor 6 WDT 7 READY monitoring section 8 Cache memory 9 Cache control section 10
Bus 13 System initialization management card 13A System initialization management program 22 Peripheral device control section 41 Memory map setting register 4
2 WDT setting register 43 READY timeout setting register 44
Cache setting register 51 ~ 5n Coprocessor 111 ~ 11n IC card 121 ~ 12n H/W 501 CRST processing section 502 WRST processing section

Claims (1)

[Claims] Claims: 1. A computer system for initializing component hardware so that a main processor can access peripheral devices and execute applications, comprising: means for setting initial values of the hardware; a coprocessor that operates independently of the coprocessor, a register that stores initial values set by the coprocessor, means for requesting the coprocessor to initialize hardware, and means for disabling access to the register by the main processor. A computer system comprising: