JPH04317358A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a self-aligned contact structure.

0002

2. Description of the Related Art FIG. 16 shows a stacked capacitor type DRAM in the manufacturing process according to a conventional example of the present invention. A DRAM memory cell is composed of a transistor 11 and a capacitor 12, and is a stacked capacitor type DR.
In AM, one source/drain diffusion layer 13a of the transistor 11 and the polycrystalline Si film 14, which is a storage node of the capacitor 12, are in contact through a contact hole 15a.

In such a DRAM, the transistor 11
The memory cell area is reduced by a self-aligned contact structure in which a sidewall made of SiO2 film 17 is formed on the side of the polycide film 16, which is a gate wiring, that is, a word line, and at the same time, a contact hole 15a is formed in a self-aligned manner. ing.

0004

However, in the self-aligned contact structure, the polycide film 16 and the polycrystalline Si film 1
4, it is necessary to provide an offset SiO2 film 21 on the polycide film 16.

For this reason, if the polycrystalline Si film 14 has a large step difference in the underlying layer and attempts to pattern the polycrystalline Si film 14 using only anisotropic etching, the so-called stringer 14a remaining after etching will be removed from the step portion between the polycide films 16. This is likely to occur. As a result, there is a possibility that the polycrystalline Si films 14 of adjacent memory cells may be short-circuited via this stringer 14a.

On the other hand, when the polycrystalline Si film 14 is isotropically etched to remove the stringer 14a, an undercut portion 14b is created under the resist 22. Moreover, the thicker the polycrystalline Si film 14 is made to increase the memory cell capacity, the larger the undercut portion 14b becomes. Therefore, even if the thickness of the polycrystalline Si film 14 is increased, it is difficult to increase the memory cell capacity.

Furthermore, in order to flatten the stepped portion between the polycide films 16, a low melting point glass film (not shown) such as a BPSG film is used in place of the SiO2 film 17, and this low melting point glass film is allowed to flow. , source/drain diffusion layer 13
The low melting point glass film becomes thicker on the surface a, making it impossible to form the contact hole 15a in a self-aligned manner.

In other words, in one conventional example as described above, it is difficult to achieve both self-aligned contact and fine processing of upper layer wiring. Therefore, even if a DRAM is manufactured using this conventional example,
It is difficult to secure a large memory cell capacity with a small memory cell area, and as a result, it is difficult to achieve high integration.

[0009]

[Means for Solving the Problems] In the method for manufacturing a semiconductor device according to the present invention, in the upper layer of patterned wiring 16,
an interlayer insulating film 31 including at least a low melting point glass film 31;
17, a step of applying heat-resistant treatment only to the interlayer insulating films 31, 17 in the contact portion, a step of applying heat treatment to the interlayer insulating films 31, 17 after the heat-resistant treatment, and a step of applying heat treatment to the interlayer insulating films 31, 17 after the heat treatment. The entire surface of the interlayer insulating films 31 and 17 is etched back to form the wiring 1 at the contact portion.
The method includes a step of leaving the interlayer insulating film 17 only on the sides of the wafer 6.

0010

[Operation] In the method of manufacturing a semiconductor device according to the present invention, heat-resistant treatment is applied only to the contact portions of the interlayer insulating films 31 and 17, so that the heat treatment after the heat-resistant treatment results in interlayer insulation in areas other than the contact portions. It is possible to cause the low melting point glass film 31 of the films 31 and 17 to flow, and to prevent the interlayer insulating films 31 and 17 in the contact portion from flowing.

Therefore, it is possible to flatten the stepped portion in areas other than the contact area, and at the same time, by etching back the entire surface of the interlayer insulating films 31 and 17 after heat treatment, the interlayer insulating film is formed only on the sides of the wiring 16 in the contact area. By leaving the film 17, the contact hole 15a can be formed in a self-aligned manner.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS First to third embodiments of the present invention applied to the manufacture of a stacked capacitor type DRAM will be described below with reference to FIGS. 1 to 15.

1 to 6 show a first embodiment. In this first embodiment, as shown in FIG.
2 Form the film 26. Then, a polycide film 16 and an offset SiO2 film 21 are sequentially deposited over the entire surface by CVD. Note that a single layer polycrystalline Si film may be used instead of the polycide film 16.

Thereafter, using a resist (not shown) as a mask, the SiO2 film 21 and the polycide film 16 are simultaneously patterned to form a word line, and the word line and S
Using the iO2 film 24 as a mask, an N-type impurity 27 is added to the active region 25 to form a source/drain diffusion layer.
ion implantation.

Then, by the CVD method, a SiO2 film 17 with a thickness of several thousand Å and a BPSG film 31 with a thickness of several hundred to several thousand Å are sequentially deposited over the entire surface. Note that by changing the source gas midway through, the SiO2 film 17 and BPS
The G film 31 may also be deposited continuously. Also, BPS
Instead of the G film 31, another low melting point glass film such as an AsSG film may be used. Furthermore, the SiO2 film 17 is not necessarily necessary, and only the BPSG film 31 may be used.

Next, as shown in FIGS. 2 and 6, the resist 32 is patterned. This pattern generally consists of a source/drain diffusion layer 1 that contacts the storage node.
The resist 32 is opened above 3a and remains in regions 33 and 34.

Although the regions 33 and 34 have stepped portions formed by the polycide film 16 and the like, it is necessary to flatten the polycrystalline Si film 14 so as not to leave etching residue during patterning of the storage node. It is an area.

Thereafter, using the resist 32 as a mask, fluorine 35 is ion-implanted into the BPSG film 31 at a dose of 10 15 cm -2 or more. As a result, the fluidity of the BPSG film 31 decreases in the portion where fluorine 35 is ion-implanted.

Next, after removing the resist 32, N2
Heat treatment is applied at a temperature of 850° C. or higher in an atmosphere. Then, as shown in FIG. 3, the BPSG film 31 flows, except for the portion where the fluorine 35 has been ion-implanted, and the step portion between the polycide films 16 is flattened. Note that the impurity 27 ion-implanted into the active region 25 is also subjected to heat treatment, and source/drain diffusion layers 13a and 13b are formed in the active region 25.

Next, the BPSG film 31 and the SiO2 film 1
By performing RIE anisotropically on the entire surface of 7, as shown in FIG. 4, the polycide film 16 and SiO2 film 21 side are SiO2 only in the part
A side wall consisting of the membrane 17 and the like is formed.

Therefore, at this time, the surface of the source/drain diffusion layer 13a is exposed, and the contact hole 15a is formed in a self-aligned manner. However, the area where the BPSG film 31 has been planarized by the flow remains flat even when the contact hole 15a is formed.

Thereafter, an interlayer insulating film 36, which is a two-layer film of a PSG film and a SiN film, is deposited by the CVD method, and a resist (not shown) is used as a mask to form a part of the interlayer insulating film 36 above the contact hole 15a. Contact hole 37 only in part
When the contact hole 15a is opened, only the contact hole 15a for the storage node is again formed in a self-aligned manner.

Note that the reason why the interlayer insulating film 36 is used is to increase the thickness of the interlayer insulating film in a portion other than on the source/drain diffusion layer 13a. Therefore, if these are not necessary, the interlayer insulating film 36 is not necessarily necessary.

Thereafter, in this state, a polycrystalline Si film 14 is deposited to a thickness necessary as a storage node by low pressure CVD, and after doping this polycrystalline Si film 14 with N-type impurities at a high concentration, The crystalline Si film 14 is processed into a pattern of storage nodes.

Next, as shown in FIG. 5, the SiN film and the SiO
A capacitor insulating film 41, which is a two-layer film with a second film, is formed on the surface of the polycrystalline Si film 14, and a plate is formed by depositing a polycrystalline Si film 42, implanting impurity ions into the polycrystalline Si film 42, and patterning it. Form an electrode.

[0026] Then, an interlayer insulating film 4 such as a BPSG film is formed.
3 is deposited and flowed to form source/drain diffusion layer 1.
After a contact hole 15b for a bit line reaching 3b is opened in an interlayer insulating film 43 or the like, a bit line is formed by depositing and patterning a polycide film 44.

Further, an interlayer insulating film 45 such as a BPSG film is deposited and flowed, and an Al wiring 46 is formed on this interlayer insulating film 45 to form a stacked capacitor type DR.
Complete AM.

According to the first embodiment as described above, the stepped portion between the polycide films 16 in the regions 33 and 34 is flattened by the BPSG film 31 without impairing the self-aligned formation of the contact hole 15a for the storage node. be converted into

Therefore, even if the thickness of the polycrystalline Si film 14 is increased and the polycrystalline Si film 14 is patterned only by anisotropic etching, storage nodes cannot be connected to each other through the stringers of the polycrystalline Si film 14. will not be short-circuited. Therefore, a large memory cell capacity can be secured with a small memory cell area, and a highly integrated DRAM can be manufactured.

FIGS. 7 to 11 show a second embodiment. In this second embodiment as well, as shown in FIG.
Up to the deposition of , substantially the same steps as in the first embodiment described above are performed.

However, in this second embodiment, as shown in FIG. 8, the non-fluid film 47, which is a two-layer film of a polycrystalline Si film and a Si3 N4 film, is then deposited in B by low pressure CVD.
It is formed on the surface of the PSG film 31. Then, a resist 48 is processed into a pattern covering the source/drain diffusion layer 13a like a storage node, and using this resist 48 as a mask, the non-fluid film 47 is patterned by etching using a gas such as SF6.

Next, after removing the resist 48, N2
Heat treatment is applied at a temperature of about 800 to 900°C in an atmosphere. Then, as shown in FIG. 9, the BPSG film 31 flows except for the portion covered by the non-fluid film 47, and the step portion between the polycide films 16 is flattened.

Next, by anisotropically RIEing the entire surfaces of the non-flowable film 47, the BPSG film 31, and the SiO2 film 17, as shown in FIG. source/drain diffusion layer 1
On 3a, side walls made of SiO2 film 17 and the like are formed only on the sides of polycide film 16 and SiO2 film 21.

Therefore, at this time, the surface of the source/drain diffusion layer 13a is exposed, and the contact hole 15a is formed in a self-aligned manner. However, the area where the BPSG film 31 has been planarized by the flow remains flat even when the contact hole 15a is formed.

After that, as shown in FIG.
A stacked capacitor type DRAM is completed by performing substantially the same steps as in the embodiment. Such a second embodiment can also provide the same effects as the first embodiment.

FIGS. 12 to 15 show a third embodiment. In this third embodiment as well, the BPSG film 3 as shown in FIG.
1 and patterning of the resist 32 as shown in FIG. 13, substantially the same steps as in the first embodiment described above are performed.

However, in this third embodiment, the source/drain diffusion layer 13a is etched by etching only the BPSG film 31 using the resist 32 as a mask.
The upper BPSG film 31 is removed, and the BPSG film 31 is left in other areas to be planarized.

Next, after removing the resist 32, N2
Heat treatment is applied at a temperature of about 800 to 900°C in an atmosphere. Then, as shown in FIG. 14, the remaining BPSG film 31 flows, and the stepped portion between the polycide films 16 in the region covered with the resist 32 is flattened.

Next, the BPSG film 31 and the SiO2 film 1
By performing RIE anisotropically on the entire surface of the BPSG film 7, as shown in FIG. SiO2 only in the part
A side wall consisting of the membrane 17 and the like is formed.

Therefore, at this time, the surface of the source/drain diffusion layer 13a is exposed, and the contact hole 15a is formed in a self-aligned manner. However, the region where the BPSG film 31 has been planarized by the flow remains flat even when the contact 15a is formed.

After that, as shown in FIG.
A stacked capacitor type DRAM is completed by performing substantially the same steps as in the embodiment. Even in such a third embodiment, the same effects as in the first embodiment can be achieved.

[0042]

[Effects of the Invention] In the method for manufacturing a semiconductor device according to the present invention, a contact hole can be formed in a self-aligned manner in a contact part, and at the same time, a stepped part can be flattened in a part other than the contact part. Both contact and upper layer wiring microfabrication are possible at the same time.

[Brief explanation of drawings]

FIG. 1 shows a part of a first embodiment of the present invention, and FIG.
FIG. 2 is a side sectional view of a portion taken along line A-A of FIG.

FIG. 2 is a side sectional view showing a step following FIG. 1;

FIG. 3 is a side sectional view showing a step following FIG. 2;

FIG. 4 is a side sectional view showing a step following FIG. 3;

FIG. 5 is a side sectional view showing a step following FIG. 4;

FIG. 6 is a plan view of a DRAM manufactured according to the first embodiment.

FIG. 7 is a side sectional view showing a part of a second embodiment of the present invention.

8 is a side sectional view showing a step following FIG. 7. FIG.

9 is a side sectional view showing a step following FIG. 8. FIG.

FIG. 10 is a side sectional view showing a step following FIG. 9;

FIG. 11 is a side sectional view showing a step following FIG. 10;

FIG. 12 is a side sectional view showing a part of a third embodiment of the present invention.

FIG. 13 is a side sectional view showing a step following FIG. 12;

FIG. 14 is a side sectional view showing a step following FIG. 13;

FIG. 15 is a side sectional view showing a step following FIG. 14;

FIG. 16 is a side sectional view showing a conventional example of the present invention.

[Explanation of symbols]

15a Contact hole 16 Polycide film 17 SiO2 film 31 BPSG film

Claims (4)

[Claims] 1. A step of forming an interlayer insulating film containing at least a low melting point glass film on the upper layer of the patterned wiring, a step of applying heat resistance treatment only to the interlayer insulating film in the contact portion, and a step of applying heat resistance treatment to the interlayer insulation film after the heat resistance treatment. A semiconductor device comprising the steps of: applying heat treatment to the interlayer insulating film; and etching back the entire surface of the interlayer insulating film after the heat treatment to leave the interlayer insulating film only on the sides of the wiring at the contact portion. manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat resistance treatment is performed by introducing fluorine into the low melting point glass film in the contact portion. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the heat resistance treatment is performed by forming a non-fluid film on the low melting point glass film in the contact portion. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the heat resistance treatment is performed by removing the low melting point glass film in the contact portion.