JPH04318959A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04318959A
JPH04318959A JP3085164A JP8516491A JPH04318959A JP H04318959 A JPH04318959 A JP H04318959A JP 3085164 A JP3085164 A JP 3085164A JP 8516491 A JP8516491 A JP 8516491A JP H04318959 A JPH04318959 A JP H04318959A
Authority
JP
Japan
Prior art keywords
sealing resin
leads
lead
semiconductor chip
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3085164A
Other languages
Japanese (ja)
Inventor
Tatsuto Nishihara
達人 西原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3085164A priority Critical patent/JPH04318959A/en
Publication of JPH04318959A publication Critical patent/JPH04318959A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor device where a distance from a semiconductor chip at the time of mounting on a circuit board up to a soldered part of the circuit board is shortened in order to prevent a loss due to a lead. CONSTITUTION:When a semiconductor chip 1 mounted on a lead 2 is resin-sealed by sealing resin 6, a lead part to be housed inside the sealing resin 6 is so formed that the leads 2 to 4 to be taken out from the sealing resin 6 can be taken out in parallel with the underface of the sealing resin 6.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置に係り、特
に樹脂モールドされるリードフレームの形状に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to the shape of lead frames molded with resin.

【0002】0002

【従来の技術】図5は従来のリードフレーム上への半導
体チップの実装状態を示す斜視図であり、図6は樹脂封
止後の図5のC−C線による断面図である。これらの図
において、1は半導体チップ、2はこの半導体チップ1
が取り付けられるリード、3,4は前記リード2と直角
に交わる方向のリード、5は前記半導体チップ1とリー
ド2,3,4とを接続する金属細線、6は前記半導体チ
ップ1と金属細線5を外部衝撃から保護するため樹脂封
止が施された封止樹脂、7は前記リード3,4をフォー
ミングしたリードフォーミング部である。リードフレー
ムを構成するリード2,3,4をヒータ(図示せず)で
加熱し、半導体チップ1を金錫半田(図示せず)等によ
りリード2に固着し、次ステーション上で、金等の金属
細線5により半導体チップ1のボンディングパターンと
、各リード2,3,4とを接続する。その後、エポキシ
等の封止樹脂6により、樹脂封止する。封止を終えた半
導体装置のリード2,3,4は、フォーミング加工(リ
ードフォーミング部7)された後、所定の長さに切断さ
れる。この後、回路基板に半導体装置のフォーミング加
工を施し、封止樹脂6下面とほぼ同一の高さとなったリ
ード2,3,4を半田付けして取り付ける。
2. Description of the Related Art FIG. 5 is a perspective view showing a state in which a semiconductor chip is mounted on a conventional lead frame, and FIG. 6 is a sectional view taken along the line CC in FIG. 5 after resin sealing. In these figures, 1 is a semiconductor chip, and 2 is this semiconductor chip 1.
3 and 4 are leads in a direction perpendicular to the leads 2, 5 is a thin metal wire connecting the semiconductor chip 1 and the leads 2, 3, and 4, and 6 is a thin metal wire 5 between the semiconductor chip 1 and the leads 2, 3, and 4. 7 is a lead forming part in which the leads 3 and 4 are formed. The leads 2, 3, and 4 that make up the lead frame are heated with a heater (not shown), and the semiconductor chip 1 is fixed to the leads 2 with gold-tin solder (not shown). The bonding pattern of the semiconductor chip 1 and each lead 2, 3, 4 are connected by a thin metal wire 5. Thereafter, resin sealing is performed using a sealing resin 6 such as epoxy. The leads 2, 3, and 4 of the semiconductor device that have been sealed are subjected to a forming process (lead forming section 7) and then cut into a predetermined length. Thereafter, the circuit board is subjected to a semiconductor device forming process, and the leads 2, 3, and 4, which are at approximately the same height as the lower surface of the sealing resin 6, are attached by soldering.

【0003】0003

【発明が解決しようとする課題】従来の半導体装置は、
以上のように構成されているので、封止樹脂6より外部
へ取り出されるリード2〜4は図6に示すように、封止
樹脂6の厚みのほぼ中央からとなり、回路基板へ取り付
けるためにはリード2〜4を封止樹脂6下面と同一また
は若干下になるようにフォーミング加工する必要がある
[Problems to be Solved by the Invention] Conventional semiconductor devices are
With the structure described above, the leads 2 to 4 taken out from the sealing resin 6 to the outside are from approximately the center of the thickness of the sealing resin 6, as shown in FIG. It is necessary to form the leads 2 to 4 so that they are flush with or slightly below the lower surface of the sealing resin 6.

【0004】また、高周波で使用される半導体装置では
、半導体チップ1から回路基板の半田付け部分までの距
離が長くなるため、リード2〜4による損失が大きくな
り、半導体チップ1の性能を十分に引き出すことができ
なくなるなどの問題点があった。
In addition, in semiconductor devices used at high frequencies, the distance from the semiconductor chip 1 to the soldered part of the circuit board becomes long, so the loss due to the leads 2 to 4 becomes large, and the performance of the semiconductor chip 1 is not fully maintained. There were problems such as not being able to withdraw the money.

【0005】本発明は、上記のような問題点を解消する
ためになされたもので、リードフレームの形状を変更す
ることにより、半導体チップの性能を最大限に引き出す
ようにした半導体装置を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and provides a semiconductor device that maximizes the performance of a semiconductor chip by changing the shape of a lead frame. With the goal.

【0006】[0006]

【課題を解決するための手段】本発明に係る半導体装置
は、封止樹脂内に収納されるリード部分をフォーミング
加工し、封止樹脂下面と水平にリードを取り出す構造と
したものである。
[Means for Solving the Problems] A semiconductor device according to the present invention has a structure in which a lead portion accommodated in a sealing resin is formed and the leads are taken out horizontally to the lower surface of the sealing resin.

【0007】[0007]

【作用】本発明における半導体装置は、封止樹脂内部の
リード部分がフォーミング加工されることにより、封止
樹脂下面より水平にリードが取り出せることから、回路
基板へ装着した場合にも、リードによる損失を低く抑え
ることができる。
[Operation] In the semiconductor device of the present invention, the lead portion inside the sealing resin is formed, so that the leads can be taken out horizontally from the bottom surface of the sealing resin. can be kept low.

【0008】[0008]

【実施例】以下、本発明の一実施例を図について説明す
る。図1は本発明によるリードフレームを構成するリー
ド上への半導体チップの実装状態を示す斜視図、図2は
、図1のA−A線によるモールド後の断面図を示す。 これらの図において、各部の構成は図5,図6と同じで
あるが、この実施例では、リードフォーミング部7は封
止樹脂6内で加工されており、かつ封止樹脂6の下面と
水平に取り出されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a state in which a semiconductor chip is mounted on a lead constituting a lead frame according to the present invention, and FIG. 2 is a cross-sectional view taken along line A--A in FIG. 1 after molding. In these figures, the configuration of each part is the same as in FIGS. 5 and 6, but in this embodiment, the lead forming part 7 is processed within the sealing resin 6, and is parallel to the lower surface of the sealing resin 6. It has been taken out.

【0009】このような構造のリードフレームを使用す
ることにより、封止樹脂6より取り出されるリード2〜
4は、封止樹脂6下面と水平方向となる。これにより、
回路基板への半導体装置の取り付けは、封止樹脂6から
取り出されたリード2〜4の根元で半田付けができ、半
導体チップ1から回路基板の半田付け部分までの距離は
封止樹脂6内部のリードフレームの長さと同等となり、
長さが短縮できる。
By using a lead frame having such a structure, the leads 2 to 2 taken out from the sealing resin 6
4 is horizontal to the lower surface of the sealing resin 6. This results in
The semiconductor device can be attached to the circuit board by soldering at the base of the leads 2 to 4 taken out from the sealing resin 6, and the distance from the semiconductor chip 1 to the soldered part of the circuit board is determined by the distance inside the sealing resin 6. It is equivalent to the length of the lead frame,
The length can be shortened.

【0010】なお、上記実施例では、半導体チップ1を
取り付けるリード2と、他のリード3,4の高さを同一
としたが、図3,図4に示すように、リード2の半導体
チップ1を取り付ける部分を凹状にしてもよい。
In the above embodiment, the height of the lead 2 to which the semiconductor chip 1 is attached is the same as that of the other leads 3 and 4, but as shown in FIGS. The part to which it is attached may be made concave.

【0011】[0011]

【発明の効果】以上説明したように、本発明によれば、
封止樹脂からのリードの引き出しは、封止樹脂下面より
水平方向となり、また、半導体チップから回路基板まで
の距離が短縮でき、高周波で使用される半導体装置では
、損失を押えることができ、半導体チップの性能を十分
に引き出せる効果がある。
[Effects of the Invention] As explained above, according to the present invention,
The leads from the encapsulating resin are pulled out horizontally from the bottom surface of the encapsulating resin, and the distance from the semiconductor chip to the circuit board can be shortened, reducing loss in semiconductor devices used at high frequencies. This has the effect of bringing out the full performance of the chip.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例によるリードフレームを示す
斜視図である。
FIG. 1 is a perspective view showing a lead frame according to an embodiment of the present invention.

【図2】図1の樹脂封止後のA−A線による断面図であ
る。
FIG. 2 is a cross-sectional view taken along line AA of FIG. 1 after resin sealing.

【図3】本発明の他の実施例によるリードフレームを示
す斜視図である。
FIG. 3 is a perspective view showing a lead frame according to another embodiment of the present invention.

【図4】図3の樹脂封止後のB−B線による断面図であ
る。
FIG. 4 is a sectional view taken along line BB after resin sealing in FIG. 3;

【図5】従来のリードフレームを示す斜視図である。FIG. 5 is a perspective view showing a conventional lead frame.

【図6】図5の樹脂封止後のC−C線による断面図であ
る。
FIG. 6 is a sectional view taken along line CC of FIG. 5 after resin sealing.

【符号の説明】[Explanation of symbols]

1  半導体チップ 2  リード 3  リード 4  リード 5  金属細線 6  封止樹脂 7  リードフォーミング部 1 Semiconductor chip 2 Lead 3 Lead 4 Lead 5 Thin metal wire 6 Sealing resin 7 Lead forming section

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】リードフレームのリード上に取り付けられ
た半導体チップを封止樹脂により樹脂封止した半導体装
置において、前記封止樹脂内に収納されるリード部分を
フォーミング加工し、このリードを前記封止樹脂下面よ
り水平に取り出したことを特徴とする半導体装置。
1. A semiconductor device in which a semiconductor chip mounted on the leads of a lead frame is sealed with a sealing resin, in which a lead portion accommodated in the sealing resin is formed, and the leads are sealed in the sealing resin. A semiconductor device characterized in that it is taken out horizontally from the bottom surface of a stopper resin.
JP3085164A 1991-04-17 1991-04-17 Semiconductor device Pending JPH04318959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3085164A JPH04318959A (en) 1991-04-17 1991-04-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3085164A JPH04318959A (en) 1991-04-17 1991-04-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04318959A true JPH04318959A (en) 1992-11-10

Family

ID=13851023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3085164A Pending JPH04318959A (en) 1991-04-17 1991-04-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04318959A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844308A (en) * 1997-08-20 1998-12-01 Cts Corporation Integrated circuit anti-bridging leads design
US5942794A (en) * 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942794A (en) * 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US6130115A (en) * 1996-10-22 2000-10-10 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US5844308A (en) * 1997-08-20 1998-12-01 Cts Corporation Integrated circuit anti-bridging leads design
EP0898309A3 (en) * 1997-08-20 2000-02-09 CTS Corporation An integrated circuit anti-bridging leads design

Similar Documents

Publication Publication Date Title
US5554886A (en) Lead frame and semiconductor package with such lead frame
JPH07273268A (en) Semiconductor package and lead frame for semiconductor package
JPS63296252A (en) Resin sealed semiconductor device
JPS6086851A (en) Resin sealed type semiconductor device
JPS58130553A (en) Semiconductor device
KR100333386B1 (en) chip scale package
JPS63310151A (en) Support pad of integrated electronic component
JP2876846B2 (en) Resin-sealed semiconductor device
JPS60257159A (en) Semiconductor device
JPS589585B2 (en) Dense hinge lead frame
KR910000018B1 (en) Semiconductor device using the lead-frame and method of manufacture there of
JPS61241954A (en) Semiconductor device
JPH03104141A (en) Semiconductor device
JPH03248454A (en) Hybrid integrated circuit device
KR200159861Y1 (en) Semiconductor package
KR100372117B1 (en) Multi Pin Type Lead Frame
JPH04206763A (en) Semiconductor device
JPH0199245A (en) Ic package
JPS5994447A (en) Glass-sealed type semiconductor device
KR100451488B1 (en) Semiconductor package having reduced size and thin thickness and fabricating method thereof
KR0129196B1 (en) Semiconductor package with separate mounting leads
JPH062710U (en) Semiconductor package
JPS6151852A (en) Printed circuit board and manufacture thereof
JPH04159762A (en) Semiconductor device
JPH04278573A (en) Package for semiconductor integrated circuit