JPH0432004A - Reading circuit for floppy disk device - Google Patents

Abstract

PURPOSE:To follow up the variance in output amplitude of a floppy disk by providing a variable level slicing circuit and a delay circuit. CONSTITUTION:The voltage signal outputted from a magnetic head 12 is subjected to full-wave rectification, and the voltage signal subjected to full-wave rectification is smoothed to determine a threshold, and the voltage signal subjected to full-wave rectification is compared with the threshold, and a variable level slicing circuit 26 outputs a pulse signal based on the comparison result. A delay circuit 28 is provided which delays the pulse signal from the variable level slicing circuit 26 in accordance with the phase deviation time of a differentiator 18 and interrupts the operation of a comparator 20 by this pulse signal. Thus, even the variance in amplitude of the voltage signal related to read of a floppy disk 10 is followed up, and an influence of a saddle continuing for a long time is excluded to take a large saddle margin.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reading circuit for a floppy disk device (hereinafter referred to as FDD), and in particular to an improvement in a configuration for eliminating a saddle.

[Prior Art] Floppy disks, which are polyester disks coated with magnetic powder, are widely used as auxiliary memories in computers, word processors, etc. as large-capacity, rewritable memories. In a floppy disk, information is recorded as magnetization changes of residual magnetization, and the magnetization changes are converted into voltage changes by a magnetic head and read out.

FIG. 7 shows the configuration of a conventional FDD reading circuit.

In this figure, a magnetic head 12 reads magnetization changes recorded on the surface of a floppy disk 10 as voltage changes, an amplifier 14 amplifies the voltage changes read by the magnetic head 12, and an amplifier 14 that lowers the output. A low-pass filter 16 that performs bandpass filtering, a differentiator 18 that differentiates the output of the low-pass filter 16, and a comparator 2 that detects zero crossings of the output of the differentiator 18 and outputs a waveform signal.
0, a time domain filter 22 that filters the output of the comparator 20 in the time domain, and a pulse shaper 24 that shapes and generates a pulse signal from the output of the time domain filter 22.

FIG. 8 shows the operation of this conventional example.

In FIG. 8(A), a magnetization change 100 indicated by an arrow is recorded on the surface of the floppy disk 10. In FIG.

The magnetic head 12 reads this magnetization change 100 and supplies it to the low-pass filter 16 via the amplifier 14. The voltage waveform output from the low-pass filter 16 to the differentiator 18 becomes a waveform 102 as shown in FIG. 8(B). The waveform 102 has a peak at a portion where the magnetization change 100 is reversed.

When the waveform 102 is differentiated by the differentiator 18, FIG.
) is a differential waveform 104 shown in FIG. Furthermore, when this is supplied to the comparator 20, a square wave signal 106 as shown in FIG. 8(D) is obtained. That is, the comparator 20 detects the zero cross of the differential waveform 104 shown in FIG. 8(C), and creates a square wave signal 106 that is inverted at this zero cross point.

The square wave signal 106, which is the output of the comparator 20, is provided to a pulse shaper 24 via a time domain filter 22. The pulse shaper 24 generates a pulse signal 108 in response to rising/falling edges of the square wave signal 106;
This pulse signal 108 will be output to the outside.

FIG. 9 shows the operation of the time domain filter 22.

Generally, in a reading circuit for an FDD device, when trying to increase the reading resolution, a waveform concave portion, a so-called saddle 110, as shown in FIG. 9(A) occurs. That is, in the differential waveform 104 output from the differentiator 18, a saddle 110 occurs particularly near its peak.

This saddle 110 corresponds to a portion on the surface of the floppy disk 10 where there is no magnetization change 100. That is, in a region of constant magnetization on the surface of the floppy disk 10, the change in the read voltage by the magnetic head 12 is zero, so when this is differentiated by the differentiator 18, the value approaches zero.

When the differential waveform [04] shown in FIG. 9(A) is supplied to the comparator 20, a pulse 112 corresponding to the saddle 110 is generated as shown in FIG. 9(B).

Time domain filter 22 filters square wave signal 106 in the time domain to remove this pulse 112. That is, the square signal 1 shown in FIG. 9(B)
This is a digital filter circuit for removing 06. In detail, the rising and falling edges of the rectangular signal 106 shown in FIG. 9(B) are detected using logical differentiation, and a certain delay is applied to the rising and falling edges of the rectangular signal 106 shown in FIG. 9(B) at that point in time.
It is determined that it is a signal when the logic of B) is inverted with respect to the logic of the previous pulse.

In this way, conventionally, the pulse 112, which is the noise corresponding to the saddle 110, has been removed by the time domain filter 22.

[The problem that the invention attempts to solve! fi] However, in the conventional FDD reading circuit,
There were problems such as the need for a low-pass filter that needed to be switched depending on the saddle, and the inability to remove extremely large saddles.

That is, if there is a saddle that lasts for a relatively long time,
The distance between the saddle and the signal becomes narrower, making it impossible to remove the saddle. In order to eliminate such obstacles, it has been necessary to provide a low-pass filter that must be switched depending on the saddle.

On the other hand, so-called level slice circuits have been used in reading circuits for hard disk drives, etc., but these circuits are based on the assumption that the amplitude of the signal related to the output from the hard disk, the so-called output amplitude, is approximately constant. It is not suitable for media with large fluctuations in output amplitude, such as floppy disks.

The present invention was made to solve these problems, and aims to eliminate the time domain filter in a reading circuit for an FDD device and to make it possible to follow output amplitude fluctuations of a floppy disk. shall be.

[Means for Solving the Problems] In order to achieve such an object, the present invention performs full-wave rectification of a voltage signal output from a magnetic head, smoothes the full-wave rectified voltage signal, and converts it to a threshold value. A variable level slicing circuit that determines the value, compares the full-wave rectified voltage signal with a threshold value, and outputs a pulse signal based on the comparison result, and a differentiator phase that outputs the pulse signal from the variable level slicing circuit. The present invention is characterized in that it includes a delay circuit that delays the comparator in accordance with the time difference and uses the pulse signal to intermittent the operation of the comparator.

[Operation] In the FDD reading circuit of the present invention, information magnetically recorded on a floppy disk is read out as a voltage signal by a magnetic head, and this voltage signal is further differentiated by a differentiator. A comparator detects zero crossings of the differentiated voltage signal and generates a square wave signal. Further, a pulse shaper generates and outputs a pulse signal from this square wave signal. On the other hand, the voltage signal read from the magnetic head is full-wave rectified in a variable level slice circuit, and the full-wave rectified voltage signal is smoothed to determine a threshold value. Further, in the variable level slice circuit, the full-wave rectified voltage signal is compared with a threshold value, and a pulse signal is output based on the result of this comparison. The pulse signal output from the variable level slice circuit is supplied to a delay circuit, which delays the pulse signal according to the phase shift time of the differentiator, and the delayed pulse signal causes the operation of the comparator to be intermittent. The Rukoto.

Therefore, since the threshold value of the variable level slice circuit is determined according to the rectification and smoothing value of the voltage signal read from the floppy disk, even if amplitude fluctuation occurs in the voltage signal read from the floppy disk, It becomes possible to follow this and perform level slicing to remove noise related to the saddle.

[Examples] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. Note that the same components as those of the conventional example shown in FIGS. 7 to 9 are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 1 shows the configuration of an FDD reading circuit according to an embodiment of the present invention.

In this figure, the output of the low-pass filter 16 is connected to a level slice circuit 26, and the level slice circuit 26 is further connected to a delay circuit 28 and a comparator 20 in sequence. Further, the differentiator 18 is connected to the delay circuit 2
8 is connected.

FIG. 2 shows a level slice circuit 2 according to the features of the present invention.
6 configurations are shown.

This figure shows full-wave rectifier circuits 30 and 32 to which the differential voltage from the low-pass filter 16 is input. In addition, the inputs of the full-wave rectifier circuits 30 and 32 include
Bias power supplies are connected through resistors 34 and 36, respectively, and therefore, full-wave rectifier circuits 30 and 32 have
A biased differential voltage is input.

Additionally, in this figure, a full-wave rectifier circuit 4 is connected to the bias power supply through resistors 38 and 40.
2 is shown. The output end of this full-wave rectifier circuit 42 is
It is connected to the output terminal of the full-wave rectifier circuit 30 via resistors 44 and 46 having a predetermined resistance ratio, and the full-wave rectifier circuit 3
A smoothing capacitor 48 is connected to the output terminals of 0 and 42.

Furthermore, in this figure, a comparator 50 is shown, and the positive input of this comparator 50 is the output terminal of the aftereffect rectifier circuit 32, and the negative input is the connection between the full-wave rectifier circuit 30 and the full-wave rectifier circuit 42. Resistors 44 and 46
The connection points are connected to each other. Comparator 5
The output of 0 is connected to delay circuit 28.

Further, FIG. 3 shows the configuration of full-wave rectifier circuits 30, 32, and 42 included in the level slice circuit 26.

That is, full-wave rectifier circuits 30, 32 and 42 have similar configurations.

In FIG. 3, the collectors and emitters of transistors 52 and 54 are connected, respectively, and a first constant current source 56 is connected to the collector side, and a second constant current source 58 is connected to the emitter side. ing. In addition, constant current source 5
6 and 58 are connected to a clamp circuit 60.

The emitters of transistors 66 and 68 are connected to the bases of transistors 52 and 54 via resistors 62 and 64, respectively. These transistors 66 and 68
Constant current sources 70 and 72 are connected to the emitters of , respectively.

The bases of transistors 66 and 68 serve as input terminals of a full-wave rectifier circuit, respectively, and the bases of transistors 52 and 5
The 4 emitters each serve as an output end.

FIG. 4 shows the operation of the full-wave rectifier circuit shown in FIG. 3.

4 (A) and (
Assume that there are differential inputs 118 and 120 as shown in B). Then, the differential inputs 118 and 120 are
It is input to the bases of transistors 52 and 54 via transistors 66 and 68, respectively. transistor 5
The outputs from emitters 2 and 54 look like the waveform 122 shown by the dashed line in FIG. 4(C). In other words, it becomes a full-wave rectified waveform.

When this waveform 122 is supplied to, for example, a capacitor 47 or 48 and smoothed, a waveform 1 shown in FIG.
This results in a smoothed waveform like 24.

Here, as shown in FIGS. 4(A) and 4(B), the peak pulses 126 and 128 are
Consider the case where it is superimposed on 0. Then, a peak pulse 130 is generated in the full-wave rectified waveform 122 in response to this. Here, the full-wave rectifier circuit shown in FIG.
Since it is driven with a constant current by the second current source 58, the peak pulse 130 in the full-wave rectified waveform 122 related to the output from the emitters of the transistors 52 and 54 hardly contributes to the smoothed waveform 124 by the capacitor 48.

Therefore, according to the full-wave rectifier circuit shown in FIG. 3, the influence of the peak pulses 126 and 128 superimposed on the operating forces 118 and 120 can be eliminated.

By using a full-wave rectifier circuit having such a configuration as the aftereffect rectifier circuits 30, 32 and 42 in FIG. 2, the level slice circuit 26 shown in FIG. 2 operates as shown in FIG. becomes.

For example, assume that the input waveforms of the full-wave rectifier circuits 30 and 32 are the sine wave 132 shown in FIG. 5(A) and a waveform differential therefrom. In this case, the voltage waveforms 134 output from the full-wave rectifier circuits 30 and 32 are both full-wave rectified waveforms, as shown in FIG. 5(B). Among these, the output of the full-wave rectifier circuit 30 is smoothed by the capacitor 48, and has an effective value according to the amplitude of the waveform 132 related to the input of the full-wave rectifier circuit 30, as shown in FIG. 5(C). A smooth waveform 136 is obtained.

On the other hand, since the input of the full-wave rectifier circuit 42 is connected to the bias power supply via the resistors 38 and 40 and is a constant voltage circuit, the output of the full-wave rectifier circuit 42 is a DC voltage 138 as shown in FIG. 5(D). Become.

When such waveforms 136 and 138 are output from the full-wave rectifier circuits 30 and 42 and supplied to the resistors 44 and 46, a DC voltage is input to the negative input of the comparator 50.

That is, the value of the DC voltage related to the negative input of the comparator 50 is determined according to the amplitude of the differential input to the aftermath rectifier circuit 30. Further, the values of the resistors 44 and 46 are set so that this voltage is about 30 to 40% of the total output voltage of the full-wave rectifier circuits 30 and 42. In this figure, resistor 44 is set to have a resistance twice the value of resistor 46.

On the other hand, the voltage waveform 134 output from the full-wave rectifier circuit 32 is input to the positive input of the comparator 50. Therefore, the voltage output as a result of the comparison in the comparator 501 becomes a pulse 140 generated at the portion where the waveform 134 exceeds the DC voltage related to the negative input of the comparator 50, as shown in FIG. 5(E).

FIG. 6 shows, as a timing chart, the operation of this embodiment employing the level slice circuit 26 having such a configuration and operation.

In FIG. 6, the voltage signal read from the floppy disk 10 by the magnetic head 12 and supplied to the differentiator 18 via the amplifier 14 and the low-pass filter 16 is, for example, as shown in FIG. 6(A). A waveform 142 is obtained.

On the other hand, this waveform 142 is also input to the level slice circuit 26 according to a feature of the present invention.

When the waveform 142 is differentially input, the level slice circuit 26 determines a threshold value according to the rectification/smoothing value of the waveform 142 by the operation described above, and divides the second threshold value and the waveform 1
42 full-wave rectified waveforms (outputs of the full-wave rectifier circuit 32) are compared. As a result of this threshold comparison, the level slice circuit 2
A pulse signal is output from the comparator 50 of No. 6.

This pulse signal is supplied to the delay circuit 28 and delayed by a predetermined time. That is, the delay circuit 28 delays the pulse signal and generates the signal 1 as shown in FIG. TS6 (B).
46 is generated. This delay time Δt corresponds to the phase shift time of the differentiating circuit 18.

On the other hand, the differentiated waveform by the differentiating circuit 18 is shown in FIG. 6(C).
A waveform 144 as shown in FIG. Waveform 1 like this
44 is input to the comparator 20.

The comparator 20 is also supplied with the waveform 146 output from the delay circuit 28, as described above.

The comparator 20 detects only the portion where the waveform 146 takes an H level among the zero-crossing portions of the waveform 144, generates a waveform 148 as shown in FIG. 6(D), and sends it to the pulse shaper 24. Output.

The pulse shaper 24 differentiates this waveform 148 to generate a rising/falling pulse 150 as shown in FIG. 6(E), and shapes this into a pulse 152 shown in FIG. 6(F). generate.

Therefore, in this embodiment, the floppy disk 1
The pulse 152 can be generated by removing the saddle effect that occurs in a portion where the magnetization on the 0 plane is constant. That is, waveform 148 can only be inverted when waveform 142 is at its peak. Furthermore, even if the amplitude of the voltage signal 142 related to reading from the floppy disk 10, that is, the output amplitude fluctuates, the threshold value is determined by the output of the full-wave rectifier circuit 30 of the level slice circuit 26. It is possible to follow output amplitude fluctuations.

Furthermore, compared to a configuration using a conventional time domain filter, it is possible to cope with saddles that continue for a long time. In other words, a large saddle margin can be achieved.

Furthermore, for the same reason, there is no need to use a filter that requires switching depending on the saddle as the low pulse filter 16.

[Effects of the Invention] As explained above, according to the present invention, even when the amplitude of the voltage signal related to reading from a floppy disk fluctuates, it is possible to follow it, and furthermore, the saddle can continue for a long time. It is also possible to eliminate the influence of this, and a large saddle margin can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a reading circuit for a floppy disk device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a level slice circuit in this embodiment, and FIG. FIG. 4 is a circuit diagram showing the configuration of the full-wave rectifier circuit in this embodiment. FIG. 4 is a waveform diagram showing the operation of the full-wave rectifier circuit in this embodiment, and FIGS. Input waveform diagram, Figure 4 (C) is a rectification and smoothing waveform diagram, Figure 5 is a waveform diagram showing the operation of the level slice circuit, and Figure 5 (A) is an input waveform diagram, Figure 5 (B) is a full-wave rectification waveform diagram, Figure 5 (C) is an eave flow and smooth waveform diagram, and Figure 5
Figure (D) is a DC voltage diagram, Figure 5 (E) is an output pulse diagram of the comparator of the level slice circuit, and Figure 6 is a timing chart diagram showing the operation of this embodiment. ) is a waveform diagram of the voltage signal related to reading from the floppy disk, FIG. 6(B) is a waveform diagram of the square wave signal related to the output of the delay circuit, and FIG. 6(C) is a waveform diagram related to the output from the differentiator. , FIG. 6(D) is an output waveform diagram of the comparator, FIG. 6(E) is a waveform diagram of a signal obtained by differentiating the comparator output, FIG. 6(F) is a waveform diagram of the pulse output from the pulse shaper, FIG. 7 is a block diagram showing the configuration of a conventional reading circuit for a floppy disk device. FIG. 8 is a timing chart showing the operation of this conventional example, and FIG. Figure 8 (B) is a waveform diagram of the voltage signal read from the floppy disk, Figure 8 (C) is a differential waveform diagram of the voltage signal read from the floppy disk, Figure 8 ( D) is the output waveform diagram of the comparator, Figure 8 (E)
is an output waveform diagram of the pulse shaper, FIG. 9 is a timing chart diagram showing the operation of the time domain filter, FIG. 9(A) is an output waveform diagram of the differentiator, and FIG. 9(B) is a comparator output waveform diagram. FIG. 9(C) is an output waveform diagram of the time domain filter. 10... Floppy disk 12... Magnetic head 18... Differentiator 20... Comparator 24... Pulse shaper 26... Level slice circuit 28... Delay circuit

Claims (1)

[Claims] A magnetic head that reads out information magnetically recorded on a floppy disk as a voltage signal, a differentiator that differentiates this voltage signal, and outputs a square wave signal by detecting zero crossings of the differentiated voltage signal. In a reading circuit for a floppy disk device, which has a comparator that shapes the square wave signal and a pulse shaper that shapes the square wave signal and outputs a pulse signal, the voltage signal output from the magnetic head is full-wave rectified. A variable level slicing circuit that smoothes a voltage signal obtained by smoothing the voltage signal to determine a threshold value, compares the full-wave rectified voltage signal with the threshold value, and outputs a pulse signal based on the comparison result. A read circuit for a floppy disk device, comprising: a delay circuit that delays a pulse signal from a differentiator according to a phase shift time of a differentiator, and uses the pulse signal to intermittent operation of a comparator.