JPH04320148A - Picture reader - Google Patents

Abstract

PURPOSE:To increase the entire read speed by quickening a transfer speed of an ineffective picture element other than a designated read area faster than a transfer speed in a designated read area when an original with a size smaller than a maximum read size is read. CONSTITUTION:An MPU 9 sets a timing to a programmable timer PTM 10 based on a position of a designation read area and size information and generates signals SH, VAL1D and they are fed to a CCD 8 and a SEL 14. A crystal oscillator OSC 11 generates a reference frequency, a frequency division counter CNT 12 frequency-divides it to obtain pulse trains whose maximum and basic operating frequencies are 10MHz and 5MHz. A clock generating gate 13 generates signals phi1, phi2, RS1, RS2 from an output of the CNT and the selector SEL 14 selects either the signals phi1, RS1 or the signals phi2, RS2 based on the signal VALID to drive the CCD 8. Thus, a waste time of an invalid area is reduced and the entire read time is decreased.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an image reading device using an image sensor such as a CCD, and in particular, it reduces the reading time when cutting out and reading a certain image area within the maximum screen size of the image sensor. The present invention relates to an image reading device that can read images.

0002

2. Description of the Related Art FIG. 4 is a schematic diagram of a conventional image reading device using an image sensor. In the figure, 1 is an image sensor, 2 is a clock driver, and 3 is a drive clock generation circuit. The image sensor 1 is composed of a one-dimensional CCD, and the drive clock generation circuit 3 generates a shift pulse signal SH and a transfer clock φ for controlling the image sensor 1.
, generates a driving clock consisting of a reset signal RS,
It is supplied to the image sensor 1 via the clock driver 2.

In the image sensor, SH takes the signal of the sensor cell into the shift register, and φ and RS are used to shift and transfer the signal in the shift register. Figure 5
is a timing diagram of these driving clocks. In the figure (
1) indicates the shift pulse signal SH. Since the shift pulse signal SH is output at the beginning of each main scan, the period TSH corresponds to a period for scanning all pixels for one line. Further, (2) indicates the transfer clock φ, and (3) indicates the reset signal RS. (4) is a reading valid area signal VALID for cutting out a certain reading area within the maximum reading size of the image sensor. This signal is combined with the video signal output from the image sensor to indicate whether the pixel is valid or invalid. In the illustrated example, one line scanning period TSH
is divided into three parts, T1, T2, and T3, and the period T2
The pixels in the area corresponding to T1 and T3 are used as valid pixels, and the pixels in the area corresponding to the preceding and succeeding periods T1 and T3 are discarded as invalid pixels. This reading valid area signal VAL
For example, as shown in Figure 6, when the maximum reading screen of the image sensor is A3 size, and when reading an A4 size document that is actually smaller, the ID is used to read A4 documents on the side of the video signal utilization device. Used to enable only pixels within the region.

0004

[Problems to be Solved by the Invention] In conventional image reading devices, the length of the main scanning period TSH is constant regardless of the actual size of the reading area, and even invalid pixels are scanned at the same speed as effective pixels. It had been transferred. Therefore, if the actual read size is smaller than the maximum read size of the image sensor, there will be a lot of wasted transfer time due to invalid pixels.
There was a problem that the actual reading speed decreased.

An object of the present invention is to reduce wasteful transfer time due to invalid pixels and to realize an efficient reading speed corresponding to the specified reading size.

[0006]

[Means for Solving the Problems] The present invention aims to increase the overall reading speed by making the transfer speed of invalid pixels outside the specified reading area of an image sensor faster than the transfer speed of valid pixels within the specified reading area. It is something to do.

FIG. 1 is a diagram showing the basic configuration of the present invention. In the figure, 1 is an image sensor, 2 is a clock driver, 3 is a drive clock generation circuit, 4 is a drive clock generation circuit for basic operating frequency, 5 is a drive clock generation circuit for maximum operating frequency, 6 is a drive clock selector, and 7 is a drive clock generation circuit. It is a control circuit.

The drive clock generation circuit 3 includes a drive clock generation circuit 4 for basic operating frequency and a drive clock generation circuit 5 for maximum operating frequency. ,
For example, the maximum operating frequency drive clock generation circuit 5 generates a transfer clock φ at 5 MHz, and a drive clock consisting of a reset signal RS1, and generates a transfer clock φ at the maximum operating frequency of the image sensor 1, for example 10 MHz.
2 and a reset signal RS2.

The drive clock selector 6 selects φ,RS1 when the read valid area signal VALID is ON (valid), and selects φ,RS2 when VALID is OFF (invalid).
Select. The control circuit 7 generates a shift pulse signal SH and a valid reading area signal VALID, supplies SH to the image sensor 1, and supplies VALID to the drive clock selector 6.
supply to. The control circuit 7 controls the main scanning line according to the position and size of the designated reading area within the maximum reading size of the image sensor using a driving clock φ, RS1 at a basic speed.
section using high-speed drive clock φ2, RS2
Then, the time required to scan each section is calculated from the number of pixels in each section and the clock frequency, and based on that, the change timing of SH and VALID is determined and signal generation is performed. .

The driving clock selector 6 selects φ based on the ON/OFF of VALID generated in this way.
, RS1 and φ2, RS2 are selected and sent to the clock driver 2. The clock driver 2 amplifies this and supplies it to the image sensor 1. The image sensor 1 reads pixels on a main scanning line at a speed determined by the current operating frequency of a given drive clock, and pixels in an invalid area are read out at high speed.

[0011]

FIG. 2 is a timing diagram of the driving clock supplied to the image sensor 1 in the configuration of the present invention shown in FIG. Hereinafter, the operation of the configuration of the present invention will be explained using FIG. 2.

In FIG. 2, (1) is a shift pulse signal SH, which is generated every main scan. The period between successive SH pulses is a main scanning period 1SH' for one line. (2) is the transfer clock φ, (3) is the reset signal R
S, and their operating frequencies are φ1 and φ2, respectively, depending on the value of the valid read area signal VALID in (4).
, RS1 and RS2.

VALID within main scanning period TSH'
The OFF, ON, and OFF sections of T1 ′, T2 ′
, T3', the interval T2' corresponds to the valid specified reading area on the main scanning line, and the interval T1'
The sections T3' and T3' correspond to the invalid area.

Since the operating frequencies of the drive clocks φ2 and RS2 at T1' and T3' are set higher than the operating frequencies of the drive clocks φ and RS1 at T2', the pixel reading speed in the interval T1' and T3' is is faster than the interval T2'. Furthermore, when comparing the timing diagram of the conventional example shown in FIG. 5, assuming that the position and size of the designated reading area are the same in both, T1'<T1, T2'=T2, T3.
'<T3, and if the frequency of φ2, RS2 is twice the frequency of φ1, RS1, the reading time of the invalid area can be reduced to half of the conventional time, and accordingly, TSH'<TSH.

[0015]

Embodiment FIG. 3 is a block diagram of an image reading apparatus according to an embodiment of the present invention. In the figure, 8 is a CCD, 9 is an MPU, 10 is a programmable timer PTM, and 11 is a crystal oscillator OSC.
, 12 is a frequency division counter CNT, 13 is a clock generation gate, 14 is a selector SEL, and 15 is a clock driver.

The MPU 9 sets appropriate timing in the PTM 10 based on information on the position and size of the specified reading area inputted from a mechanism such as a key or a tablet (not shown), and causes the PTM 10 to generate the SH and VALID signals. , are supplied to the CCD 8 and SEL 14, respectively.

The OSC 11 generates a pulse train at a reference frequency, and the CNT 12 divides this to obtain a pulse train at the maximum operating frequency or basic operating frequency. Gate 13 combines the outputs of CNT12 and outputs φ1 and φ2.
, RS1 and RS2 are generated.

SEL14 determines φ based on the value of VALID.
1 and RS1 or φ2 and RS2. The clock driver 16 has SH, φ1, R
The drive pulses of each set of S or SH, φ2, and RS2 are amplified and applied to the CCD 8 to drive the CCD 8.

The CCD 8 performs a reading operation according to the applied driving pulse and outputs a video signal VOUT.

[0020]

[Effects of the Invention] According to the present invention, when reading an original whose size is smaller than the maximum reading size of an image sensor,
Since the wasted time spent reading invalid areas can be reduced, the reading speed is improved, and it is possible to significantly improve efficiency at a low cost, especially when used in electronic filing systems and digital copiers that read a large number of documents. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a timing diagram of a drive clock in the configuration of the present invention.

FIG. 3 is a configuration diagram of an image reading device according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional image reading device using an image sensor.

FIG. 5 is a timing diagram of a drive clock in a conventional image reading device.

FIG. 6 is an explanatory diagram of document reading at a small reading size.

[Explanation of symbols]

1 Image sensor 2 Clock driver 3 Drive clock generation circuit 4 Drive clock generation circuit for basic operating frequency 5 Drive clock generation circuit for maximum operating frequency 6 Drive clock selector

Claims (1)

[Claims] 1. An image reading device that reads an image using an image sensor, comprising: a first driving clock having a basic operating frequency of the image sensor; and a second driving clock having a frequency higher than the basic operating frequency of the image sensor. a drive clock generation circuit that generates a drive clock, a drive clock selector that selects either the first drive clock or the second drive clock outputted from the drive clock generation circuit according to an instruction, and The first driving clock is selected when scanning the valid reading area according to the position and size of the valid reading area specified by , and the second driving clock is selected in the remaining invalid reading area. A control circuit that generates a signal and applies it to the drive clock selector, supplies the drive clock obtained from the drive clock selector to the image sensor, and outputs the video signal extracted from the image sensor together with the valid reading area signal. An image reading device characterized by: