JPH04320332A - Thin film formation method - Google Patents

Thin film formation method

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Publication number
JPH04320332A
JPH04320332A JP8842091A JP8842091A JPH04320332A JP H04320332 A JPH04320332 A JP H04320332A JP 8842091 A JP8842091 A JP 8842091A JP 8842091 A JP8842091 A JP 8842091A JP H04320332 A JPH04320332 A JP H04320332A
Authority
JP
Japan
Prior art keywords
thin film
compound
film
electrode
atoms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8842091A
Other languages
Japanese (ja)
Inventor
Hitoshi Ito
仁 伊藤
Haruo Okano
晴雄 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8842091A priority Critical patent/JPH04320332A/en
Publication of JPH04320332A publication Critical patent/JPH04320332A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form selectively a good quality of thin film on a substrate in a specified region. CONSTITUTION:In a thin film formation method which forms a thin film by introducing a raw gas and absorbing a compound on a substrate by chemical reaction, A CuN compound, which is electrically polarized as the compound, is used whereas Cu atoms of the CuN compound is selectively introduced to upper electrodes 17 and 19 on the substrate by means of electric power.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、薄膜の形成方法に係り
、特にCVD法を用いた薄膜の形成方法の改良に関する
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a thin film, and more particularly to an improvement in a method for forming a thin film using a CVD method.

【0002】0002

【従来の技術】一般に超LSIなどの半導体装置は、電
荷を流し、電気信号を伝達するための導電性薄膜と導電
性薄膜間の電気的絶縁を図るための絶縁性薄膜とが積層
された構成をしている。導電性薄膜は、通常、Al・S
i・Cu合金、Asのような不純物が添加された多結晶
Si、WSi2 などの薄膜をパターニングして形成さ
れる。
[Prior Art] Semiconductor devices such as VLSIs generally have a structure in which a conductive thin film for flowing charge and transmitting electrical signals and an insulating thin film for electrically insulating the conductive thin films are stacked. doing. The conductive thin film is usually made of Al・S
It is formed by patterning a thin film of i.Cu alloy, polycrystalline Si added with impurities such as As, WSi2, or the like.

【0003】このような超LSIなどの半導体装置の高
集積化は主として素子の微細化によって実現されてきた
。例えば、IMDRAM、256KSRAMなどの超L
SIでは、ゲート長が1〜1.2μmまで縮小されて作
られており、更に、サブミクロンのオーダーのゲート長
をもつ高集積なULSIの制作が研究室レベルで試みら
れている。
High integration of semiconductor devices such as VLSIs has been achieved mainly by miniaturization of elements. For example, ultra large memory such as IMDRAM, 256KSRAM, etc.
SIs are manufactured with gate lengths reduced to 1 to 1.2 μm, and further attempts are being made at the laboratory level to create highly integrated ULSIs with gate lengths on the order of submicrons.

【0004】しかしながら、寸法がこのようなオーダー
の素子をスケーリング則に従い縦方向及び横方向をとも
に縮小すると、素子の性能及び信頼性が低下するため微
細化は主として横方向の寸法を縮小することで実現され
ている。
However, if an element with dimensions of this order is reduced in both the vertical and lateral directions according to the scaling law, the performance and reliability of the element will deteriorate, so miniaturization is mainly achieved by reducing the lateral dimension. It has been realized.

【0005】即ち、配線抵抗は断面積に比例するため、
横方向の寸法を縮小した場合には、縦方向の寸法を縮小
しないほうが抵抗値が小さくなるので性能向上の点でも
有利になる。また、縦方向の寸法を縮小すると電流密度
が著しく大きくなるため、配線中に電子が流れると配線
を構成する原子、例えば、Al配線の場合ではAl原子
が輸送され配線の線幅が細り、しまいには配線が断線す
る現象が生じる(エレクトロ・マイグレーション)。こ
のようなこともあるので、なるべく断面積を大きくする
ために、導電性薄膜の縦方向の縮小は、通常、積極的に
なされずにきた。
That is, since the wiring resistance is proportional to the cross-sectional area,
If the horizontal dimension is reduced, the resistance value will be smaller if the vertical dimension is not reduced, which is advantageous in terms of performance improvement. In addition, when the vertical dimension is reduced, the current density increases significantly, so when electrons flow in the wiring, the atoms that make up the wiring, for example, Al atoms in the case of Al wiring, are transported and the line width of the wiring becomes narrower. A phenomenon occurs in which the wiring becomes disconnected (electro migration). Because of this, in order to increase the cross-sectional area as much as possible, vertical reduction of the conductive thin film has generally not been actively carried out.

【0006】絶縁性薄膜の場合も、多層配線間の耐圧の
確保とクロストークの抑制という観点から、薄膜化は積
極的にはなされなかった。
[0006] In the case of insulating thin films as well, thinning has not been actively pursued from the viewpoint of ensuring voltage resistance between multilayer interconnections and suppressing crosstalk.

【0007】このように超LSIの信頼性及び信頼性を
維持する観点から、各薄膜は急激に薄くすることが出来
なかった。
[0007] As described above, from the viewpoint of maintaining the reliability and reliability of VLSIs, each thin film cannot be rapidly thinned.

【0008】この結果、超LSIの表面は凹凸な形状を
示し、例えば、サブミクロンの設計基準の超LSIでは
、0.5μm以下のピッチで配線が形成され、それらの
間が絶縁膜で埋めているため、その表面形状は凹凸の激
しいものとなる。
As a result, the surface of a VLSI exhibits an uneven shape. For example, in a VLSI based on submicron design standards, wiring is formed at a pitch of 0.5 μm or less, and the spaces between them are filled with an insulating film. As a result, the surface shape becomes extremely uneven.

【0009】更に、半導体装置の集積度を上げるため、
各配線の形状として切り立った長方形が採用されている
。配線の形状がこのように切り立ってくると、その上に
堆積した絶縁膜の形状も同様に切り立つ。
Furthermore, in order to increase the degree of integration of semiconductor devices,
A sharp rectangle is adopted as the shape of each wiring. When the shape of the wiring becomes steep in this way, the shape of the insulating film deposited on it also becomes steep.

【0010】このような下地絶縁膜の表面に次の層の導
電性膜をスパッタ堆積すると、段差部でいわゆる段切れ
と呼ばれる段差底部での導電膜の極端な細線化が生じ、
著しい場合には、切れて堆積するようになる。この現象
は特に接続孔の底部で顕著に見られ、接続孔が細くて深
い孔になると、極端な場合、接続孔の底部にまったく導
電性薄膜が堆積しなくなる。例えば、16MDRAMで
は開口径が0.5μm、深さが1.5μm前後になると
予想されており、この場合、アスペクト比が3前後にな
り、通常のスパッタでは、Al合金膜が接続孔の底部に
堆積しないことが実験で確認されている。
When the next layer of conductive film is sputter-deposited on the surface of such a base insulating film, the conductive film becomes extremely thin at the bottom of the step, which is called a step cut.
In severe cases, it may break off and accumulate. This phenomenon is particularly noticeable at the bottom of the connection hole, and in extreme cases when the connection hole is narrow and deep, no conductive thin film is deposited at all at the bottom of the connection hole. For example, in a 16MDRAM, the opening diameter is expected to be 0.5 μm and the depth to be around 1.5 μm. In this case, the aspect ratio will be around 3, and with normal sputtering, the Al alloy film will be at the bottom of the connection hole. It has been confirmed through experiments that it does not accumulate.

【0011】このような段差底部や接続孔の底部におけ
る導電性薄膜の膜厚の不均一性はスパッタで形成したこ
とが原因している。スパッタの場合、膜の堆積速度は、
その点での見込み角にほぼ比例する。このため、見込み
角が極端に小さい段差底部や接続孔の底部では堆積速度
が非常に遅くなり、相対的に薄い導電性薄膜が形成され
膜厚が一定でなくなる。
The non-uniformity of the thickness of the conductive thin film at the bottom of the step or the bottom of the connection hole is caused by the fact that it is formed by sputtering. For sputtering, the film deposition rate is
It is approximately proportional to the viewing angle at that point. For this reason, the deposition rate becomes extremely slow at the bottom of a step or the bottom of a connection hole where the angle of view is extremely small, and a relatively thin conductive thin film is formed, resulting in an uneven film thickness.

【0012】絶縁性薄膜の場合にも同様の困難が生じる
。即ち、配線間のスペースを均一に絶縁性薄膜で生める
ことが困難になり、オーバハング現象が生じる。ひとた
びこの現象が生じると、配線の頂上部での出っ張った絶
縁性薄膜がつながった時点で、反応ガスがそれ以上溝部
に入っていかなくなる。その結果、スペースを生めた絶
縁性薄膜中にいわゆる“巣”と呼ばれる空洞が生じる。
Similar difficulties arise with insulating thin films. That is, it becomes difficult to uniformly create spaces between wirings using an insulating thin film, and an overhang phenomenon occurs. Once this phenomenon occurs, the reaction gas no longer enters the groove once the protruding insulating thin film at the top of the wiring is connected. As a result, a cavity called a "cavity" is created in the insulating thin film that has created the space.

【0013】上述した超LSIの表面のように、凹凸形
状の薄膜表面に更に薄膜を形成する場合には、膜厚の均
一性が重要になってくる。上述した薄膜形成上の問題を
解決するために、均一な膜厚の薄膜を形成する技術の出
現が待たれていた。
[0013] When a thin film is further formed on the uneven surface of the thin film, such as the surface of the VLSI described above, uniformity of the film thickness becomes important. In order to solve the above-mentioned problems in forming thin films, the emergence of a technique for forming thin films with uniform thickness has been awaited.

【0014】近年、均一な膜厚の導電性薄膜の堆積方法
として、減圧化学的気相成長法(LPCVD)で金属膜
を堆積する方法の研究が盛んに行われている。この方法
によれば、系の圧力を減圧にすることにより、いわゆる
ソースガスの“回り込み”効果が顕著に現われ、段差底
部にも原料ガスが十分供給され、段差被覆性に優れた薄
膜が得られる。例えば、DRAMのビット線の抵抗を低
減するためにWSi2 薄膜が実用化されている。即ち
、DRAMのビット線の不純物がドープされたSi膜の
代わりにLPCVD法で形成したWSi2 薄膜を用い
たり、Si膜上にWSi2 薄膜を形成したりすること
で低抵抗化が実現できる。
[0014] In recent years, as a method for depositing a conductive thin film with a uniform thickness, research has been actively conducted on a method of depositing a metal film by low pressure chemical vapor deposition (LPCVD). According to this method, by reducing the pressure of the system, the so-called "wrap-around" effect of the source gas becomes noticeable, and the source gas is sufficiently supplied to the bottom of the step, making it possible to obtain a thin film with excellent step coverage. . For example, WSi2 thin films have been put into practical use to reduce the resistance of DRAM bit lines. That is, lower resistance can be achieved by using a WSi2 thin film formed by LPCVD instead of the impurity-doped Si film of the DRAM bit line, or by forming a WSi2 thin film on the Si film.

【0015】従来よりCVD法で導電性薄膜を形成する
場合に、膜質の制御,不純物の除去,表面の酸化などの
点に問題があったが、最近、原料ガスの純度も改善され
、ロードロック機構を付加したCVD装置も開発されて
表面酸化の問題も少なくなった。
Conventionally, when forming a conductive thin film using the CVD method, there were problems in controlling the film quality, removing impurities, and oxidizing the surface, but recently, the purity of the raw material gas has been improved, and load lock has been achieved. CVD equipment with added mechanisms has also been developed, which has reduced the problem of surface oxidation.

【0016】しかしながら、CVD法ではまだ均一な膜
質の薄膜を溝底部に成膜するのが困難であるため、希弗
酸等を用いたエッチングでは、溝底部の薄膜のエッチン
グ速度が平坦部の薄膜のそれより速くなり、一様にエッ
チングするのが困難であるという問題があった。
However, with the CVD method, it is still difficult to form a thin film of uniform quality on the bottom of the groove, so when etching using dilute hydrofluoric acid, etc., the etching rate of the thin film on the bottom of the groove is lower than that of the thin film on the flat part. The problem was that it was difficult to etch uniformly.

【0017】溝底部,接続孔の低部に薄膜を均一に堆積
する方法として、薄膜の選択成長を利用したものがある
。薄膜の選択成長とは、ある特定の材料を特定の条件で
用いて気相成長させると特定の下地表面上にのみ所望の
薄膜を堆積できる現象をいい、現時点では材料として高
融点金属であるタングステン(W)、モリブデン(Mo
)、チタンシリサイド(TiSi2 )、タンタルシリ
サイド(TaSi2 )、アルミニュウム(Al)、銅
(Cu)、単結晶Siなどが報告されている。
[0017] As a method for uniformly depositing a thin film on the bottom of the groove and the lower part of the connection hole, there is a method using selective growth of the thin film. Selective thin film growth refers to a phenomenon in which a desired thin film can be deposited only on a specific base surface by vapor phase growth using a specific material under specific conditions.Currently, the material used is tungsten, a high melting point metal. (W), molybdenum (Mo
), titanium silicide (TiSi2), tantalum silicide (TaSi2), aluminum (Al), copper (Cu), single crystal Si, etc. have been reported.

【0018】このような気相成長法は、選択CVD法と
呼ばれており、段差部及び接続孔の底部から上部に向か
い薄膜を一様に堆積することができるため、段差部及び
接続孔のアスペクト比の低減化や基板表面の平坦化が実
現できる。
[0018] Such a vapor phase growth method is called a selective CVD method, and it is possible to uniformly deposit a thin film from the bottom to the top of the step portion and connection hole. It is possible to reduce the aspect ratio and flatten the substrate surface.

【0019】デザインルールが小さくなると、微細なパ
ターニングやエッチングが困難になる。このため、必要
な箇所に必要な量だけの薄膜を堆積する選択CVD法は
今後の超LSIの薄膜形成技術として有望である。
[0019] As the design rule becomes smaller, fine patterning and etching become difficult. Therefore, the selective CVD method, which deposits the required amount of thin film at the required location, is promising as a thin film forming technology for future VLSIs.

【0020】また、下地形状をなんらかの方法で決めて
おけば、選択的に堆積する膜は、下地を選ぶために自己
整合的に下地との位置を決めることができ、いわゆるマ
スクの合わせずれなどを考える必要がなく、集積度をあ
げる観点からも、また素子の信頼性をあげる観点からも
有望である。
[0020] Furthermore, if the shape of the base is determined in some way, the selectively deposited film can be positioned with the base in a self-aligned manner to select the base, and so-called misalignment of the mask can be avoided. There is no need to think about it, and it is promising both from the viewpoint of increasing the degree of integration and from the viewpoint of increasing the reliability of the device.

【0021】しかしながら従来の選択CVD法では、表
面化学反応を利用するため、その制御が困難であり、実
用化に至らなかった。
However, the conventional selective CVD method utilizes a surface chemical reaction, which is difficult to control, and has not been put to practical use.

【0022】CVD法を用いないで選択的に薄膜を形成
する方法としてはメッキを利用したものがある。これは
薄膜を堆積する化学種を含む溶液中に基板を浸し、電気
化学的方法により、基板の特定の下地表面に選択的に薄
膜を堆積するというものである。この方法によりCuな
どの薄膜が実現されている。
[0022] As a method for selectively forming a thin film without using the CVD method, there is a method using plating. In this method, a substrate is immersed in a solution containing a chemical species for depositing a thin film, and a thin film is selectively deposited on a specific underlying surface of the substrate by an electrochemical method. A thin film of Cu or the like has been realized by this method.

【0023】しかしながら、メッキ液の純度や堆積した
薄膜の純度、また現在のところCu膜が堆積する下地が
限られていることから実用化には至っていない。
However, this method has not been put into practical use due to the purity of the plating solution, the purity of the deposited thin film, and the limited number of substrates on which the Cu film can be deposited.

【0024】[0024]

【発明が解決しようとする課題】上述の如く、従来の各
種の薄膜の形成方法にはそれなりの効果が観測され有望
視されるが、その欠点も顕著になり、本命視されるもの
はまだない。
[Problems to be Solved by the Invention] As mentioned above, various conventional thin film forming methods have been observed to have certain effects and are considered promising, but their drawbacks have also become noticeable, and no method has yet been considered a favorite. .

【0025】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、基板の所定領域に良質
な薄膜を形成することができる薄膜の形成方法を提供す
ることにある。
The present invention has been made in consideration of the above circumstances, and its object is to provide a thin film forming method that can form a high quality thin film on a predetermined region of a substrate.

【0026】[0026]

【課題を解決するための手段】本発明の骨子は、電気分
極した化合物の所定の原子を電気力で基板上の所定領域
に導き薄膜を成長させることにある。
The gist of the present invention is to guide predetermined atoms of an electrically polarized compound to a predetermined region on a substrate by electric force to grow a thin film.

【0027】即ち、上記の目的を達成するために、本発
明の薄膜の形成方法は、原料ガスを導入し、化学反応に
より基板上に化合物を吸着させて薄膜を形成する薄膜の
形成方法において、化合物として電気分極した化合物を
用いると共に、電気力により化合物の所定の原子を基板
上の所定領域に選択的に導くことを特徴とする。
That is, in order to achieve the above object, the thin film forming method of the present invention involves introducing a raw material gas and adsorbing a compound onto a substrate through a chemical reaction to form a thin film. It is characterized by using an electrically polarized compound as the compound and selectively guiding predetermined atoms of the compound to a predetermined region on the substrate by electric force.

【0028】なお、電気分極した化合物の所定の原子を
電気力で基板上の所定領域に導くには、基板上の所定領
域を帯電させることにより行なうことが望ましい。
[0028] In order to guide the predetermined atoms of the electrically polarized compound to a predetermined region on the substrate by electric force, it is desirable to conduct this by charging the predetermined region on the substrate.

【0029】なお、電気分極した化合物の所定の原子を
電気力で基板上の所定領域に導くには、電場中に基板を
おいて行なうことが望ましい。
Note that in order to guide predetermined atoms of the electrically polarized compound to a predetermined region on the substrate by electric force, it is preferable to place the substrate in an electric field.

【0030】[0030]

【作用】本発明の薄膜の形成方法では、電気分極した化
合物を用いているため、電気力により化合物の所定の原
子を基板上の所定領域に選択的に導くことができる。
[Operation] Since the thin film forming method of the present invention uses an electrically polarized compound, it is possible to selectively guide predetermined atoms of the compound to a predetermined region on a substrate by electric force.

【0031】したがって、膜厚や膜質が均一な薄膜を容
易に所望の領域に堆積することができる。
[0031] Therefore, a thin film having uniform thickness and quality can be easily deposited in a desired region.

【0032】[0032]

【実施例】以下、本発明を図面を用い詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings.

【0033】図1,図2,図3はそれぞれ本発明の第1
の実施例に係わるCu薄膜の形成方法で用いる試料基板
25の厚み方向の断面図,下部電極部における断面図,
上部電極部における断面図である。
FIG. 1, FIG. 2, and FIG. 3 each illustrate the first aspect of the present invention.
A cross-sectional view in the thickness direction of a sample substrate 25 used in the method of forming a Cu thin film according to the embodiment, a cross-sectional view at the lower electrode part,
FIG. 3 is a cross-sectional view of the upper electrode section.

【0034】これを形成工程に従い説明すると、最初、
シリコン基板1上に厚さ約0.2μmの熱酸化膜3を形
成する。
[0034] To explain this according to the forming process, first,
A thermal oxide film 3 having a thickness of approximately 0.2 μm is formed on a silicon substrate 1.

【0035】次にこの熱酸化膜3上にスパッタリング法
を用いて厚さ約0.5μmのAl膜を堆積した後、この
Al膜をパターニングして図2に示すような形状の下部
電極5,7及び外部電源と電気的接続をとるための電極
取り出し部9,11を形成し、熱酸化膜3上に下部電極
部13を形成する。
Next, after depositing an Al film with a thickness of about 0.5 μm on this thermal oxide film 3 using a sputtering method, this Al film is patterned to form a lower electrode 5 having a shape as shown in FIG. 7 and an external power source are formed, and a lower electrode part 13 is formed on the thermal oxide film 3.

【0036】次に全面にプラズマCVD法を用いて厚さ
約0.1μmの二酸化シリコン膜15を形成した後、こ
の二酸化シリコン膜15上に厚さ約0.5μmのAl膜
をスパッタリング法を用いて堆積する。次いでこのAl
膜をパターニングして図3に示すような下部電極5,7
に対向する上部電極17,19を形成し、二酸化シリコ
ン膜15上に上部電極部21を形成する。
Next, a silicon dioxide film 15 with a thickness of about 0.1 μm is formed on the entire surface using a plasma CVD method, and then an Al film with a thickness of about 0.5 μm is formed on this silicon dioxide film 15 using a sputtering method. and deposit. Then this Al
The film is patterned to form lower electrodes 5 and 7 as shown in FIG.
Upper electrodes 17 and 19 facing each other are formed, and an upper electrode portion 21 is formed on the silicon dioxide film 15.

【0037】最後に、フォトリソグラフィ,反応性スパ
ッタリングを用いて下部電極部13の電極取り出し部9
,11上の二酸化シリコン膜15に接続孔23を設けて
試料基板25が完成する。
Finally, the electrode extraction portion 9 of the lower electrode portion 13 is formed using photolithography and reactive sputtering.
, 11 are provided with connection holes 23 in the silicon dioxide film 15 to complete the sample substrate 25.

【0038】以上のようにして形成して得られた試料基
板25をCVD装置に搬入して成膜を行なう。
The sample substrate 25 formed as described above is carried into a CVD apparatus to form a film.

【0039】図5はこのCVD装置の構成を示す概略断
面図である。膜形成室29の内部には試料基板25を載
置したサセプタ31が収容されており、この上に試料基
板25が載置されている。このサセプタ31の内部には
、試料基板25を加熱するための、例えば、ヒータ等か
らなる加熱源33が設けられている。
FIG. 5 is a schematic sectional view showing the structure of this CVD apparatus. A susceptor 31 on which a sample substrate 25 is placed is housed inside the film forming chamber 29, and the sample substrate 25 is placed on top of the susceptor 31. A heat source 33 made of, for example, a heater is provided inside the susceptor 31 to heat the sample substrate 25 .

【0040】膜形成室29の上部にはサセプタ31に対
向して上下に可動できるステンレス製の放電用電極35
及びこの放電用電極35の開口部を挿通して上下に可動
し、下部電極部13の電極取り出し部9,11に接触し
てこれら電極取り出し部9,11をそれぞれ異なる極性
に帯電させるための帯電用電極37,39が設けられて
いる。
At the upper part of the film forming chamber 29, there is a discharge electrode 35 made of stainless steel that faces the susceptor 31 and is movable up and down.
A charging member is inserted through the opening of the discharge electrode 35, moves up and down, contacts the electrode extraction parts 9 and 11 of the lower electrode part 13, and charges the electrode extraction parts 9 and 11 to different polarities. electrodes 37 and 39 are provided.

【0041】膜形成室29の外部にはガス供給部41,
ガス排気部43が設けられている。ガス供給部41はス
テンレス製のBCl3 ボンベ,窒化銅(CuN)ボン
ベ,N2 ボンベ等からなる。
Outside the film forming chamber 29, a gas supply section 41,
A gas exhaust section 43 is provided. The gas supply section 41 includes a stainless steel BCl3 cylinder, a copper nitride (CuN) cylinder, an N2 cylinder, and the like.

【0042】BCl3 ボンベは配管45を介して膜形
成室29に接続されている。なお、BCl3 ガスの膜
形成室29への導入は配管45に設けられたバルブ47
の開け閉めにより制御される。同様にしてCuNボンベ
,N2 ボンベに対してそれぞれ配管49,53及びバ
ルブ51,55が設けられている。
The BCl3 cylinder is connected to the film forming chamber 29 via a pipe 45. The BCl3 gas is introduced into the film forming chamber 29 through a valve 47 provided in the pipe 45.
Controlled by opening and closing. Similarly, pipes 49 and 53 and valves 51 and 55 are provided for the CuN cylinder and the N2 cylinder, respectively.

【0043】ガス排気部43は排気ポンプ等からなり、
ゲートバルブ57を介して膜形成室29に接続されてい
る。
[0043] The gas exhaust section 43 consists of an exhaust pump, etc.
It is connected to the film forming chamber 29 via a gate valve 57.

【0044】次にこのように構成されたCVD装置27
を用いたCu膜の形成方法を説明する。
Next, the CVD apparatus 27 configured as described above
A method for forming a Cu film using the following will be explained.

【0045】先ず、ゲートバルブ57を開きガス排気部
43により膜形成室29内のガスを排気し、膜形成室2
9内の圧力を約1×10−7Torr以下まで減圧する
First, the gate valve 57 is opened and the gas in the film forming chamber 29 is exhausted by the gas exhaust section 43.
Reduce the pressure inside 9 to about 1 x 10-7 Torr or less.

【0046】次にバルブ47を開きガス供給部41のB
Cl3 ガスを膜形成室29内に導入すると共に、放電
用電極35とサセプタ31との間に高周波電圧を印加し
て放電を起こし、上部電極17,19の表面を除去する
。 これはAl膜のパターニングの際に生じたダメージ層や
自然酸化膜を除去するための処理である。なお、この目
的のためには、例えば、Arプラズマを発生させ、Ar
イオンにより上部電極17,19の表面を除去するなど
他の方法を用いてもよい。
Next, the valve 47 is opened and the gas supply section 41 is
Cl3 gas is introduced into the film forming chamber 29, and a high frequency voltage is applied between the discharge electrode 35 and the susceptor 31 to generate a discharge, thereby removing the surfaces of the upper electrodes 17 and 19. This is a process for removing the damaged layer and natural oxide film generated during patterning of the Al film. Note that for this purpose, for example, Ar plasma is generated and Ar
Other methods may be used, such as removing the surfaces of the upper electrodes 17 and 19 using ions.

【0047】次にバルブ45を閉じ排気部43により膜
形成室29内のガスを再び排気し、膜形成室29内の圧
力を1×10−7Torr以下にした後、加熱源33に
電圧を印加して試料基板25を加熱し、試料基板25の
表面温度を350℃にする。
Next, the valve 45 is closed and the gas in the film forming chamber 29 is exhausted again by the exhaust section 43, and after the pressure in the film forming chamber 29 is reduced to 1×10 −7 Torr or less, a voltage is applied to the heating source 33 . The sample substrate 25 is heated to bring the surface temperature of the sample substrate 25 to 350°C.

【0048】次に帯電用電極37,39を下ろして帯電
用電極37,39をそれぞれ試料基板25の電極取り出
し部9,11に接触させた後、直流電源(不図示)によ
り帯電用電極37,39にそれぞれ+100V,−10
0Vの直流電圧を印加する。この結果、静電誘導により
試料基板25の上部電極17,19の表面にはそれぞれ
正電荷,負電荷が誘起される。なお、このときの状態は
図4に示される電気回路図で表わすことができる。
Next, after lowering the charging electrodes 37 and 39 and bringing them into contact with the electrode extraction parts 9 and 11 of the sample substrate 25, respectively, the charging electrodes 37 and 39 are removed by a DC power source (not shown). 39 +100V, -10 respectively
Apply a DC voltage of 0V. As a result, positive charges and negative charges are induced on the surfaces of the upper electrodes 17 and 19 of the sample substrate 25, respectively, due to electrostatic induction. Note that the state at this time can be represented by the electrical circuit diagram shown in FIG.

【0049】次にガス供給部41のCuNボンベ中のC
uNの蒸気圧を上げると共に、配管49中での再凝縮を
防止するためにCuNボンベと配管49とをヒーターで
加熱し250℃に保持し、試料基板25の表面温度が3
50℃に安定したことを確認してバルブ51を開き、A
rをキャリアガスに用いてCuNガスを膜形成室29の
導入し、この状態を30分間保持し、Cu薄膜の成膜を
行なう。このときの膜形成室29内の圧力は1×10−
3〜1x10−2Torr程度であった。
Next, the C in the CuN cylinder of the gas supply section 41
In order to increase the vapor pressure of uN and prevent recondensation in the pipe 49, the CuN cylinder and the pipe 49 are heated with a heater and maintained at 250°C, and the surface temperature of the sample substrate 25 is raised to 3.
After confirming that the temperature has stabilized at 50°C, open valve 51 and
CuN gas is introduced into the film forming chamber 29 using r as a carrier gas, and this state is maintained for 30 minutes to form a Cu thin film. At this time, the pressure inside the film forming chamber 29 is 1×10−
It was about 3 to 1×10 −2 Torr.

【0050】次にバルブ51を閉じCuN/Arガスの
供給を停止した後、ゲートバルブ57を開けてガス排出
部43により膜形成室29内のガスを排気して膜形成室
29内の圧力を10分間1×10−7Torr以下に保
持する。
Next, after closing the valve 51 and stopping the supply of CuN/Ar gas, the gate valve 57 is opened and the gas in the film forming chamber 29 is exhausted by the gas exhaust section 43 to reduce the pressure in the film forming chamber 29. Maintain the pressure below 1×10 −7 Torr for 10 minutes.

【0051】最後に、ゲートバルブ57を閉じた後にバ
ルブ55を開いて乾燥N2 ガスを膜形成室29の導入
し、膜形成室29内の圧力を大気圧程度にしてCu薄膜
の形成が終わる。
Finally, after closing the gate valve 57, the valve 55 is opened to introduce dry N2 gas into the film forming chamber 29, and the pressure in the film forming chamber 29 is brought to about atmospheric pressure, thereby completing the formation of the Cu thin film.

【0052】以上の工程を経た試料基板25を取り出し
て見ると、試料基板25の上部電極17,19上には色
の変化から目視で薄膜が堆積していることが確認された
When the sample substrate 25 that had undergone the above steps was taken out and looked at, it was confirmed visually that a thin film had been deposited on the upper electrodes 17 and 19 of the sample substrate 25 from a change in color.

【0053】次いでこのCu薄膜を定量分析及び定性分
析にかけて調べたところ、上部電極17,19上にはC
u薄膜が堆積しており、電極板17,19上のCu薄膜
の膜厚は共に約0.5μmであり、実験誤差以内で一致
した。
Next, this Cu thin film was examined by quantitative analysis and qualitative analysis, and it was found that carbon was present on the upper electrodes 17 and 19.
A thin Cu film was deposited on the electrode plates 17 and 19, and the thicknesses of the Cu thin films on the electrode plates 17 and 19 were both approximately 0.5 μm, which coincided within experimental error.

【0054】しかしながら、上部電極17(正電荷が帯
電)上に堆積したCu薄膜中のNの含有量は、上部電極
19(負電荷が帯電)上に堆積したCu薄膜中のNの含
有量よりも30〜50倍多かった。
However, the N content in the Cu thin film deposited on the upper electrode 17 (positively charged) is lower than the N content in the Cu thin film deposited on the upper electrode 19 (negatively charged). It was also 30 to 50 times more common.

【0055】次に本発明の第2の実施例に係るCu薄膜
の形成方法を説明する。
Next, a method for forming a Cu thin film according to a second embodiment of the present invention will be described.

【0056】この実施例が先に説明した第1の実施例と
異なる点は、上部電極17,19の帯電状態を変えてC
u薄膜の形成を行なったことにある。
This embodiment differs from the first embodiment described above by changing the charging state of the upper electrodes 17 and 19.
The reason is that a u thin film was formed.

【0057】即ち、帯電用電極39のみを試料基板25
の電極取り出し部11に接触させた後、この電極取り出
し部11に−100Vの電圧を印加し、上部電極19に
負電荷を帯電させて膜形成を行なったことにある。
That is, only the charging electrode 39 is connected to the sample substrate 25.
After the upper electrode 19 was brought into contact with the electrode extraction part 11, a voltage of -100V was applied to the electrode extraction part 11 to charge the upper electrode 19 with a negative charge to form a film.

【0058】このような帯電状態で得られたCu薄膜を
調べたところ、上部電極17(帯電無し)上には厚さ約
0.1μmのCu薄膜が形成され、上部電極19(負電
荷が帯電)上には厚さ約0.5μmのCu薄膜が形成さ
れていた。
When the Cu thin film obtained in such a charged state was examined, a Cu thin film with a thickness of about 0.1 μm was formed on the upper electrode 17 (uncharged), and a Cu thin film with a thickness of about 0.1 μm was formed on the upper electrode 19 (negatively charged). ) A thin Cu film with a thickness of about 0.5 μm was formed on the top.

【0059】以上の述べた第1及び第2の実施例で示さ
れた事実は次のように考察される。CuとNの電気陰性
度はそれぞれ1.9(Cu),3.0(N)であるのた
め、CuN化合物はN原子がδ− にCu原子がδ+ 
に分極しており、CuN化合物は全体として電気双極子
を形成している。
The facts shown in the first and second embodiments described above can be considered as follows. The electronegativities of Cu and N are 1.9 (Cu) and 3.0 (N), respectively, so in a CuN compound, the N atom is δ- and the Cu atom is δ+.
The CuN compound as a whole forms an electric dipole.

【0060】したがって、第1の実施例のように上部電
極17が正に帯電し、上部電極19が負に帯電している
場合には、CuN化合物は図6(a),(b)に示され
るような形で上部電極17,19の表面に付着する。即
ち、静電引力のため上部電極17の表面のAl原子とC
uN化合物のN原子とが優先的に結合し、上部電極19
の表面のAl原子とCuN化合物のCu原子とが優先的
に結合する。
Therefore, when the upper electrode 17 is positively charged and the upper electrode 19 is negatively charged as in the first embodiment, the CuN compound becomes as shown in FIGS. 6(a) and 6(b). It is attached to the surfaces of the upper electrodes 17 and 19 in such a manner that it is exposed. That is, due to electrostatic attraction, Al atoms on the surface of the upper electrode 17 and C
The N atom of the uN compound is preferentially bonded to the upper electrode 19.
The Al atoms on the surface of the CuN compound bond preferentially to the Cu atoms of the CuN compound.

【0061】しかしながら、試料基板25の表面温度(
350℃)は、CuN化合物の分解温度(約300℃)
より高いのでCuN化合物はしだいに分解する。このと
き、表面に正の電荷が帯電した上部電極17上のN原子
は、試料基板25の表面のAl原子とCu原子との間に
はさまれ脱離しにくい状態にあるため、上部電極17上
に堆積したCu薄膜中のN原子の含有量が多くなる。
However, the surface temperature of the sample substrate 25 (
350℃) is the decomposition temperature of the CuN compound (approximately 300℃)
Since it is higher, the CuN compound gradually decomposes. At this time, the N atoms on the upper electrode 17 whose surface is positively charged are sandwiched between the Al atoms and Cu atoms on the surface of the sample substrate 25 and are difficult to desorb. The content of N atoms in the Cu thin film deposited increases.

【0062】一方、表面に負電荷が帯電した上部電極1
9上のN原子は、真空側に面しているのでN原子同士が
結合して脱離しやすい状態にあるため、上部電極19上
に堆積したCu薄膜中のN原子の含有量は少なくなる。
On the other hand, the upper electrode 1 whose surface is negatively charged
Since the N atoms on the upper electrode 9 face the vacuum side, the N atoms are likely to bond with each other and desorb, so that the content of N atoms in the Cu thin film deposited on the upper electrode 19 decreases.

【0063】また、第2の実施例のように上部電極17
が無帯電、上部電極19が負に帯電している場合、上部
電極17上に堆積するCu膜の厚さは、基板温度で決ま
るCuN化合物と上部電極17の表面のAl原子との付
着確率でほぼ決まる。即ち、CuN化合物と試料基板2
1表面との間の静電引力によるCu膜堆積の助勢効果が
なくなる。したがって、表面に負電荷が帯電した上部電
極19上には厚さ約0.5μmのCu薄膜が堆積される
が、無帯電の上部電極17上には厚さ約0.1μmのC
u薄膜しか堆積しないことになる。
Furthermore, as in the second embodiment, the upper electrode 17
When is uncharged and the upper electrode 19 is negatively charged, the thickness of the Cu film deposited on the upper electrode 17 is determined by the adhesion probability between the CuN compound and the Al atoms on the surface of the upper electrode 17, which is determined by the substrate temperature. Almost decided. That is, the CuN compound and the sample substrate 2
The effect of promoting Cu film deposition due to electrostatic attraction between the two surfaces disappears. Therefore, a Cu thin film with a thickness of about 0.5 μm is deposited on the upper electrode 19 whose surface is negatively charged, whereas a Cu thin film with a thickness of about 0.1 μm is deposited on the uncharged upper electrode 17.
Only the u thin film will be deposited.

【0064】次に本発明の第3の実施例に係るCu薄膜
の形成方法を説明する。
Next, a method for forming a Cu thin film according to a third embodiment of the present invention will be described.

【0065】図7(a)には本実施例で用いる試料基板
25の断面図が示されている。なお、図1の試料基板2
5と対応する部分には図1と同一符号を付し、詳細な説
明は省略する。
FIG. 7(a) shows a cross-sectional view of the sample substrate 25 used in this example. Note that the sample substrate 2 in FIG.
Portions corresponding to 5 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

【0066】この試料基板25を形成工程に従い説明す
ると、最初、シリコン基板1上に厚さ約0.2μmの熱
酸化膜3を形成する。次いでスパッタリング法を用いて
熱酸化膜3上にAl膜を堆積した後、このAl膜の基板
周辺部分を除去し、図7(b)に示すような形状の電極
板59を形成する。
To explain the formation process of this sample substrate 25, first, a thermal oxide film 3 with a thickness of about 0.2 μm is formed on a silicon substrate 1. Next, an Al film is deposited on the thermal oxide film 3 using a sputtering method, and then a portion of the Al film around the substrate is removed to form an electrode plate 59 having a shape as shown in FIG. 7(b).

【0067】次にCVD装置27の帯電用電極37を、
図8(a)に示すような一部が欠けた円板状の電極を備
えた帯電用電極37aに代える。この帯電用電極37a
の円板状電極部はステンレス製であり、厚さ約100μ
mの二酸化シリコン膜が被覆されている。また、この帯
電用電極37aを下げると、図8(b)に示すように電
極板59に接触するように配置される。
Next, the charging electrode 37 of the CVD device 27 is
The charging electrode 37a is replaced with a charging electrode 37a having a partially chipped disk-shaped electrode as shown in FIG. 8(a). This charging electrode 37a
The disc-shaped electrode part is made of stainless steel and has a thickness of approximately 100μ.
m silicon dioxide film is coated. Further, when the charging electrode 37a is lowered, it is placed so as to contact the electrode plate 59 as shown in FIG. 8(b).

【0068】次にこのような変更を受けたCVD装置の
サセプタ31に試料基板25を載置した後、第1の実施
例と同様に膜形成室29内のガスを排気し、プラズマに
より試料基板25の電極59のダメージ層及び自然酸化
膜を除去する。このときプラズマが帯電用電極37aの
影響を受けないように、帯電用電極37aを電極板59
にだぶらない位置に退避させ、電極59の全面がプラズ
マに一様に晒されるようにする。
Next, after placing the sample substrate 25 on the susceptor 31 of the CVD apparatus modified as described above, the gas in the film forming chamber 29 is evacuated as in the first embodiment, and the sample substrate is removed by plasma. The damaged layer and natural oxide film of the electrode 59 of No. 25 are removed. At this time, the charging electrode 37a is connected to the electrode plate 59 so that the plasma is not affected by the charging electrode 37a.
The electrode 59 is evacuated to a position where it does not overlap so that the entire surface of the electrode 59 is uniformly exposed to plasma.

【0069】次に加熱源33により試料基板25を加熱
して試料基板25の表面温度を350℃にし、表面温度
が安定したら帯電用電極37a,39を試料基板25の
電極59に接触させ、次いで帯電用電極37aに+10
0Vの直流電圧を印加すると共に、帯電用電極39をア
ース電位に落とした。この結果、静電誘導により帯電用
電極37aに対向する電極59の表面には負電荷が現わ
れる。なお、正電荷は帯電用電極39を介して電極59
から流れ出てなくなる。
Next, the sample substrate 25 is heated by the heat source 33 to bring the surface temperature of the sample substrate 25 to 350° C. Once the surface temperature is stabilized, the charging electrodes 37a and 39 are brought into contact with the electrode 59 of the sample substrate 25, and then +10 to charging electrode 37a
While applying a DC voltage of 0 V, the charging electrode 39 was lowered to the ground potential. As a result, negative charges appear on the surface of the electrode 59 facing the charging electrode 37a due to electrostatic induction. Note that the positive charge is transferred to the electrode 59 via the charging electrode 39.
It flows out and disappears.

【0070】しかる後、帯電用電極39を電極59から
離し、次いで帯電用電極37aに電圧を印加するのを止
め、帯電用電極37aを電極59から離す。この結果、
電極59には負の電荷が帯電する。
Thereafter, the charging electrode 39 is separated from the electrode 59, and then the application of voltage to the charging electrode 37a is stopped, and the charging electrode 37a is separated from the electrode 59. As a result,
The electrode 59 is negatively charged.

【0071】最後に第1の実施例で説明した方法と同様
にして電極59上にCu薄膜を堆積する。
Finally, a Cu thin film is deposited on the electrode 59 in the same manner as described in the first embodiment.

【0072】以上の方法で得られた電極59(負電荷が
帯電)上のCu薄膜の膜厚を調べたところ約0.3μm
であることが確認された。
When the thickness of the Cu thin film on the electrode 59 (negatively charged) obtained by the above method was examined, it was approximately 0.3 μm.
It was confirmed that

【0073】図9(a)には本発明の第4の実施例に係
わるCu薄膜の形成方法に用いる試料基板25の断面図
が示されている。なお、図1の試料基板25と対応する
部分には図1と同一符号を付し、詳細な説明は省略する
FIG. 9(a) shows a cross-sectional view of a sample substrate 25 used in a method for forming a Cu thin film according to a fourth embodiment of the present invention. Note that portions corresponding to the sample substrate 25 in FIG. 1 are given the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

【0074】これを形成工程に従い説明すると、最初、
シリコン基板1上に厚さ約0.2μmの熱酸化膜3を形
成し、次いでこの熱酸化膜3上にスパッタリング法によ
り厚さ約0.5μmのAl膜を堆積する。
[0074] To explain this according to the forming process, first,
A thermal oxide film 3 with a thickness of about 0.2 μm is formed on the silicon substrate 1, and then an Al film with a thickness of about 0.5 μm is deposited on the thermal oxide film 3 by sputtering.

【0075】次にAl膜の基板周辺部分を除去して電極
61を形成した後、プラズマCVD法を用いて厚さ約0
.2μmの二酸化シリコン膜15を全面に堆積する。
Next, the electrode 61 is formed by removing the Al film around the substrate, and then the electrode 61 is formed to a thickness of about 0 using the plasma CVD method.
.. A 2 μm silicon dioxide film 15 is deposited over the entire surface.

【0076】最後に図9(b)に示すように電気的導通
をとるための接続孔23を二酸化シリコン膜15に設け
る。
Finally, as shown in FIG. 9(b), a connection hole 23 for establishing electrical continuity is provided in the silicon dioxide film 15.

【0077】このようにして得られた試料基板25をC
VD装置27のサセプタ31に載置し、第3の実施例と
同じ手順,方法,条件(ただし、基板温度は350℃か
ら450℃へ変更)でCu薄膜の成膜を行なう。
The sample substrate 25 thus obtained was
It is placed on the susceptor 31 of the VD device 27, and a Cu thin film is formed using the same procedure, method, and conditions as in the third embodiment (however, the substrate temperature is changed from 350° C. to 450° C.).

【0078】以上の方法で得られたCu薄膜を調べたと
ころ、二酸化シリコン膜15上にもCu薄膜が堆積して
おり、その膜厚は約0.3μmであった。
When the Cu thin film obtained by the above method was examined, it was found that the Cu thin film was also deposited on the silicon dioxide film 15, and its thickness was about 0.3 μm.

【0079】比較のため、電極板61に負電荷を帯電さ
せないでCu薄膜の成膜を行ない、負電荷を帯電させた
場合と負電荷を帯電させない場合とを比較したところ、
堆積速度の点では両者に顕著の差はみられなかったが、
Cu薄膜の二酸化シリコン膜15に対する付着性や密着
性に関しては負電荷を帯電させた場合の方がはるかに優
れていた。
For comparison, a Cu thin film was formed without charging the electrode plate 61 with a negative charge, and the results were compared between the case where the electrode plate 61 was charged with a negative charge and the case where it was not charged with a negative charge.
Although there was no significant difference between the two in terms of deposition rate,
Regarding the adhesion and adhesion of the Cu thin film to the silicon dioxide film 15, the case where the Cu thin film was negatively charged was far superior.

【0080】次に本発明の第5の実施例に係るCu薄膜
の形成方法を説明する。この実施例が先に説明した第1
〜第4の実施例と主に異なる点は、試料基板25を電場
中においてCu薄膜を形成することにある。
Next, a method for forming a Cu thin film according to a fifth embodiment of the present invention will be described. This example is the first example described above.
The main difference from the fourth embodiment is that a Cu thin film is formed on the sample substrate 25 in an electric field.

【0081】最初、図10に示すような試料基板25を
用意する。
First, a sample substrate 25 as shown in FIG. 10 is prepared.

【0082】これを製造工程に従い説明すると、通常の
方法に従いシリコン基板63に素子分離を行ないMOS
トランジスタを形成した後、所定パターンの絶縁膜、例
えば厚さ約1.4μmの酸化膜65をシリコン基板63
上に形成する。
To explain this according to the manufacturing process, element isolation is performed on the silicon substrate 63 according to the usual method, and MOS
After forming the transistor, a predetermined pattern of an insulating film, for example, an oxide film 65 with a thickness of about 1.4 μm, is placed on the silicon substrate 63.
Form on top.

【0083】次にAl合金膜をマグネトロンスパッタリ
ング等を用いて全面に堆積した後、通常のフォトリソグ
ラフィと反応性イオンエッチングとを用いてAl合金膜
をパターニングして所定形状の配線67を形成する。
Next, an Al alloy film is deposited over the entire surface using magnetron sputtering or the like, and then the Al alloy film is patterned using ordinary photolithography and reactive ion etching to form wiring 67 in a predetermined shape.

【0084】最後にプラズマCVD法を用いて全面に層
間絶縁膜としてシリコン酸化膜69を堆積すると共に、
レジストエッチバック,ラッピングなどによりシリコン
酸化膜69の表面を平坦化する。次いでフォトリソグラ
フィと反応性イオンエッチングとを用いて層間接続孔7
1を形成して試料基板25が完成する。
Finally, a silicon oxide film 69 is deposited as an interlayer insulating film over the entire surface using the plasma CVD method, and
The surface of the silicon oxide film 69 is planarized by resist etchback, lapping, or the like. Next, the interlayer connection hole 7 is formed using photolithography and reactive ion etching.
1 is formed to complete the sample substrate 25.

【0085】このようにして得られた試料基板25では
、層間接続孔71の形成工程で、層間接続孔71の底部
のAl合金膜表面73が、反応性イオンエッチングに用
いるエッチングガス、例えば、フッ素(F)、炭素(C
)を取り込むため、このAl合金膜表面73にはダメー
ジ層が形成されている。更に、そのAl合金膜表面73
には、空気中の酸素で酸化されるので酸化膜も形成され
ている。
In the sample substrate 25 thus obtained, in the step of forming the interlayer connection hole 71, the Al alloy film surface 73 at the bottom of the interlayer connection hole 71 was exposed to an etching gas used for reactive ion etching, for example, fluorine. (F), carbon (C
), a damaged layer is formed on the surface 73 of this Al alloy film. Furthermore, the Al alloy film surface 73
Because it is oxidized by oxygen in the air, an oxide film is also formed on it.

【0086】次に図5のCVD装置27の放電用電極3
5を水冷ができるような電極いわゆる水冷電極に換える
。但し、サセプタ31に対向して上下に可動できるもの
を用いる。
Next, the discharge electrode 3 of the CVD apparatus 27 in FIG.
5 is replaced with an electrode that can be water-cooled, a so-called water-cooled electrode. However, one that can move up and down facing the susceptor 31 is used.

【0087】次にこのように変更されたCVD装置27
のサセプタ31に試料基板25を載置した後、ゲートバ
ルブ57を開いてガス排気部43により膜形成室29内
の圧力を1×10−7Torr以下に減圧する。
Next, the CVD apparatus 27 modified in this way
After placing the sample substrate 25 on the susceptor 31 , the gate valve 57 is opened and the pressure inside the film forming chamber 29 is reduced to 1×10 −7 Torr or less by the gas exhaust section 43 .

【0088】次に水冷電極を試料基板25の表面から約
150mm離れた位置に固定した後、第1の実施例と同
様にしてBCl3 プラズマを発生させ、Al合金膜表
面73をエッチングしてダメージ層,酸化膜を除去する
Next, after fixing the water-cooled electrode at a position approximately 150 mm away from the surface of the sample substrate 25, BCl3 plasma is generated in the same manner as in the first embodiment to etch the Al alloy film surface 73 and remove the damaged layer. , remove the oxide film.

【0089】次にプラズマガス等を排気するために再び
膜形成室29内の圧力を1×10−7Torr以下に減
圧し、次いで加熱源33に電圧を印加して試料基板25
を加熱し、その表面温度を350℃にする。
Next, in order to exhaust plasma gas etc., the pressure inside the film forming chamber 29 is again reduced to 1×10 −7 Torr or less, and then a voltage is applied to the heating source 33 to remove the sample substrate 25 .
is heated to a surface temperature of 350°C.

【0090】次に水冷電極を試料基板25側に近づけ、
試料基板25と水冷電極との間隔を30mmとした後、
水冷電極に+1kVの直流電圧を印加すると共に、膜形
成室29及びサセプタ31をアース電位に落とした。こ
のとき水冷電極と膜形成室29及びサセプタ31との間
で放電が生じないように注意する。
Next, bring the water-cooled electrode close to the sample substrate 25 side,
After setting the distance between the sample substrate 25 and the water-cooled electrode to 30 mm,
A DC voltage of +1 kV was applied to the water-cooled electrode, and the film forming chamber 29 and susceptor 31 were lowered to earth potential. At this time, care must be taken to prevent discharge from occurring between the water-cooled electrode, the film forming chamber 29, and the susceptor 31.

【0091】このようして発生する電場の強さは、サセ
プタ31の実効的な電極面積が正確に見積れないので正
確には算出できないが、試料基板25と水冷電極との間
には約+300V/cmのほぼ均一な電界がかかってい
る。この場合、電気力線は、水冷電極から試料基板25
に向かう方向に走っている。
The strength of the electric field generated in this way cannot be calculated accurately because the effective electrode area of the susceptor 31 cannot be accurately estimated, but it is approximately +300 V between the sample substrate 25 and the water-cooled electrode. A substantially uniform electric field of /cm is applied. In this case, electric lines of force flow from the water-cooled electrode to the sample substrate 25.
running in the direction of

【0092】次に第1の実施例と同じ条件、手順でCu
N/Arガスを膜形成室29内に導入し、試料基板25
上にCu薄膜を堆積する。このとき、水冷電極の表面に
はCuNが再凝縮したものとみられるものが薄く局所的
に堆積していた。
Next, under the same conditions and procedures as in the first example, Cu
N/Ar gas is introduced into the film forming chamber 29, and the sample substrate 25 is
A Cu thin film is deposited on top. At this time, a thin layer of what appeared to be recondensed CuN was locally deposited on the surface of the water-cooled electrode.

【0093】図11には層間接続孔71が位置する領域
に堆積したCu薄膜75が示されている。
FIG. 11 shows a Cu thin film 75 deposited in the region where the interlayer connection hole 71 is located.

【0094】Cu薄膜75はシリコン基板63の全面に
堆積したが、その厚さは配線67上では約0.4μm、
層間絶縁膜であるシリコン酸化膜69上では約0.05
μmであった。即ち、Cu薄膜75の膜厚には下地依存
性があり、層間接続孔71の露出しているAl合金膜表
面73、つまり溝部から優先的にCu薄膜75が堆積す
る。
The Cu thin film 75 was deposited on the entire surface of the silicon substrate 63, and its thickness was about 0.4 μm on the wiring 67.
Approximately 0.05 on the silicon oxide film 69, which is an interlayer insulating film.
It was μm. That is, the thickness of the Cu thin film 75 is dependent on the underlying layer, and the Cu thin film 75 is preferentially deposited from the exposed Al alloy film surface 73 of the interlayer connection hole 71, that is, from the groove portion.

【0095】また、Cu薄膜75中のN含有率を調べた
ところ8atomic%以下であることが分かった。
Further, when the N content in the Cu thin film 75 was examined, it was found to be 8 atomic % or less.

【0096】更に、Cu薄膜75のX線回折強度も調べ
てみた。その結果、ミラー指数(111)方向の回折強
度が強かった。即ち、Cu薄膜75はミラー指数(11
1)方向に強く配向していることが分かった。なお、バ
ルクのCu薄膜のX線回折強度を調べたところ、ミラー
指数(111),(200),(220)方向の回折強
度比は1:0.46:0.20であった。つまり、バル
クのCu薄膜はこれらの方向に一様に配向していた。
Furthermore, the X-ray diffraction intensity of the Cu thin film 75 was also investigated. As a result, the diffraction intensity in the Miller index (111) direction was strong. That is, the Cu thin film 75 has a Miller index (11
1) was found to be strongly oriented in the direction. When the X-ray diffraction intensity of the bulk Cu thin film was examined, the diffraction intensity ratio in the Miller index (111), (200), and (220) directions was 1:0.46:0.20. In other words, the bulk Cu thin film was uniformly oriented in these directions.

【0097】比較例として、サセプタ31のみをアース
電位に落とし、水冷電極に−1kVを印加して電気力線
が走る向きを逆(試料基板25から水冷電極に向かう方
向)にして上記実施例と同様にしてCu薄膜の成膜実験
を行なった。その結果、Cu薄膜の膜厚は下地依存性を
示さず、Cu薄膜の堆積速度も遅くなった。なお、配線
67,シリコン酸化膜69上に堆積されたCu薄膜の膜
厚はともに0.1μm程度であった。また、Cu薄膜の
窒素含有量も上記実施例のそれより多く、著しい場合に
は30atomic%になる場合もあった。
As a comparative example, only the susceptor 31 was lowered to the ground potential, -1 kV was applied to the water-cooled electrode, and the direction in which the electric lines of force ran was reversed (from the sample substrate 25 to the water-cooled electrode). A Cu thin film deposition experiment was conducted in the same manner. As a result, the thickness of the Cu thin film did not show dependence on the underlying layer, and the deposition rate of the Cu thin film also became slow. Note that the thicknesses of the Cu thin films deposited on the wiring 67 and the silicon oxide film 69 were both about 0.1 μm. Further, the nitrogen content of the Cu thin film was also higher than that of the above example, and in some cases it was as high as 30 atomic%.

【0098】以上述べた本実施例及び比較例の結果は次
のように考察できる。
The results of the present example and comparative example described above can be considered as follows.

【0099】CuN化合物は配管51の出口から排気部
43の排気孔までの高圧から低圧の領域に沿って基本的
には流れる。しかし、試料基板25においては、試料基
板25が加熱されていると共に水冷電極に電圧が印加さ
れているため、圧力差以外に、濃度差に基づく拡散現象
及び電場の強度とCuN化合物の電気分極の強度との積
に比例した力に従ってCuN化合物が試料基板25の表
面方向に流れる。
[0099] The CuN compound basically flows along the region from the high pressure to the low pressure from the outlet of the pipe 51 to the exhaust hole of the exhaust section 43. However, in the sample substrate 25, since the sample substrate 25 is heated and a voltage is applied to the water-cooled electrode, in addition to the pressure difference, there is a diffusion phenomenon based on the concentration difference, the intensity of the electric field, and the electric polarization of the CuN compound. The CuN compound flows toward the surface of the sample substrate 25 according to a force proportional to the product of the strength and the force.

【0100】先に説明したようにCuN化合物はN原子
がδ− にCu原子がδ+ に分極している。このため
、本実施例のように電気力線が水冷電極から試料基板2
5に走っている場合には、Cu原子が試料基板25側を
向き、N原子が真空側を向くようにCuN化合物が配向
するので、試料基板25の表面にはCuN化合物の原子
がが優先的に吸着する。
As explained above, in the CuN compound, the N atoms are polarized to δ- and the Cu atoms are polarized to δ+. For this reason, as in this example, lines of electric force flow from the water-cooled electrode to the sample substrate 2.
5, the CuN compound is oriented so that the Cu atoms face the sample substrate 25 side and the N atoms face the vacuum side, so atoms of the CuN compound preferentially appear on the surface of the sample substrate 25. adsorbs to.

【0101】したがって、CuN化合物の熱分解が生じ
ると、N原子は容易にN2 ガスとなり試料基板25か
ら離れるため、Cu薄膜75中のN含有量が少なくなる
と考えられる。更に、水冷電極とサセプタ31との間に
電圧が印加されていることにより配線67上には静電誘
導で負電荷が生じ、Cu薄膜75の堆積を助長する効果
も加わっていると考えられる。
[0101] Therefore, when thermal decomposition of the CuN compound occurs, N atoms easily become N2 gas and separate from the sample substrate 25, so it is thought that the N content in the Cu thin film 75 decreases. Furthermore, since a voltage is applied between the water-cooled electrode and the susceptor 31, negative charges are generated on the wiring 67 by electrostatic induction, which is considered to have an additional effect of promoting the deposition of the Cu thin film 75.

【0102】また、配向性が強いCu薄膜75が得られ
たのは、CuN化合物が整然と配向して試料基板25の
表面に吸着することが起因していると考えられる。
[0102] The reason why the Cu thin film 75 with strong orientation was obtained is considered to be because the CuN compound was oriented in an orderly manner and adsorbed to the surface of the sample substrate 25.

【0103】一方、電気力線の向きを逆にしてCu薄膜
の成膜を行なった比較例の実験では、N原子が試料基板
25側を向き、Cu原子が真空側を向くようにCuN化
合物が配向するので、N原子が優先的に試料基板25の
表面に付着するようになる。したがって、この状態では
CuNが熱分解を起こしても、N原子はCu原子と試料
基板25の表面の原子とではさまれた構造にあるので、
N原子はN2 ガスとなって試料基板25から離れるの
が困難になり、Cu薄膜中に多くのN原子が含まれるよ
うになったと考えられる。
On the other hand, in a comparative example experiment in which a Cu thin film was formed with the electric lines of force reversed in direction, the CuN compound was formed so that the N atoms faced the sample substrate 25 side and the Cu atoms faced the vacuum side. Because of the orientation, N atoms preferentially adhere to the surface of the sample substrate 25. Therefore, in this state, even if CuN undergoes thermal decomposition, the N atoms are sandwiched between the Cu atoms and the atoms on the surface of the sample substrate 25.
It is thought that the N atoms became N2 gas and became difficult to separate from the sample substrate 25, and a large number of N atoms came to be included in the Cu thin film.

【0104】また、堆積速度が遅くなったのは、上述し
たようにN原子がN2 化合物として試料基板25から
離れにくくなるので基板表面にN原子が溜まり、熱分解
が抑制されたからだと考えられる。
[0104] Furthermore, the reason why the deposition rate became slower is thought to be because, as mentioned above, N atoms become difficult to separate from the sample substrate 25 as N2 compounds, so N atoms accumulate on the substrate surface and thermal decomposition is suppressed. .

【0105】また、バルクのCu薄膜に比べて配向性の
強いCu薄膜が得られなかったのは、N原子がCu原子
と試料基板25の表面の原子との間に常に存在するため
だと考えられる。
[0105] Also, the reason why a Cu thin film with stronger orientation than a bulk Cu thin film could not be obtained is thought to be because N atoms always exist between Cu atoms and atoms on the surface of the sample substrate 25. It will be done.

【0106】なお、上記第1〜第5の実施例では原料ガ
スとしてCuNを用いたが、他の原料ガス、例えば、ア
ジ化銅(CuN3 )を用いても同様の効果が得られる
Although CuN was used as the source gas in the first to fifth embodiments, similar effects can be obtained by using other source gases, such as copper azide (CuN3).

【0107】また、上記第1〜第5の実施例ではCu薄
膜を形成する場合について述べたが、本発明は、他の薄
膜の形成、例えば、水素化チタン(TiH2)、臭化チ
タン(TiBr2 )などを用いたTi薄膜の形成や六
弗化タングステン(WF6 )、塩化タングステン(W
Cl2 ,WCl4 ,WCl5 ,WCl6 )、臭
化タングステン(WBr2 ,WBr5 ,WBr6 
)、ヨウ化タングステン(WI2 ,WI3 )などを
用いたW薄膜の形成にも適用できる。
[0107] Furthermore, although the above first to fifth embodiments have described the case of forming a Cu thin film, the present invention is also applicable to the formation of other thin films, such as titanium hydride (TiH2), titanium bromide (TiBr2), etc. ), tungsten hexafluoride (WF6), tungsten chloride (W
Cl2, WCl4, WCl5, WCl6), tungsten bromide (WBr2, WBr5, WBr6)
), tungsten iodide (WI2, WI3), etc. can also be applied to the formation of a W thin film.

【0108】なお、原料ガスとしてチタンやタングステ
ンの化合物を用いる場合には、原料ガスを膜形成室29
に導入する前に、予め高温のガス溜を通して一部分解さ
せて構造上対称性の崩れた中間体を形成しておくと、試
料基板25の表面の帯電効果や電場印加効果がより顕著
に現われる。
Note that when using titanium or tungsten compounds as the raw material gas, the raw material gas is passed through the film forming chamber 29.
If the sample substrate 25 is partially decomposed by passing it through a high-temperature gas reservoir to form an intermediate whose structure is not symmetrical before being introduced into the sample substrate 25, the charging effect on the surface of the sample substrate 25 and the effect of applying an electric field will be more pronounced.

【0109】また、下地としてアルミや二酸化シリコン
を用いたが、他の下地、例えば、シリコン等の下地でも
よい。
Further, although aluminum and silicon dioxide are used as the base, other bases such as silicon may be used.

【0110】次に本発明の第6の実施例に係る薄膜の形
成方法を説明する。これは本発明をチタンシリサイド膜
の形成に適用したものである。
Next, a method for forming a thin film according to a sixth embodiment of the present invention will be explained. This is an application of the present invention to the formation of a titanium silicide film.

【0111】最初、図5のCVD装置の配管49に取り
付けられたCuNボンベをステンレス製のTiH2 ボ
ンベに換え、配管53に取り付けられたN2 ボンベを
ステンレス製のSiCl4 ボンベに換える。また、第
5の実施例と同様に水冷電極を用いる。次いでTiH2
 ボンベ及び配管49の全体を200℃に、SiCl4
 ボンベ及び配管53の全体を100℃に加熱してTi
H2 ガス,SiCl4 ガスの蒸気圧を上げると共に
、TiH2 ガス,SiCl4 ガスが配管部分で再凝
縮するのを防止する。
First, the CuN cylinder attached to the pipe 49 of the CVD apparatus shown in FIG. 5 is replaced with a stainless steel TiH2 cylinder, and the N2 cylinder attached to the pipe 53 is replaced with a stainless steel SiCl4 cylinder. Further, a water-cooled electrode is used as in the fifth embodiment. Then TiH2
The entire cylinder and piping 49 are heated to 200°C with SiCl4
The entire cylinder and piping 53 are heated to 100°C to
This increases the vapor pressure of H2 gas and SiCl4 gas, and prevents TiH2 gas and SiCl4 gas from recondensing in the piping section.

【0112】次に図10に示した構造の試料基板25を
サセプタ31に載置した後、Arガスをキャリアガスと
して用いBCl3 プラズマを発生させ、配線67の表
面のダメージ層及び自然酸化膜層を除去する。次いで加
熱源33の電源を入れて試料基板25を加熱し、その表
面温度を450℃にした。このとき、水冷電極を試料基
板25の上方約20mmの位置に退避させ、水冷電極の
過熱を防止する。
Next, after placing the sample substrate 25 having the structure shown in FIG. 10 on the susceptor 31, BCl3 plasma is generated using Ar gas as a carrier gas to remove the damaged layer and natural oxide film layer on the surface of the wiring 67. Remove. Next, the heating source 33 was turned on and the sample substrate 25 was heated to a surface temperature of 450°C. At this time, the water-cooled electrode is retracted to a position approximately 20 mm above the sample substrate 25 to prevent the water-cooled electrode from overheating.

【0113】次に水冷電極とサセプタ31との間に、図
12(a)に示されるような低周波の矩形状の電圧を印
加し続け、この状態でバルブ51,55を開けてTiH
2 ガス,SiCl4 ガスを膜形成室29に導入する
。しかる後、バルブ51,55を閉じてTiH2 ガス
,SiCl4 ガスの導入を停止する。更に矩形状の電
圧の印加も停止する。
Next, a low frequency rectangular voltage as shown in FIG. 12(a) is continued to be applied between the water-cooled electrode and the susceptor 31, and in this state, the valves 51 and 55 are opened to
2 gas and SiCl4 gas are introduced into the film forming chamber 29. Thereafter, the valves 51 and 55 are closed to stop the introduction of TiH2 gas and SiCl4 gas. Furthermore, the application of the rectangular voltage is also stopped.

【0114】最後に、加熱源33の電源を切り、試料基
板25の表面温度を室温にまで下げる。
Finally, the heating source 33 is turned off and the surface temperature of the sample substrate 25 is lowered to room temperature.

【0115】以上の工程を経た試料基板25をX線回折
測定法を用いて調べてみた。その結果、厚さ約0.5μ
mのチタンシリサイド膜が配線67の表面のみに選択的
に堆積しているのを確認した。
[0115] The sample substrate 25 that underwent the above steps was examined using an X-ray diffraction measurement method. As a result, the thickness is approximately 0.5μ
It was confirmed that the titanium silicide film of m was selectively deposited only on the surface of the wiring 67.

【0116】また、試料基板25の表面温度を更に高い
温度に設定してチタンシリサイド膜の成膜を行なったと
ころ、試料基板25の全面にチタンシリサイド膜が堆積
したことを確認した。
Furthermore, when the surface temperature of the sample substrate 25 was set to a higher temperature to form a titanium silicide film, it was confirmed that the titanium silicide film was deposited on the entire surface of the sample substrate 25.

【0117】なお、チタンシリサイド膜の組成は、試料
基板25の表面温度,原料ガスであるTiH2 ガス,
SiCl4 ガスの流量,水冷電極とサセプタ31との
間に印加する矩形状の電圧の振幅及び周期を変えること
で制御できた。
[0117] The composition of the titanium silicide film is determined by the surface temperature of the sample substrate 25, the source gas TiH2 gas,
This could be controlled by changing the flow rate of the SiCl4 gas and the amplitude and period of the rectangular voltage applied between the water-cooled electrode and the susceptor 31.

【0118】以上の方法で配線67に選択的にチタンシ
リサイド膜が形成されたのは次のように考えられる。
The reason why the titanium silicide film was selectively formed on the wiring 67 by the above method is considered to be as follows.

【0119】Ti,H,Si,Clの電気陰性度は、そ
れぞれ1.5(Ti),2.1(H),1.8(Si)
,3.0(Cl)である。このため、TiH2 化合物
及びSiCl4 化合物の原子間の結合に関与するのは
主として共有結合であるが、わずかであるがイオン結合
も寄与することになる。したがって、TiH2 化合物
,SiCl4 化合物はそれぞれ(δ− )H−Ti(
δ+ )−H(δ− ),(δ− )Cl4 −Si(
δ+ )のように分極している。
[0119] The electronegativity of Ti, H, Si, and Cl is 1.5 (Ti), 2.1 (H), and 1.8 (Si), respectively.
, 3.0 (Cl). Therefore, although covalent bonds are mainly involved in the bonding between atoms of the TiH2 compound and the SiCl4 compound, ionic bonds also make a small contribution. Therefore, TiH2 compound and SiCl4 compound are (δ-)H-Ti(
δ+ )-H(δ-), (δ-)Cl4-Si(
It is polarized like δ+).

【0120】ところでSiCl4 化合物の構造はSi
を中心にした四面体構造であるため、SiCl4 化合
物の電気双極子モ−メントは小さい。しかしながら、S
iCl4 の融点,沸点はそれぞれ−70℃,57.6
℃といずれも低く、100℃で一部分解を始めるので、
上述のように試料基板25の表面温度(450℃)を設
定すると、SiCl4 化合物のSi原子とCl原子と
の結合手が切れ、分極の効果の高いSiCl2 化合物
が形成される。これはSiCl2 化合物のSi原子の
π軌道がCl原子の軌道でスクリーニングされなくなる
ため、Si(δ+ )の効果が出てくるようになる。
By the way, the structure of the SiCl4 compound is Si
Since it has a tetrahedral structure centered on , the electric dipole moment of the SiCl4 compound is small. However, S
The melting point and boiling point of iCl4 are -70℃ and 57.6, respectively.
Both temperatures are low, and some decomposition begins at 100°C, so
When the surface temperature (450° C.) of the sample substrate 25 is set as described above, the bond between the Si atom and the Cl atom of the SiCl4 compound is broken, and a SiCl2 compound having a high polarization effect is formed. This is because the π orbital of the Si atom in the SiCl2 compound is no longer screened by the orbital of the Cl atom, so that the effect of Si(δ+) comes into play.

【0121】したがって、試料基板25の表面電位が+
のときは、図13(a)に示すように、SiCl2 化
合物のCl原子及びTiH2 化合物のH原子が配線6
7に選択的に吸着する。しかしながら、SiCl2化合
物の電気双極子モーメントの方がTiH2 化合物のそ
れより大きいので、SiCl2 化合物の方が優先的に
配線67に吸着し、配線67の表面はSiCl2 化合
物のSi原子(δ+ )で覆われることになる。
Therefore, the surface potential of the sample substrate 25 is +
In this case, as shown in FIG. 13(a), the Cl atom of the SiCl2 compound and the H atom of the TiH2 compound form the wiring 6.
selectively adsorbs to 7. However, since the electric dipole moment of the SiCl2 compound is larger than that of the TiH2 compound, the SiCl2 compound is preferentially adsorbed to the wiring 67, and the surface of the wiring 67 is covered with Si atoms (δ+) of the SiCl2 compound. It turns out.

【0122】次に試料基板25側の表面電位が+から0
になると、配線67上におけるSiCl2 化合物の吸
着状態が変化しないままTiH2 化合物,SiCl2
 化合物はそれぞれランダムな配向で試料基板25に吸
着しようとする。しかしながら、試料基板25の表面の
Si原子(δ+ )の影響で、図13(b)に示すよう
に、TiH2 化合物のTi原子及びSiCl2 化合
物のSi原子が優先的に配線67に吸着する。これら化
合物は試料基板25の表面温度が450℃と高いので互
いに反応しあう。このとき、TiH2 化合物のH原子
は真空側を向く。更に、配線67の表面電位を再び0か
ら+にすると、SiCl2 化合物のCl原子が配線6
7の表面側に向いて吸着し、このCl原子は前記H原子
と反応してHClの形で脱離する。その結果、SiCl
2 化合物のSi原子が前記Ti原子と直接結合する。 以上のメカニズムが繰り返されることにより、配線67
上に選択的にTiSix膜が形成される。
Next, the surface potential on the sample substrate 25 side changes from + to 0.
When the adsorption state of the SiCl2 compound on the wiring 67 remains unchanged, the TiH2 compound and SiCl2
The compounds tend to be adsorbed onto the sample substrate 25 in random orientations. However, due to the influence of Si atoms (δ+) on the surface of the sample substrate 25, the Ti atoms of the TiH2 compound and the Si atoms of the SiCl2 compound are preferentially adsorbed to the wiring 67, as shown in FIG. 13(b). These compounds react with each other because the surface temperature of the sample substrate 25 is as high as 450°C. At this time, the H atoms of the TiH2 compound face the vacuum side. Furthermore, when the surface potential of the wiring 67 is changed from 0 to + again, the Cl atoms of the SiCl2 compound
The Cl atoms are adsorbed toward the surface of 7, and these Cl atoms react with the H atoms and are desorbed in the form of HCl. As a result, SiCl
2. The Si atom of the compound is directly bonded to the Ti atom. By repeating the above mechanism, the wiring 67
A TiSix film is selectively formed thereon.

【0123】次に本発明の第7の実施例に係る薄膜の形
成方法を説明する。
Next, a method for forming a thin film according to a seventh embodiment of the present invention will be described.

【0124】この実施例が先に説明した第6の実施例と
異なる点は、水冷電極とサセプタ31との間に印加する
電圧を変えたことにある。
This embodiment differs from the previously described sixth embodiment in that the voltage applied between the water-cooled electrode and the susceptor 31 was changed.

【0125】即ち、図12(b)に示すように、+から
−に跨がる矩形状の電圧を水冷電極とサセプタ31との
間に印加する。
That is, as shown in FIG. 12(b), a rectangular voltage ranging from + to - is applied between the water-cooled electrode and the susceptor 31.

【0126】図14(a)に示すように、配線67の表
面電位が−の場合、原料ガスであるSiCl2 化合物
は、Si原子が配線67の表面側、Cl原子が真空側と
なる配向性を以て配線67の表面に近づいて吸着する。 また、他の原料ガスであるTiH2 化合物は、Ti原
子が配線67の表面側、H原子が真空側となる配向性を
以て配線67の表面に近づき吸着する。しかしながら、
SiCl2 化合物の電気双極子モーメントの方がTi
H2化合物のそれより大きいのでSiCl2 化合物の
方が優先的に配線67の表面に吸着する。その結果、配
線67の表面は主としてSiCl2のCl原子で覆われ
るようになる。
As shown in FIG. 14(a), when the surface potential of the wiring 67 is -, the SiCl2 compound which is the raw material gas has an orientation such that the Si atoms are on the surface side of the wiring 67 and the Cl atoms are on the vacuum side. It approaches the surface of the wiring 67 and is attracted to it. Further, the TiH2 compound, which is another source gas, approaches the surface of the wiring 67 and is adsorbed with an orientation such that the Ti atoms are on the surface side of the wiring 67 and the H atoms are on the vacuum side. however,
The electric dipole moment of the SiCl2 compound is higher than that of Ti.
Since it is larger than that of the H2 compound, the SiCl2 compound is preferentially adsorbed to the surface of the wiring 67. As a result, the surface of the wiring 67 is mainly covered with Cl atoms of SiCl2.

【0127】そして図14(b)に示すように配線67
の表面電位を−から+に変えると、SiCl2 化合物
は、Cl原子が配線67の表面側、Si原子が真空側と
なる配向性を以て配線67の表面に近づく。このとき、
配線67上におけるSiCl2 化合物の吸着状態は変
化しない。配線67の表面に近づいたSiCl2 化合
物は、配線67の表面のCl(δ− )により斥力を受
けるため、配線67への吸着が抑制される。
Then, as shown in FIG. 14(b), the wiring 67
When the surface potential of is changed from - to +, the SiCl2 compound approaches the surface of the wiring 67 with an orientation such that Cl atoms are on the surface side of the wiring 67 and Si atoms are on the vacuum side. At this time,
The adsorption state of the SiCl2 compound on the wiring 67 does not change. The SiCl2 compound that approaches the surface of the wiring 67 receives a repulsive force from Cl (δ-) on the surface of the wiring 67, so that adsorption to the wiring 67 is suppressed.

【0128】一方、TiH2 化合物は、H原子が配線
67の表面側、Ti原子が真空側となる配向性を以て配
線67の表面に近づく。TiH2 化合物が配線67の
表面に近づくと、配線67の表面のCl原子(δ− )
は、TiH2 化合物のH原子(δ+ )と結合してH
Clの形で配線67から抜けていき、その結果、Ti原
子はSi原子と直接接合するようになる。更に、配線6
7の表面電位を+から再び−にすると、SiCl2 化
合物のSi(δ+ )が配線67の表面側に向いて吸着
し、このSi原子は前記Ti原子と直接接合する。以上
のメカニズムが繰り返されることにより、Clの含有量
の少ない良質のチタンシリサイド膜(TiSix)が配
線67の表面に選択的に形成される。このチタンシリサ
イド膜は、第6の実施例で形成したチタンシリサイド膜
と比べて、塩素含有量が更に少なく、より良質な膜であ
る。
On the other hand, the TiH2 compound approaches the surface of the wiring 67 with an orientation such that the H atoms are on the surface side of the wiring 67 and the Ti atoms are on the vacuum side. When the TiH2 compound approaches the surface of the wiring 67, Cl atoms (δ-) on the surface of the wiring 67
is combined with the H atom (δ+) of the TiH2 compound to form H
The Ti atoms escape from the wiring 67 in the form of Cl, and as a result, the Ti atoms come to be directly bonded to the Si atoms. Furthermore, wiring 6
When the surface potential of the wiring 67 is changed from + to - again, Si (δ+) of the SiCl2 compound is adsorbed toward the surface of the wiring 67, and this Si atom is directly bonded to the Ti atom. By repeating the above mechanism, a high quality titanium silicide film (TiSix) with a low Cl content is selectively formed on the surface of the wiring 67. This titanium silicide film has a lower chlorine content and is of better quality than the titanium silicide film formed in the sixth embodiment.

【0129】なお、バルブ51,55をピエゾバルブに
交換し、水冷電極とサセプタ31との間に印加する電圧
の周波数と同期させてピエゾバルブを開閉して原料ガス
を間欠的に導入してもよい。
Note that the valves 51 and 55 may be replaced with piezo valves, and the source gas may be introduced intermittently by opening and closing the piezo valves in synchronization with the frequency of the voltage applied between the water-cooled electrode and the susceptor 31.

【0130】即ち、電圧が−のときはSiCl2 ガス
のみを導入してTiH2 ガスのTi(δ+ )原子の
吸着を防止し、電圧が+のときはTiH2 ガスのみを
導入してSiCl2 ガスのCl(δ− )原子の吸着
を防止することでチタンシリサイド膜に含まれる不純物
を激減できる。
That is, when the voltage is negative, only SiCl2 gas is introduced to prevent the adsorption of Ti(δ+) atoms in TiH2 gas, and when the voltage is positive, only TiH2 gas is introduced to prevent the adsorption of Ti(δ+) atoms in SiCl2 gas. By preventing adsorption of δ−) atoms, impurities contained in the titanium silicide film can be drastically reduced.

【0131】なお、上記第6及び7の実施例ではSi用
の原料ガスとしてSiCl4 、Ti用の原料ガスとし
てTiH2 を用いたが、他の原料ガスを用いても同様
な効果が得られる。例えば、SiCl4 の代わりにモ
ノシラン、ジシラン及びそれらのハロゲン化物を用いて
もよい。
In the sixth and seventh embodiments, SiCl4 was used as the source gas for Si and TiH2 was used as the source gas for Ti, but similar effects can be obtained by using other source gases. For example, monosilane, disilane, and their halides may be used instead of SiCl4.

【0132】また、TiH2 の代わりに弗化タングス
テン(WF6 )、塩化タングステン(WCl2 ,W
Cl4 ,WCl5 ,WCl6 )、臭化タングステ
ン(WBr2 ,WBr5 ,WBr6 )、ヨウ化タ
ングステン(WI2 ,WI3 )等を用い、これとモ
ノシラン、ジシラン及びそれらのハロゲン化物を用いる
ことで、タングステンシリサイド膜を形成することがで
きる。この場合もチタンシリサイド膜形成の場合と同様
な効果を得ることができる。
[0132] Also, instead of TiH2, tungsten fluoride (WF6), tungsten chloride (WCl2, W
A tungsten silicide film is formed by using tungsten bromide (WBr2, WBr5, WBr6), tungsten iodide (WI2, WI3), etc., and monosilane, disilane, and their halides. can do. In this case as well, the same effects as in the case of forming a titanium silicide film can be obtained.

【0133】更に、窒化銅(CuN)やアジ化銅(Cu
N3 )等を用いCu膜を堆積したら、水素化チタン(
TiH2 )や臭化チタン(TiBr2 )等を用いて
Ti膜を堆積することができ、前述したCu薄膜堆積の
実施例と同様な効果があった。
Furthermore, copper nitride (CuN) and copper azide (CuN)
After depositing a Cu film using N3) etc., titanium hydride (
A Ti film could be deposited using TiH2), titanium bromide (TiBr2), etc., and the same effect as in the above-mentioned example of depositing a Cu thin film was obtained.

【0134】特に、これらのチタンやタングステンの化
合物を原料ガスに用いる場合には、原料ガスを膜形成室
29に導入する前に高温のガス溜を通すことで一部分解
させ,SiCl2 のように構造上対称性の崩れた中間
体を形成しておくと、電場印加効果はより顕著に現われ
た。
In particular, when these titanium or tungsten compounds are used as raw material gases, the raw material gases are partially decomposed by passing them through a high temperature gas reservoir before being introduced into the film forming chamber 29, so that they have a structure like SiCl2. When an intermediate with broken upper symmetry was formed, the effect of electric field application was more pronounced.

【0135】また、上記実施例では水冷電極とサセプタ
31との間に印加した電圧の波形は矩形状であったが、
所定の電場が発生するものなら他の形状であってもよい
。なお、ここでいう電場は電極間に放電が生じない程度
の大きさの電場であり、通常のプラズマ成膜装置で生じ
る電場とは異なる。
Furthermore, in the above embodiment, the waveform of the voltage applied between the water-cooled electrode and the susceptor 31 was rectangular;
Other shapes may be used as long as a predetermined electric field is generated. Note that the electric field referred to here is an electric field of a magnitude that does not cause discharge between the electrodes, and is different from the electric field generated in a normal plasma film forming apparatus.

【0136】その他、本発明の要旨を逸脱しない範囲で
種々変形して実施できる。
[0136] In addition, various modifications can be made without departing from the gist of the present invention.

【0137】[0137]

【発明の効果】以上述べたように本発明の薄膜の形成方
法によれば、所定配向で化合物を基板上の所定領域に容
易に導くことができるため、不純物の少ない良質な薄膜
を基板上の所定領域に堆積できる。
As described above, according to the thin film forming method of the present invention, a compound can be easily guided to a predetermined region on a substrate in a predetermined orientation, so that a high quality thin film with few impurities can be formed on the substrate. It can be deposited in a predetermined area.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1の実施例に係わる試料基板の断面
図。
FIG. 1 is a sectional view of a sample substrate according to a first embodiment of the present invention.

【図2】下部電極部の形状を示す図。FIG. 2 is a diagram showing the shape of a lower electrode part.

【図3】上部電極部の形状を示す図。FIG. 3 is a diagram showing the shape of an upper electrode part.

【図4】静電誘導により上部電極に電荷が帯電した状態
を示す図。
FIG. 4 is a diagram showing a state in which the upper electrode is charged with electric charge due to electrostatic induction.

【図5】本発明の第1の実施例に係わるCVD装置の概
略構成図。
FIG. 5 is a schematic configuration diagram of a CVD apparatus according to a first embodiment of the present invention.

【図6】CuN化合物の上部電極への付着の様子を示す
図。
FIG. 6 is a diagram showing how a CuN compound is attached to the upper electrode.

【図7】本発明の第3の実施例で用いる試料基板を示す
図。
FIG. 7 is a diagram showing a sample substrate used in a third embodiment of the present invention.

【図8】本発明の第3の実施例で用いる帯電用電極を示
す図。
FIG. 8 is a diagram showing a charging electrode used in a third embodiment of the present invention.

【図9】本発明の第4の実施例で用いる試料基板を示す
図。
FIG. 9 is a diagram showing a sample substrate used in a fourth embodiment of the present invention.

【図10】本発明の第5の実施例で用いる試料基板を示
す図。
FIG. 10 is a diagram showing a sample substrate used in a fifth embodiment of the present invention.

【図11】Cu薄膜の堆積状態を示す図。FIG. 11 is a diagram showing the deposition state of a Cu thin film.

【図12】水冷電極とサセプタとの間に印加する電圧の
波形を示す図。
FIG. 12 is a diagram showing a waveform of a voltage applied between a water-cooled electrode and a susceptor.

【図13】本発明の第6の実施例におけるTiH2 化
合物,SiCl2 化合物の配線表面への吸着の様子を
示す図。
FIG. 13 is a diagram showing how TiH2 compounds and SiCl2 compounds are adsorbed onto the wiring surface in the sixth embodiment of the present invention.

【図14】本発明の第7の実施例におけるTiH2 化
合物,SiCl2 化合物の配線表面への吸着の様子を
示す図。
FIG. 14 is a diagram showing how TiH2 compounds and SiCl2 compounds are adsorbed onto the wiring surface in the seventh embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…シリコン基板、3…熱酸化膜、5,7…下部電極、
9,11…電極取り出し部、13…下部電極部、15…
二酸化シリコン膜、17,19…上部電極、21…上部
電極部、23…接続孔、25…試料基板、27…CVD
装置、29…膜形成室、31…サセプタ、33…加熱源
、35…放電用電極、37,37a,39…帯電用電極
、41…ガス供給部、43…ガス排気部、45,49,
53…配管,47,51,55…バルブ、57…ゲート
バルブ、59,61…電極、63…シリコン基板、65
…酸化膜、67…配線、69…シリコン酸化膜、71…
層間接続孔、73…Al合金膜表面、75…Cu薄膜。
1... Silicon substrate, 3... Thermal oxide film, 5, 7... Lower electrode,
9, 11... Electrode extraction part, 13... Lower electrode part, 15...
Silicon dioxide film, 17, 19... Upper electrode, 21... Upper electrode part, 23... Connection hole, 25... Sample substrate, 27... CVD
Apparatus, 29... Film formation chamber, 31... Susceptor, 33... Heat source, 35... Electrode for discharge, 37, 37a, 39... Electrode for charging, 41... Gas supply section, 43... Gas exhaust section, 45, 49,
53... Piping, 47, 51, 55... Valve, 57... Gate valve, 59, 61... Electrode, 63... Silicon substrate, 65
...Oxide film, 67...Wiring, 69...Silicon oxide film, 71...
Interlayer connection hole, 73...Al alloy film surface, 75...Cu thin film.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  原料ガスを導入し、化学反応により基
板上に化合物を吸着させて薄膜を形成する薄膜の形成方
法において、前記化合物として電気分極した化合物を用
いると共に、電気力により前記化合物の所定の原子を前
記基板上の所定領域に選択的に導くことを特徴とする薄
膜の形成方法。
1. A method for forming a thin film in which a raw material gas is introduced and a compound is adsorbed onto a substrate through a chemical reaction to form a thin film, in which an electrically polarized compound is used as the compound, and a predetermined polarization of the compound is performed by electric force. A method for forming a thin film, the method comprising selectively guiding atoms of to a predetermined region on the substrate.
【請求項2】  原料ガスを導入し、化学反応により基
板上に化合物を吸着させて薄膜を形成する薄膜の形成方
法において、前記化合物として電気分極した化合物を用
いると共に、前記基板上の所定領域を帯電させることに
より前記化合物の所定の原子を前記基板上の所定領域に
選択的に導くことを特徴とする薄膜の形成方法。
2. A method for forming a thin film in which a raw material gas is introduced and a compound is adsorbed onto a substrate through a chemical reaction to form a thin film, in which an electrically polarized compound is used as the compound, and a predetermined area on the substrate is A method for forming a thin film, comprising selectively guiding predetermined atoms of the compound to a predetermined region on the substrate by charging the compound.
【請求項3】  原料ガスを導入し、化学反応により基
板上に化合物を吸着させて薄膜を形成する薄膜の形成方
法において、前記化合物として電気分極した化合物を用
いると共に、前記基板を電場中において前記化合物の所
定の原子を前記基板上の所定領域に選択的に導くことを
特徴とする薄膜の形成方法。
3. A method for forming a thin film in which a material gas is introduced and a compound is adsorbed onto a substrate by a chemical reaction to form a thin film, in which an electrically polarized compound is used as the compound, and the substrate is placed in an electric field to form a thin film. A method for forming a thin film, comprising selectively guiding predetermined atoms of a compound to a predetermined region on the substrate.
JP8842091A 1991-04-19 1991-04-19 Thin film formation method Pending JPH04320332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8842091A JPH04320332A (en) 1991-04-19 1991-04-19 Thin film formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8842091A JPH04320332A (en) 1991-04-19 1991-04-19 Thin film formation method

Publications (1)

Publication Number Publication Date
JPH04320332A true JPH04320332A (en) 1992-11-11

Family

ID=13942293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8842091A Pending JPH04320332A (en) 1991-04-19 1991-04-19 Thin film formation method

Country Status (1)

Country Link
JP (1) JPH04320332A (en)

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