JPH0432089A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize the data write control without increasing a WE terminal by constituting the device so that it becomes impossible to write data from all data input/output terminals of a group to which a specific data input/output terminal belongs. CONSTITUTION:I/O terminals are divided into two groups of I/O 1, I/O 2 - I/O 8, and I/O 9, I/O 10 - I/O 16, and an I/O 1 and I/O 9 being specific I/O terminals, a write control circuit 13 and 93 are provided, respectively. To data-in buffer circuits 11, 21 - 81, 91, and 101 - 161, and the write control circuits 13, 93, a write control signal is inputted through a -WE control circuit 2 from a -WE terminal. In this case, the number of -WE terminals is one. Also, a control clock is inputted to the write control circuits 13, 93 through a control circuit 4. In such a way, the data write control of every group can be realized without necessitating an increase of a write control signal input terminal (-WE) terminal) being an external terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of data input/output terminals (110 terminals).

[Prior Art] As shown in FIG. 2, a conventional semiconductor memory device has a data storage system provided between a memory cell array 1, I10 terminals 1101 to 11016, each 170 terminal 1701 to I1016, and a memory cell array. In-buffer circuit 1
1,21. ~81, 91, 101~161 and data out buffer circuits 12, 22. ~82.92,10
2 to 162 and the first write control signal input terminal (Wπ
terminal) Wπ1, the second Wππ terminal π2, each data in buffer circuit 11°21 to 81, and the first Wπ terminal Wπ
1, and each data in buffer circuit 91, 101.
The second W provided between ~161 and the second WT terminal 12
π control circuit 3.

In the semiconductor memory device having the above configuration, the I10 terminal 1701
Data writing from ~1708 to the memory cell array 1 becomes possible by setting the Wπ terminal Wπ1 to a low level. On the other hand, 110 terminal l109~! To write data from 1016 to memory cell array 1, use W■ terminal W”
This is possible by setting E-2 to low level. In addition, data writing from all of the 110 terminals 1101 to 11016 to the memory cell array 1 is performed by Wπi 'W'E-1
This is possible by setting W2 and W2 to low level.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, data writing control for the two sets of 110 terminals 1101 to 1108 and 1109 to 11016 was performed using control signals from two Wπ terminals. The number of terminals required corresponds to the number of sets of 110 terminals, resulting in the problem of an increase in the number of external terminals and an accompanying increase in the package size.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of data input/output terminals, a plurality of data in buffer circuits provided between each data input/output terminal and a memory cell array, and a plurality of data in buffer circuits provided between each data input/output terminal and a memory cell array. In a semiconductor memory device equipped with a write control signal input terminal connected to an in-buffer circuit, the data input/output terminals are divided into a plurality of groups, a write control circuit is provided for each group, and a control clock and a write control signal input terminal are provided. The write control circuit controls all the data in buffer circuits of the set to which the specific data input/output terminal belongs based on the write control signal from the input/output terminal and the data from the specific data input/output terminal, and controls the data input/output of the specific data. It is characterized by disabling data writing from all data input/output terminals of the group to which the terminal belongs.

That is, data writing control for each set of 110 terminals is performed using a clock from a control clock terminal conventionally provided in a memory device and input data from a specific 170 terminal, thereby providing one terminal. It has been achieved without any problems.

[Example] The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

As shown, 110 terminals 1101. 1102~l1
08°1109, data in buffer circuits 11, 21 to 81, 91, 101 to 161 and data out buffer circuits 12.22 to B2, 92, 102 to 1 are provided between l1010 to l1016 and memory cell array 1, respectively.
62 are provided.

In this embodiment, the 110 terminal is 1101. l102~1
708 and 109, divided into two mornings, l1010 to 11016, and 1701 and 1109 as specific 170 terminals.
are provided with write control circuits 13 and 93, respectively.

Data in buffer circuit 11.21 to 81, 91.10
1 to 161 and the write control circuit 13.93, a write control signal is input from one terminal through the ffl control circuit 2, and unlike the conventional example described above, there is only one ffl terminal.

Further, a control clock is input from the control clock terminal CL to the write control circuit 13.93 via the control circuit 4.

Next, the operation will be explained. First, control clock terminal C
When L becomes low level and the control circuit 4 is activated, W
If the l-terminal is at low level and the 110 terminal 1101 is at low level, the 110 terminals 1101 to 1108 are disabled for writing in that cycle.

Similarly, when the control clock terminal CL becomes a low level and the control circuit 4 is activated, if the 1st terminal is at a low level and the 110 terminal 1109 is at a low level, the 110
Terminals 1709 to 11016 become unwritable in that cycle. Therefore, the input signal from one terminal, the input signal from control clock terminal CL, and the input signal from one
70 terminal 1101. 1109, a particular 110 terminal 1101 . I containing 1109
It controls the morning data writing of terminal 10.

In addition, there are 110 terminals 101 to 11032, and sets of 110 terminals are 1101 to 1108. 1109-11016
．． l1017~1024, 11025~11032
In the semiconductor memory device as well, by providing a write control circuit for each sheath of each of the 170 terminals, morning write control of each of the 170 terminals can be performed, as in the above embodiment.

[Effects of the Invention] As explained above, the semiconductor memory device of the present invention divides the data input/output terminals into a plurality of groups, provides a write control circuit for each group, and performs write control from the control clock and write control signal input terminal. Based on the signal and the data from the specific data input/output terminal, the write control circuit controls all the data in buffer circuits of the group to which the specific data input/output terminal belongs, and Since data writing from all data input/output terminals is disabled, there is no need to add an external write control signal input terminal (W terminal).
Therefore, data writing control of the data input/output terminal (terminal 110) every morning can be realized without increasing the package size.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor memory device. 101~l1016・・・・・・・・・110 terminal,
11.21~81°91.101~161...Data in buffer circuit, 12.22~82°92.102~162...Data out buffer circuit, Wπ... ...1 terminal, CL...
・・・・・・Control clock terminal, 13・・・・・・・・・
- Write control circuits 1101 to 1108, 93...1109 to 11016 write control circuits.

Claims (1)

[Claims] A semiconductor comprising a plurality of data input/output terminals, a plurality of data in buffer circuits provided between each data input/output terminal and a memory cell array, and a write control signal input terminal connected to each data in buffer circuit. In a memory device, data input/output terminals are divided into a plurality of groups, and a write control circuit is provided for each group. The write control circuit controls all the data in buffer circuits of the group to which the specific data input/output terminal belongs, and disables data writing from all data input/output terminals of the group to which the specific data input/output terminal belongs. A semiconductor memory device characterized by: