JPH0432094A - Semiconductor storage circuit device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of an element and its malfunction by providing a switch between a bit line and the prescribed potential, and providing a control circuit for allowing this switch to conduct in the case of a state all word lines are not selected. CONSTITUTION:This SRAM is provided with eight pieces of N channel type MOS transistors (NMOSTR) Q1, 60 pieces of P channel type MOS transistors Q2, and 60 pieces of NMOSTRs Q3. Also, the NMOSTR Q1 configures a switch provided between bit lines R0 - R7 and the prescribed potential. Moreover, the PMOSTR Q2 and the NMOSTR Q3 configure a control circuit for allowing the switch to conduct in the case of a state that all word lines W1 - W60 are not selected, and cutting off the switch in the case of a state that at least one piece of word line is selected. In such a way, reliability of an element and a wiring is enhanced, and a malfunction of a circuit can be eliminated.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory circuit device, and particularly to a semiconductor memory circuit device in which all word lines can be in a non-selected state due to the relationship between the number of address signal inputs and the number of word lines. in between.

[Prior Art] As a conventional semiconductor memory circuit device, for example, 6°
8-bit static read/write memory (static random access memory, hereinafter referred to as SR)
AM) includes a decoder 102 that decodes address input signals ADO, ADI, . . . , AD5, and word lines Wl, W2, . WaO and a group of memory elements connected to this word line (hereinafter referred to as a memory cell group)
1o1, read-side bit lines RO, . , write enable) Wτ writes write information (hereinafter referred to as write data) WDO, ..., WD7, and a read circuit (hereinafter referred to as write enable) connected to the common bit lines RO, ..., R7. , called sense amplifier)1
04, and a read data terminal RDO that outputs read information (hereinafter referred to as read data) to the outside of the SRAM.
. , RD7. The memory cell 101 is the fifth
As shown in the figure, inverting amplifiers (hereinafter referred to as inverters) 10 and 11 connected in a loop that hold information and an inverter 12 that outputs information to the read-side bit line Ri when the word line Wi becomes a high potential and N-channel MO
S transistor (hereinafter referred to as NMOSTr) Q5,
NMO5TrQ4. which inputs write data to the information holding unit 10.11 through the write side bit lines Di and TJ when the write enable WEi becomes high potential. It consists of Q6.

Here, address input signal A of the SRAM shown in FIG.
Since DO, ADI, ..., AD5 are 6 bits,
Address input signals ADO, ADI, . . . , AD5 and word lines Wl, W2 . ..., the correspondence with W2O is as shown in the table below. Note that the selected word line in this table has a high potential, and the unselected word line has a low potential.

As is clear from this table, there are four types of address input states in which no word line is selected.

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit device, the number of address signal inputs (6) and the total number of word lines (60) have a relationship of 25 x 60 < 26, so any word line cannot be selected. When an address signal that is not specified is input, the read-side common bit line connected to the memory cell is in a floating state, so the input of the sense amplifier connected to the bit line becomes undefined, and the output also becomes undefined. There was a problem. In particular, if the sense amplifier is composed of MO9 type transistors, the human power is at a floating potential, which causes a through current to flow from the power supply to the ground, causing circuit malfunction. Although the through current depends on the size of the transistors that make up the sense amplifier, it flows from several tens of microns to several mA, so in a circuit with a bit count of, for example, 32 bits, a current of nearly 100 mA flows by itself, causing damage to elements and wiring. Reliability may be an issue.

In addition, this problem does not only apply to SRAM, but also to read-only memory circuits (ROM) and dynamic RAM (DRAM).
The same is true.

[Means for Solving the Problems] In the semiconductor memory circuit device of the present invention, the number m of word lines for selecting memory elements and the number n of address signal inputs for selecting the word lines satisfy m <2'. A switch provided between a bit line through which information of a storage element is transmitted and a predetermined potential in a semiconductor memory circuit device in which all word lines can be in a non-selected state in response to the address signal. and a control circuit that makes the switch conductive when all word lines are unselected and turns off the switch when at least one word line is selected.

[Example] Next, the present invention will be explained with reference to the drawings.

Figure 1 shows the first embodiment of the present invention (60 words x 8 bits)
It is a circuit diagram of SRAM. Similarly to the conventional example, the SRAM of this embodiment also receives 6-bit address input signals ADO and ADI.
,..., a decoder 102 that decodes AD5, and 60 word lines Wl selected by this decoder,
W2. ..., W2C, the memory cell group 101 connected to this word line, the bit line RO, ..., R7 to which the output from the memory cell group 101 is commonly connected, and the memory cell group 101. It is input via circuits 105 and 106. Write data WDO by write enable W■.

..., a circuit 103 for writing WD7, a sense amplifier 104 connected to the common bit lines RO, ..., R7, and read data terminals RDO, ..., RD7 that output read data to the outside of the SRAM. The memory cell 101 also has the same structure as shown in FIG.

Here, the SRAM of this embodiment has each bit line RO.

. . . 8 N-channel type MO5s whose gates are inputted to the node CL provided between R7 and the ground potential GND.
) transistor (hereinafter referred to as NMO5Tr) Ql, and each word line Wl, W2 . ..., 60 P-channel type MO5) transistors (hereinafter referred to as PMO3Tr) transistors Q2 whose gates are inputted with W2C, and each word line Wl are arranged in parallel between the ground potential GND and the node CL. ,
W2. ..., W2C is equipped with 60 NMO9TrQ3 input to the gate, and NMO5TrQ1 is connected to the bit line RO, ---, R7 and a predetermined potential (ground potential GN
D) constitutes a switch provided between PMO3TrQ
2 and NMO5TrQ3 are all word lines Wl, W2
．． . . . constitutes a control circuit that makes the switch conductive when W2C is not selected and turns off the switch when at least one word line is selected.

Next, the operation of the circuit shown in FIG. 1 will be explained. Address input signal ADO as explained in the prior art section.

AD 1. ..., AD5 is (0, O, 0, 0, 0, 0
) to (1,1,1,0,1,1,) are word lines Wl, W2 . ..., one of the W2Cs becomes selected (high potential), but the subsequent address input signals, that is, from (1, 1, 1, 1, 0, 0) to (1° 1, 1
．． 1. 1. Until 1), all word lines are in a non-selected state (low potential). When all word lines are in the unselected state, PMOSTrQ2 whose gate is connected to the word line
are all conductive and NMO5TrQ3 is all cut off. Therefore, since the node CL becomes the power supply potential VDD, that is, a high level, the NMO5Tr whose gate is connected to it
Q1 are all conductive, and bit lines RO, . . . , R7 are fixed to ground potential GND.

On the other hand, word lines Wl, W2. ..., when any one of W2C is selected, PMO9TrQ2 whose gate is connected to the selected word line is cut off, and NMO5Tr
Q3 is conductive. Therefore, node CL is at ground potential GND
, that is, the level becomes low, so NMO5TrQ1 is cut off, and information from memory cell 101 is transferred to read data terminal R.
DO, . . . are output to RD7.

That is, according to this embodiment, no matter what address input signal is input, the bit lines RO, . . . , R7 will never become floating.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a memory circuit device according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the write-side bit line and the read-side bit line are not separate, but a pair of write/read common bit lines Bi, l.
1m, and an NMO5TrQ1 is provided between the point where complementary information is input or output and the bit line correction and the ground potential GND (predetermined potential), while the bit line Bi and the power supply potential VDD ( The point is that an NMO9TrQ4 whose gate is connected to the node CL is provided as a switch between the NMO9TrQ4 and the node CL (predetermined potential). FIG. 4 shows a memory cell 109.
The circuit is shown below. This memory cell 109 has an inverter 13, 14 connected in a loop that holds information, and an information holding part and a bit line Bi when the word line W1 becomes a high potential.
, NMO5TrQ7 that inputs and outputs information between
It has

Now, word lines Wl, W2. ..., when all the PMO5TrQ2 are conductive and the node CL becomes high level when all W2C are in the unselected state (low level), the bit line Bi, correction is because the bit line potential fixing NMOS TrQl and Q4 are conductive. It has a fixed potential and will never be in a floating state. On the other hand, the word line Wl.

W2. ..., when any one of W2C is selected, one of PMOSTrQ2 is cut off and any one of N
MOSTrQ3 becomes conductive, node CL becomes low level, and NMO5TrQ1. Q4 is all shut off and normal operation is possible.

FIG. 3 is a circuit diagram showing an SRAM memory cell, FIG. 4 is a circuit diagram of a conventional SRAM, and FIG. 5 is a circuit diagram of a conventional SRAM memory cell.

[Effects of the Invention] As explained above, the present invention provides a semiconductor memory circuit in which the number m of word lines and the number n of address input signals satisfy the relationship m<2n. ) and a control circuit that makes the switch conductive when all word lines are unselected, so the bit lines will not remain floating even when all word lines are unselected. Therefore, it has the effect of preventing the element from deteriorating or malfunctioning due to a through current flowing through the readout circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an SRAM according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of 5R101, 109 according to another embodiment of the present invention.
ψ ・ ・ ・ ・ ・102 ・ ・ ・ ・ sha
φ φ ・Conflict ・103.110 ・ ・ ◆ ・
・ ・104.111 Conflict ・Memorial cell group, ・Decoder, ・Write circuit, ・Read circuit (sense amplifier), 105.106... Write control circuit (write enable circuit), 10.11゜12.13,14...Inverting amplifier (inverter), Ql, Q3. Q4゜Q5. Q6. Q7...N-channel MOS transistor (NMOSTr), BO,n,..., B7. f7...Write/read common bit line, Ql...P channel type MOS) transistor (P
MOSTr), CL ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
・Node, VDD・・・・・・・・・Power supply potential. ADO, ADI,..., AD5...Address input signal, W......Write control signal (write enable), WDO,..., WD?・ ・ ・ ・Write information (write data),

Claims (1)

[Claims] The number m of word lines for selecting a storage element and the number n of address signal inputs for selecting the word line have a relationship of m<2^n, and all word lines are activated in response to the address signal. In a semiconductor memory circuit device in which a non-selected state may occur, a switch provided between a bit line through which information of a storage element is transmitted and a predetermined potential is made conductive when all word lines are non-selected. A semiconductor memory circuit device comprising: a control circuit that shuts off the switch when at least one word line is selected.