JPH0432371A - Synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit area by providing a detection pulse generating means which receives a detection signal resulting from part or all of a frame pulse in a 2nd line signal inverted by an inversion means detected by a detection means, receives a detection signal stored in a storage means and outputs a detection pulse to the synchronizing signal detection circuit. CONSTITUTION:The synchronizing signal detection circuit is provided with an EXOR gate 30 inverting a 2nd line signal to an input terminal with the storage result of a detection signal by a storage means 20 and a detection pulse generating means 40 which receives a detection signal resulting from part or all of a frame pulse in an inverted 2nd line signal detected by a detection means 10, receives a detection signal stored in a storage means 20 and outputs a detection pulse. Then the detection means 10 detects all or part of the frame pulse in a 1st line signal. Thus, it is not needed to detect all blocks in both the line signals and number of transistors required for the detection means 10 is saved. Thus, the circuit area in the case of LSI is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal detection circuit suitable for high-definition televisions such as the MUSE system.

[Conventional technology]

Conventionally, in television systems, so-called high-definition televisions with 1000 or more scanning lines have been considered, compared to the NTSC system with 525 scanning lines, and the MUSE system has been proposed as one of these systems. In this method, as shown in FIG. 5, a first line signal and a second line signal having opposite phases are interpolated into a transmission signal as synchronization signals for frame synchronization, and these first and second line signals are interpolated into a transmission signal. Second
The line signal is a frame in which high level and low level bare (hereinafter referred to as H and L, respectively) for 4 clocks each are repeated 1.7.5 times (140 clocks) during one line (480 clocks) period. The pulses are multiplexed, and the first frame pulse is multiplexed. Second
The frame synchronization signal is detected by detecting the line signal.

Note that CK in FIG. 5 indicates a transmission lock, and its frequency is 16.2 MHz.

By the way, FIG. 6 shows an example of a synchronization signal detection circuit used in a conventional MUSE system high-definition television. In the figure, 1 indicates a 1-bit input terminal, and 2
is a MUSE video signal format with 1 scanning line (1
3 is a one-scan line (hereinafter referred to as IH) shift register which delays the input signal by 480 clocks corresponding to the line) and outputs it. 3 is the input signal of the H shift register 2 and the current input signal. EXOR gate that outputs an H signal when the phase is opposite, 4 is a 4-stage shift l/registor that delays the input signal by 4 clocks and outputs it, 5 is 4
An EXOR gate which receives the output signal of the stage shift register 4 and the current input signal and outputs a high level (hereinafter referred to as H) signal when both signals are in opposite phase to each other, 6 is both EXO
an AND gate into which the output signals of R gates 3 and 5 are input;
7 has a 7 bit counter, both EXOR games h3.5
The clock pulse is counted while the output of AND gate 6 becomes H due to the H output of When the output of AND gate 6 becomes L, the count value is cleared.

Then, when the frame synchronization synchronization signal shown in FIG.
As shown in the figure, since the first line signal delayed by IH by the IH shift register 2 is input to the EXOR gate 3, the first line signal of opposite phase is input to the EXOR gate 3. The second line signal is input at the same time, and the output of the EXOR gate 3 becomes H for a period of 480 clocks corresponding to IH, while the output of the EXOR gate 5 is delayed by 4 clocks by the 4-stage shift register 4. Since the second line signal is high for 144 clock periods, the output of the AND gate 6 is high for 144 clock periods when the output of the EXOR gate 5 is high.

Further, as shown in FIG. 7, when the second line signal is input, the counter 7 continues counting clock pulses for a period of 1 to 44 clocks when the output of the AND gate 6 becomes H, and is carried at the 128th clock. In order to generate this, the carry output generated from this counter 7 is used as a synchronization detection pulse for Frehem synchronization.

[Problem to be solved by the invention]

Conventional synchronization signal detection circuits utilize the fact that the first line signal and second line signal for frame synchronization interpolated into the transmission signal are in opposite phases to each other, and detect two full clocks of both line signals. However, since frame synchronization detection is performed when a frame pulse in the second line signal is detected, IH
In order to hold data for (480 clocks) with a delay,
A 480-stage shift register is required as the IH shift register 2, and when such a synchronization signal detection circuit is integrated into an LSI, there is a problem that the circuit area becomes extremely large.

At this time, when calculating the required number of transistors (hereinafter referred to as "number"), in general, in a 0MO8 configuration, the number of transistors for an n-input AND gate is (2n + 2), which means that for a 2-input AND gate, there are 6 transistors. So, n input NA
There are 20 ND gates, and from this 2-input NAND
There are 4 for a gate, 2 for a 2-input EXOR gate, 2 for an inverter, 1 cone for one stage of a shift register, and 152 for a 7-bit counter, so the 6th
In the conventional circuit shown in the figure, the shift register has 484 stages and 5
808 pieces, counter] 152 pieces, each gate 12.1
4.15]O transistors in total, and a total of 5970 transistors are required.

This invention was made to solve the above-mentioned problems, and the synchronous signal detection circuit is integrated into an LSI. The purpose of this invention is to make the circuit area smaller than before.

[Means to solve the problem]

The synchronization signal detection circuit according to the present invention includes a transmission signal including line signals of a plurality of lines, a first line signal in which a frame pulse is multiplexed, and a frame pulse having an opposite phase to the frame pulse of the first line signal. A synchronization signal for frame synchronization consisting of a multiplexed second line signal is interpolated, and in a synchronization signal detection circuit that detects the synchronization signal from the transmission signal, the first line signal input to the input terminal is interpolated. a detection means for detecting all or a part of the frame pulses and outputting a detection signal; a storage means for storing the detection signal; an inverting means for inverting the second line signal; a detection signal outputted when all or part of the frame pulse in the second line signal inverted by the inverting means is detected by the detecting means; and a detection signal output from the detecting means; The present invention is characterized in that it includes detection pulse generation means which receives the detection signal stored in the means and outputs a detection pulse.

[Effect]

In this invention, in order to detect all or part of the 71 norm pulses in the first line signal by the detection means,
It is not necessary to detect two full clocks of each of both line signals as in the prior art, and the number of transistors required for the detection means is largely reduced, and when implemented as an LSI, the circuit area can be reduced.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of the synchronization signal detection circuit of the present invention.

In the figure, 1- is a 1-bit input terminal, 10 is a detection means for detecting all the frame pulses of the first line signal of the frame synchronization signal and outputting a detection signal;
Two-stage shift register 101 and shift register 101
Outputs Q2 to Q14 of each stage except for the output Q1 of the first stage and the output Q142 of the final stage], 18 4-input NAND gates whose inputs are the outputs of 4 stages from the second stage side and 1
A gate pair 102 consisting of a total of 35 seven 4-input AND gates arranged alternately in parallel, and a shift register 101
The first stage output Q1. It consists of a 37-input AND gate 103 whose inputs are the output of each gate of the final stage Q142 and the gate pair]02.

Furthermore, 20 is a storage means for storing the detection signal of the detection means 1-0, and inputs the output of the detection means 1-0 and the acquisition clock φ, and when the output of the detection means 1-0 is H. AND gate 202 that provides a clock for data acquisition to clock input CLKA of register 201 only for the output of AND gate 103 of detection means 10 and register 201
EXOR gate 20 which receives the output of
It consists of 3.

At this time, the clock CLKB of the register 201 and the successive clock φB, which is out of phase with the clock φ^, are input.

Further, 30 is an EXOR gate as an inverting means for inputting the output of the storage means 20 and the synchronizing signal to the input terminal and inverting and outputting the second line signal of the synchronizing signal, and 40 is a detection pulse generating means. Yes, the output of register 201 and AN
AND gate 40 whose input is the output of D gate 103
1 and a register 402 that takes in the output of the AND gate 401 at the timing of clock φA and reads it out at the timing of clock φB.
The register 402 takes in the output and outputs an H detection pulse.

Next, the operation will be explained with reference to the timing chart shown in FIG.

First, at the time when the first line signal of the synchronization signal for frame synchronization is input, since the output of the register 201 is already in progress, the signal input to the input terminal 1 of the shift register 101 is inverted by the EXOR gate 30. The first line signal is input to the shift register 101 as is.

Then, the shift register 101 holds 142 clocks worth of data including the frame pulse in the first line signal, and the output Q1- of each stage of the shift register 1.01 is held.
-Q142, outputs Q2 to Q141 cause the outputs of each gate of gate pair 102 to become H in response to the H and L frame pulses of the first line signal to each gate of gate pair 1-02, and this Time shift register 101
The output Q1. Since Q142 is also at H, all inputs of AND gate 103 become H, and its output becomes H, as shown in FIG.

Next, as shown in FIG.
According to the output, the output of AND gate 202 is clocked φA
On the other hand, the output of the EXOR gate 203 becomes H due to the H output of the AND gate 103,
The register 201 takes in the H output of the EXOR gate 203 at the timing of the H output of the AND gate 202, and the output of the register 201- is inverted to H.

Then, as shown in the jlj2 figure, AND gate ] 03
The output of the detection means 1 becomes L, and the storage means 20 stores the output of the detection means 1 as L.
The H output as a detection signal due to -0 continues to be stored.

Furthermore, when the second line signal of the synchronization signal is input to the input terminal while the output of the register 201 is in the H state,
Since the second line signal to the input terminal 1- is inverted by the EXOR gate 30, the inversion of the second line signal causes the first line signal of the opposite phase to continue to the shift register 01. By the same operation as described above, the shift register 01 holds 142 clocks worth of data including frame pulses, and the output of each gate of the gate pair 102 becomes H, as shown in FIG. , all the inputs of the AND gate 103 become H, and the output becomes H again.

Since both inputs of the AND gate 401 become H due to the H output of the AND gate 103, the AND gate 4
The output of 01 becomes H, and as shown in FIG.
1's H output is taken in, the output of the register 402 becomes H for a period corresponding to one cycle of the clock φB at the timing of the clock φ, and the H detection pulse from the register 402 is sent to the subsequent circuit assuming that a synchronization signal for frame synchronization has been detected. is output to.

By the way, when calculating the number of T required in the configuration shown in Figure 1111, it is found that 2-input AND gates "202.401, 12 in total, 2-input EXOR gates 2
03, 30, total of 4, 37-input AND gate and gate pair 102, 17 4-input AND gates, total 246
18 4-input NAND gates with gate pairs 102, totaling 144, 142-stage shift register 01 and 17
28 transistors are required, for a total of 2134 transistors, which is significantly smaller than the conventional 5970 transistors.

Therefore, all of the frame pulses in the first line signal are detected by the detection means 1 consisting of a 142-stage shift register 0]-, etc.
0, it is not necessary to detect all the clocks of both line signals as in the past, and the number of transistors required for the detection means 10 can be significantly reduced. It is possible to reduce the size of the image.

Also, after detecting the frame pulse in the first line signal,
The detection result is stored in the storage means 20, and the frame pulse in the next inverted second line signal, that is, the signal equivalent to the first line signal, is detected again by the EXOR gate 30. Since a detection pulse is generated by the detection pulse generation means 40 based on the detection result stored in the storage means 30, highly reliable synchronous detection can be performed.

FIG. 3 shows a block diagram of another embodiment of the invention.

In this figure, what is different from FIG. 1 is a -33-stage shift register 111 and a 5-input AND gate whose inputs are the output Q1 of the first stage to the output Q5 of the fifth stage of shift register 1]1. 112 and 16 4-input N outputs from the sixth stage output Q6 to the final stage output Q133 of the shift register 111, each of which receives outputs from four stages from the sixth stage side.
A gate pair 113 consisting of an AND gate and 16 4-input AND gates arranged in sequence and in parallel, a total of 32;
The detection means 11 is constituted by a 33-input AND gate which receives the output of the ND gate 112 and the output of each gate of the gate pair 113. 2
03 +, : is input, and the second half of the frame pulse in the first line signal and the H part following this frame pulse are detected by the conno detection means 1].

Next, the operation of the detection means]-1 will be explained. First, at the time when the first line signal is input, the output of the register 201 is L, so that the signal input to the input terminal 1 is It is input to the shift register 111 as it is without being inverted by the shift register 1.
A first line signal is input to 11.

Then, the shift register 111 holds data for 133 clocks including the frame pulse in the 1st line signal, and at this time, the shift register 111 holds 16 bears of H and the data of the frame pulse starting from the end of the frame pulse. When the following five clocks of H data are held, the output of the AND gate 112 and the gate pair 113
All the outputs of each gate become H, and AND gate 11
All the inputs of the AND gate 114 become H, and the output becomes H. From then on, the H output of the AND gate 114 as a detection signal is stored in the storage means 2° by the same operation as in the case of FIG.
Thereafter, the output of AND gate 114 is inverted to L.

Furthermore, when the second line signal is input to the input terminal 1, the second line signal is inverted by the EXOR gate 3o, and a signal equivalent to the -th line signal is input to the shift register 111. By the same operation as described above, the second half of the frame pulse and the H part for 5 clocks following this frame pulse are held in the shift register 111, and the output of the AND gate 112 and the gate pair 1
All the outputs of the 13 gates become H, and all the inputs of the AND gate 114 become H again, and this AND gate 11
4 and the H output of the register 201 of the storage means 2o, the output of the AND gate 401 (7) becomes H, and as in the case of FIG.
An H detection pulse for one cycle of is output.

By the way, in the configuration shown in FIG. 3, the required T
When calculating the r number, two-input AND gates 202, 40
1 for a total of 12, 2-input EXoR gate 203.30 for a total of 4, 5-input AND gate 112.33 input AN
The D gate 114 and the 16 4-input AND gates of the gate pair 113 make up another 240 pieces, the 16 4-input NAND gates of the gate pair 113 make a total of 128 pieces, and the 133-stage shift register] 11 makes it 1596 pieces. A total of 1980 transistors are required, which is still significantly less than the conventional method and even less than the case of FIG.

Therefore, as in the case of FIG. 1, the circuit area can be reduced when integrated into an LSI.

FIG. 4 is a block diagram of another embodiment of the present invention.

This figure differs from FIG. 1 in that it has a 133-stage shift register 121 and a 5-input A which receives the output Q1 of the first stage to the output Q5 of the fifth stage of the shift register 121.
Output Q of the 132nd stage, one stage before the final stage, from the ND gate 122 and the output Q7 of the seventh stage of the shift register 111
Of the outputs Q7 to Q132 up to 132, 2
A gate pair 123 consisting of 16 2-input NAND gates and 16 2-input AND gates, each of which takes the output of each stage as input, and a total of 32 gates arranged in parallel in order, and the output and gate of the AND gate 122. The detection means 12 is constituted by a 33-input AND gate 124 which receives the output of each gate of the pair 123, and the output of the AND gate 124 is ANDed.
gates 202 and 401, and an EXOR gate 203, and this detecting means 12 detects the second half of the frame pulse in the first line signal and a characteristic part of the H and L periods, and the H following this frame pulse. This is to detect this part.

In such a configuration, when the first line signal is input to the shift register 1.21, as in the case of FIG.
When 33 clocks' worth of data is held in the shift register 121-, and when the shift register 121 holds 16 bears of H from the latter half of the frame pulse and 5 clocks' worth of H data following the frame pulse, The output of the AND gate 122 and the output of each gate of the gate pair 123 all become H, all the inputs of the AND gate 124 become H, and the output becomes H, so the I-no resistor is activated by the same operation as that shown in FIG. An H detection pulse is output from 402.

In this case, even if the duty ratio of the frame pulse is no longer 50% for some reason, each NAND of the gate pair 123 is
, AND gate detects two clocks between the L period and the H period of the frame pulse, so even if the duty ratio of the frame pulse changes somewhat, the frame pulse can be reliably detected.

By the way, T required in the configuration shown in FIG.
If you calculate the numbers, you will get a 2-input AND gate: 202.401, 12 in total, 2-input EXOR gate 2
03.30, total of 4, 5 input AND game) 112.3
A total of 176 3-input AND gates 1-1.14 and 16 2-input AND gates in gate pair 123, a total of 64 in 16 2-input NAND gates in gate pair 113,
A 133-stage shift register 21 has 1596 transistors, which means a total of 1852 transistors are required, which is still significantly less than the conventional method.1. The number of cases required is even less than that in either of FIGS. 1 and 3.

Therefore, it goes without saying that the number of required transistors can be significantly reduced, but by detecting the characteristic parts of the H and L periods of the frame pulse, even if the number of transistors is reduced, the duty ratio of the frame pulse will vary slightly. frame pulses can be reliably detected regardless of the

In each of the above embodiments, the storage means 20 is replaced by the register 20.
1, an AND gate 202, and an EXOR gate 203, but the present invention is not limited to this, and for example, a 1-bit counter with carry-out may be used.

Furthermore, in each of the above embodiments, the register 2 of the storage means 2o
AND gate 202 to store the clock in 01.
However, it is not limited to this and may be given externally. For example, it can be realized by also using the output of a counter that counts 480 clocks used in other circuits based on the MUSE format. By using the counter as the counter, it becomes possible to further reduce the number of transistors required for the synchronization signal detection circuit itself.

Furthermore, the detection pulse generating means 40 is not limited to the configuration of each of the above embodiments.

〔Effect of the invention〕

As described above, according to the present invention, since all or part of the frame pulse in the first line signal is detected by the detection means, it is not necessary to detect all clocks of both line signals as in the conventional case. The number of transistors required for the detection means can be significantly reduced, and L S
When integrated, the circuit area can be reduced.

Also, after detecting the frame pulse in the first line signal,
The detection result is stored in the storage means, and the next second line signal is inverted by the inversion means, and the frame pulse in the signal, that is, the signal equivalent to the first line signal, is detected again, and this detection result and the signal are stored. Since the detection pulse is generated based on the detection result stored by the means, highly reliable synchronous detection can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the synchronization signal detection circuit of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIGS. 3 and 4 are other embodiments of the present invention, respectively. Example block wiring diagram, Fig. 5 is a waveform diagram of a synchronizing signal in MUSE format, Fig. 6 is a block wiring diagram of a conventional synchronous signal detection circuit, and Fig. 7 is an evening timing chart for explaining the operation of Fig. 6. It is. In the figure, 10. 1.1.12 is a detection means, 20 is a storage means, 30 is an EXOR gate, and 40 is a detection pulse generation means. Note that the same reference numerals in each figure indicate the same parts, and the t- indicates corresponding parts.

Claims (1)

[Claims] (1) A first line signal in which a frame pulse is multiplexed on a transmission signal including line signals of a plurality of lines;
A synchronization signal detection circuit that interpolates a frame synchronization signal consisting of a frame pulse of a line signal and a second line signal multiplexed with a frame pulse of opposite phase, and detects the synchronization signal from the transmission signal, a detection means for detecting all or part of the frame pulse in the first line signal input to an input terminal and outputting a detection signal; a storage means for storing the detection signal; and a storage means for storing the detection signal. an inverting means for inverting the second line signal to the input terminal according to a signal storage result; and all or part of the frame pulse in the second line signal inverted by the inverting means is detected by the detecting means. 1. A synchronization signal detection circuit comprising detection pulse generation means that receives a detected and output detection signal and the detection signal stored in the storage means and outputs a detection pulse.