JPH04323865A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve an yield by using a word line as an opposed electrode of a capacity element of a memory cell. CONSTITUTION:Charge storage electrodes 2al of a capacity element of a memory cell corresponding to a bit line 5a and a word line 1l are provided on a gate electrode (word line 1m) of a MOS transistor of a memory cell corresponding to a bit line 5b and a word line 1m through a capacitive insulating film. That is, a role of the opposed electrode is shared by the line 1m. The lines 1l, 1m become active at different timings, and the electrode 2al and the line 1m are insulated in a DC manner. Accordingly, no problem in an operation occurs. Thus, a multilayer structure can be alleviated, a step difference of a connecting opening 4 of bit lines 5a, 5b to a diffused layer is reduced, and its yield is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having vertically stacked memory cells suitable for high integration and large capacity.

0002

[Prior Art] Figure 3 shows the structure of a conventional vertically stacked memory cell.
and shown in FIG. FIG. 3 is a plan view of a vertically stacked memory cell, and FIG. 4 is a cross-sectional view taken along the line X--X in FIG.

Next, the manufacturing process and structure of a conventional vertically stacked memory cell will be explained. In a conventional vertically stacked memory cell, first a word line 1l of a polysilicon film is formed, and then an interlayer insulating film 14 is applied over the entire surface. Thereafter, a capacitor opening is made in the interlayer insulating film 14 in order to connect the capacitor element 9-1 and the charge storage electrode 2al (polysilicon film) at a predetermined position. Furthermore, a polysilicon film is applied to the entire surface and patterned into the desired shape through a series of steps, forming the charge storage electrode 2.
al etc. are formed. Furthermore, a capacitive insulating film 10 is applied over the entire surface by thermal expansion or CVD technology. Furthermore, a polysilicon film that will become the other electrode is applied and patterned into a desired shape through a series of steps to form the counter electrode 13. In FIG. 3, the opening 12 of the counter electrode 13 is shown. Through the steps up to this point, a capacitive element of a memory cell is completed in which the capacitive insulating film 10 is disposed between the charge storage electrode 2al etc. and the counter electrode 13. Thereafter, an interlayer insulating film 11 is applied, and holes are made in the interlayer insulating film at predetermined positions to connect the bit line side diffusion layer 42 and the bit line 5a. Further, a bit line wiring film is applied to the entire surface and patterned into a desired shape through a series of steps to form a bit line 5a.

0004

[Problems to be Solved by the Invention] This conventional vertically stacked memory cell requires a charge storage electrode and a counter electrode in order to form the capacitive element of the memory cell in addition to the word line, which requires a large manufacturing process. Not only that, but with the multilayer structure, the step difference in the connecting hole between the bit line and the diffusion layer on the bit line side becomes larger, which causes problems in terms of yield such as increased contact resistance and bit line disconnection. There were many.

[0005]

Means for Solving the Problems The present invention provides a semiconductor memory device having vertically stacked memory cells including MOS transistors and capacitive elements, in which a capacitance of the vertically stacked memory cells corresponding to a predetermined bit line and a word line is provided. The element has its charge storage electrode provided via a capacitive insulating film on the word line which is the gate electrode of the MOS transistor of the memory cell corresponding to the bit line and word line adjacent to the predetermined bit line and word line, respectively. That is what it is.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view showing a memory cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line X--X in FIG.

An element isolation insulating film 8 is formed on a P-type silicon substrate 7, word lines 1l, 1m, ... are formed, and a diffusion layer 9-1 on the capacitor side and a diffusion layer 9-2 on the bit line side are ion-implanted. Since the technique used to form the transistor is the same as that of a conventional MOS transistor, a detailed explanation will be omitted. Next, a capacitor insulating film 10 is formed on the word lines 1l, 1m, . . . by thermal oxidation or CVD technology. Furthermore, in order to connect the diffusion layer 9-1 on the capacitor side and the charge storage electrode, openings are made in the insulating film at predetermined positions using lithography and etching techniques, and a polysilicon film is then applied to the entire surface, using lithography techniques. , patterned into a desired shape using etching technology, and formed a charge storage electrode 2al,
2bm,... are formed. Through the steps up to this point, a capacitive element of a memory cell with a capacitive insulating film 10 disposed between the charge storage electrode and the word line electrode is completed. Thereafter, an interlayer insulating film 11 is applied, holes are formed in the interlayer insulating film at predetermined positions using lithography and etching techniques, and a bit line wiring film is further applied over the entire surface, and the required areas are formed using lithography and etching techniques. The bit lines 5a,
5b,... are formed.

The charge storage electrode 2al of the capacitive element of the memory cell corresponding to the bit line 5a and the word line 1l is connected to the bit line 5a.
A capacitive insulating film 1 is placed on the gate electrode (word line 1m) of the MOS transistor of the memory cell corresponding to b and the word line 1m.
0. That is, the word line 1m plays the role of the counter electrode. Word line 1l and 1m
are activated at different timings, and since storage electrode 2al and word line 1m are electrically isolated from each other, no operational problem occurs.

0010

[Effects of the Invention] As explained above, the present invention uses a word line as the counter electrode of the capacitive element of the memory cell, which eliminates the need for a polysilicon film dedicated to the counter electrode, which was previously required, and greatly reduces the number of manufacturing steps. In addition to this, the multilayer structure can be relaxed, and the level difference in the connecting hole between the bit line and the diffusion layer can be reduced, resulting in an improvement in yield.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment of the present invention.

FIG. 2 is a sectional view taken along line XX in FIG. 1;

FIG. 3 is a plan view showing a conventional example.

FIG. 4 is a sectional view taken along the line XX in FIG. 3;

[Explanation of symbols]

1l, 1m Word lines 2al, 2bm Charge storage electrodes 3al, 3bm Contact hole 4 between charge storage electrode and diffusion layer Contact hole 5a, 5 between bit line and diffusion layer
b Bit line 6 Edge of element isolation insulating film 7 P-type silicon substrate 8 Element isolation insulating films a-1, a-2 N-type diffusion layer 10 Capacitive insulating film 11 Interlayer insulating film 12 Opening 13 of counter electrode 13 Counter electrode 14 Interlayer insulation film

Claims (1)

[Claims] 1. In a semiconductor memory device having a vertically stacked memory cell including a MOS transistor and a capacitor, the capacitor of the vertically stacked memory cell corresponding to a predetermined bit line and word line has its charge storage electrode A semiconductor memory device comprising a capacitive insulating film provided on a word line which is a gate electrode of a MOS transistor of a memory cell corresponding to a bit line and word line adjacent to a predetermined bit line and word line, respectively. .