JPH04323875A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device formed on an insulating amorphous material and a method of manufacturing the same.

0002

[Background Art] In recent years, semiconductor devices have become highly integrated, and
Mass production of MDRAM, 1MSRAM, etc., 16M, 64MD
Development and prototyping of RAM, 4MSRAM, etc. is underway. In the future, as the density of these semiconductor devices progresses further, it is expected that expectations for the realization of semiconductor devices with three-dimensional structures will further increase. Taking SRAM as an example, 4M
In the above SRAM, the memory cells are made of high-resistance poly-
4-T type SRAM using Si or n
6 that formed channel and p-channel MOSFETs
-SRA with stacked CMOS structure instead of T-type SRAM
M is being considered and prototyped. In a stacked CMOS structure, an n-channel MOSFET is formed on a silicon substrate,
It has a structure in which p-channel poly-Si TFTs are stacked with an insulating material in between, and has the advantages of 4-T type and 6-T type. That is, the p channel is
-By forming with Si TFT and creating a stacked structure, a CMOS structure can be realized with almost the same cell size as a 4-T type, and SR has excellent high integration, soft error resistance, and low power consumption.
AM can be realized.

0003

[Problem to be solved by the invention] However, the conventional pol
The structure and manufacturing method of y-SiTFT has the following problems. (1) Since it is necessary to perform annealing at about 550° C. to 650° C. for several hours to several tens of hours, the throughput is low. (2) Solid-phase growth annealing at about 550°C to 650°C alone cannot sufficiently improve the crystallinity such as the crystallization rate of polycrystalline silicon, forming a TFT with a sufficient on-off ratio. difficult to do. (3) Since source/drain regions are formed using the gate electrode as a mask using the self-alignment method, an off-leak current occurs due to current generated by electron-hole pairs at the drain end, and the off-state current cannot be suppressed. (4) Reducing the film thickness in the channel region has the effect of improving field effect mobility and reducing off-state current, so it is desirable to reduce the film thickness to about 300 to 500 Å or less. When the source/drain regions are made thinner, the source/drain regions are also made thinner, resulting in an increase in the sheet resistance and contact resistance of the source/drain regions. There were other problems. Therefore, the present invention uses a simpler and more practical TFT structure and its manufacturing method to form highly crystalline polycrystalline silicon with good reproducibility, and to form polycrystalline silicon with high mobility and a large on-off ratio.
- An element structure for forming a Si TFT and a method for manufacturing the same are provided.

0004

[Means for Solving the Problems] A semiconductor device of the present invention includes:
1) In a semiconductor device in which the channel region of an insulated gate semiconductor device is formed of a non-single-crystalline semiconductor mainly composed of silicon, a gate electrode having a sidewall, a low-concentration layer formed in a part of the non-single-crystalline semiconductor region, etc. It is characterized by having at least a region containing an impurity and a thin film containing a high concentration impurity forming source/drain regions formed on the region containing a low concentration impurity.

2) The semiconductor device is characterized in that it is formed as an element of a stacked part of a three-dimensional IC.

3) The channel region is characterized in that the polycrystalline semiconductor layer mainly composed of silicon has a thickness of 50 Å to 250 Å.

4) The crystallization rate of the polycrystalline semiconductor layer is 99
．． It is characterized by being 5% or more. 5) The thin film forming the source/drain region is made of polycrystalline silicon doped with impurities.

6) The polycrystalline silicon layer doped with impurities has a resistivity of 5×10 −4 Ω·cm or less.

7) In a semiconductor device in which the channel region of an insulated gate semiconductor device is formed of a non-single crystal semiconductor mainly composed of silicon, a gate insulating layer is formed under the non-single crystal semiconductor layer mainly composed of silicon forming the channel region. a lower gate electrode formed with a film sandwiched therebetween; an upper gate electrode having sidewalls formed on top of a non-single-crystalline semiconductor layer mainly made of silicon forming the channel region with a gate insulating film sandwiched therebetween; a non-single-crystalline semiconductor region containing a low concentration of impurities formed adjacent to a non-single-crystalline semiconductor region mainly composed of silicon; a source/drain formed on the non-single-crystalline semiconductor region containing the low-concentration impurities; It is characterized by having at least a thin film containing a high concentration impurity forming a region.

8) The gate end of the lower gate electrode is located inside the outer end of the sidewall of the upper gate electrode.

Furthermore, the method for manufacturing a semiconductor device of the present invention includes:
9) A method for manufacturing a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a non-single crystal semiconductor mainly composed of silicon, including a step of forming a non-single crystal semiconductor layer, a step of forming a gate insulating film, and a step of forming a gate insulating film. form an electrode,
forming a region containing a low concentration of impurity in a part of the non-single crystal semiconductor layer by a self-alignment method; forming a sidewall on the gate electrode; and forming a region on at least a part of the region containing the low concentration of impurity. The method is characterized in that it includes at least a step of selectively forming a thin film containing a high concentration of impurity to form source/drain regions.

10) In the step of forming the thin film constituting the source/drain region, the thin film is selectively formed under the condition that the thin film is not formed on at least the sidewalls.

11) A non-single-crystal semiconductor layer mainly composed of silicon forming a channel region is coated with at least a gas containing at least one of fluorine and chlorine, and a doping gas such as diborane is further added to the gas. The method is characterized in that it includes at least a step of exciting and decomposing into a plasma state and forming a film.

[0014]

【Example】

(Embodiment 1) FIG. 1 is an example of a cross-sectional view of a semiconductor device in an embodiment of the present invention. FIG. 1 shows a simple example of application to a three-dimensional transistor (stacked CMOS).

In FIG. 1, 101 is a silicon substrate;
02 is a p-well region, 103 is an element isolation region, 10
4 is a gate insulating film, 105 is a lower gate electrode, 106 is an n+ region forming a source/drain region, 107 is a gate insulating film, 108 is a polycrystalline silicon layer, 109 is a gate insulating film, 110 is an upper gate electrode, 111 is a 114 is a contact hole, 112 is a p+ region which becomes a source/drain region, and 113 is a p+ region on a gate electrode.
Low resistance thin film formed from the same process and the same element material as the region, 1
15 is wiring. The poly-SiTFT of the present invention is
It is characterized by having a self-aligned structure using sidewalls, and is characterized by a structure in which films are selectively formed in source and drain regions. In the present invention, the sidewalls can prevent short circuits between the source/drain region and the gate electrode, and at the same time, the sidewalls can form an offset structure. -Emissio
Off-leakage current caused by n-current etc. is suppressed, and a sufficient on-off ratio can be obtained.

FIG. 2 is another example of a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 2, 201 is a silicon substrate;
02 is a p-well region, 203 is an element isolation region, 20
4 is a gate insulating film, 205 is a lower gate electrode, 206 is an n+ region forming a source/drain region, 207 is a gate insulating film, 208 is a polycrystalline silicon layer, 209 is a gate insulating film, 210 is an upper gate electrode, 211 is a p-region, 2
12 is a side wall, 213 is a p+ region, and 214 is a contact hole. poly-SiTFT of the present invention
is characterized by an LDD structure in which a p- region 211 and a p+ region 213 are formed using sidewalls. Figure 1
Although the process is slightly more complicated than that of the offset gate structure shown in FIG.

FIG. 3 is another example of a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 3, 301 is a silicon substrate;
02 is a p-well region, 303 is an element isolation region, 30
4 is a gate insulating film, 305 is a lower gate electrode, 306 is an n+ region forming a source/drain region, 307 is a gate insulating film, 308 is a polycrystalline silicon layer, 309 is a gate insulating film, 310 is an upper gate electrode, 311 is a p-region, 3
12 is a side wall, 313 is a p+ region which becomes a source/drain region, 314 is a contact hole, 315 is a low resistance thin film formed on the gate electrode in the same process and using the same element material as the p+ region, and 316 is a wiring. pol of the invention
The y-Si TFT is characterized by having a self-aligned structure using sidewalls, and has a p-region 311.
After forming, sidewalls are formed and p+ regions 313 which become source/drain regions are selectively formed.
It realizes an LDD structure.

Note that FIGS. 1 to 3 take as an example a double gate structure in which a polycrystalline silicon layer is sandwiched between two upper and lower gate electrodes with a gate insulating film interposed therebetween. By adopting such a double gate structure, the thickness of the polycrystalline silicon layer is reduced to 2.
When the thickness is 50 Å or less, preferably 150 Å or less, the on-current increases dramatically, and the gate length is 1.2 μm and the gate width is 0.
．． When the drain voltage was 3V and the gate voltage was 3V, an on-current of about 0.4×10 −6 A was obtained with a 6 μm P-channel transistor having the structure shown in FIG. 1. Furthermore, Figure 2
By employing the LDD structure shown in Figure 1, the on-current characteristics were improved as the resistance component in the offset region was reduced, and approximately 1 x 10-6 A was obtained with the above transistor size. Furthermore, by adopting the TFT structure shown in Figure 3,
Thinning of the polycrystalline silicon layer, which is a problem in the structure shown in FIG.
The TFT characteristics are improved by following the p+
An increase in the sheet resistance of the region can be prevented. As a result, even when the film was thinned to 150 Å or less, it was possible to prevent a decrease in on-current due to an increase in resistance component or poor contact, and an on-current of approximately 3 x 10-6 A was obtained under the above transistor size and measurement conditions. .

Furthermore, by employing the offset gate structure or LDD structure shown in FIGS. 1 to 3, the off-state current can be reduced by about one order of magnitude or more compared to the conventional structure. For example, in a P-channel transistor with a gate length of 1.2 μm and a gate width of 0.6 μm, the off-state current when the drain voltage is 3 V and the gate voltage is 0 V can be suppressed to 1×10 −14 A or less. As a result, an on-off ratio of 7 to 8 digits or more was obtained. still,
In order for the offset structure or LDD structure of the upper electrode to function effectively, it is important that the lower electrode end is located inside the outer edge of the sidewall of the upper electrode. Therefore, it is desirable that the gate length of the lower electrode be equal to or narrower than that of the upper electrode. Figure 4 shows
1 is an example of a manufacturing process diagram of a semiconductor device in an embodiment of the present invention. In addition, in FIG. 4, the pol of the LDD structure shown in FIG.
A manufacturing process diagram for producing a y-SiTFT is shown.

In FIG. 4, (a) shows a silicon substrate 4
In this step, a p-well region 402 is formed in 01, and an element isolation region 403 is formed using the LOCOS oxidation method.

(b) shows that after forming the gate insulating film 404,
This is a step of forming a lower gate electrode 405 using poly-Si or the like as an element material, and then patterning it into a predetermined shape to form an n+ region 406 that forms a source/drain region.

(c) forms a gate insulating film 407;
This is a step of forming a polycrystalline silicon layer 408 and patterning it into a predetermined shape. Methods for forming gate insulating films include low-temperature deposition methods such as CVD, plasma CVD, ECR-PCVD, photo-CVD, and sputtering, which reduce the redistribution of impurities in elements formed on silicon substrates. This is desirable for the purpose of prevention.

Next, as a method for forming the polycrystalline silicon layer, plasma CVD (PCVD) is used at a substrate temperature of 300°C.
Polycrystalline silicon is grown to a thickness of 50 Å at a low temperature of about ℃~450℃.
A method of forming a film with a thickness of about 1500 Å is effective. In addition to SiH4, Si2H6, etc., fluorine (F) is used as a reaction gas.
A high quality polycrystalline silicon film can be formed at a low temperature by mixing an appropriate amount of a reactive gas containing elements such as , chlorine (Cl), and the like. An example of film forming conditions is shown below. As a reaction gas, SiH
4. Using dichlorosilane (SiH2Cl2), H2,
For example, the mixing ratio is SiH4:SiH2Cl2=1:20
~1:200 or so, SiH4:H2=1:100~1:
Set the temperature to about 1000 and increase the substrate temperature to 300°C to 450°C.
RF power is applied to decompose the reaction gas and form a polycrystalline silicon film. Regarding film thickness, when the polycrystalline silicon layer is made thinner, the off-state current decreases and Vth(
A phenomenon in which the threshold voltage (threshold voltage) decreases is known. Therefore, the thickness of the polycrystalline silicon layer is preferably 500 Å or less,
A thickness of approximately 50 Å to 250 Å is particularly desirable. Therefore, it is particularly important to form such a thin film of high quality polycrystalline silicon. When the substrate temperature is below 300°C, the crystallization rate is low and no <220> orientation is observed, but when the substrate temperature is about 400°C to 450°C, the crystallization rate is 50 Å to 250°C.
Even with a thin film on the order of Å, it is possible to form high-quality polycrystalline silicon with <220> orientation and a crystallization rate of 98% or more. In addition, in terms of increasing the crystallization rate, the substrate temperature is 450℃.
Films formed at temperatures between ℃ and 600℃ are even better,
A crystallization rate of 99.5% or more can be achieved and is effective in increasing the on-current and reducing the off-current of TFTs.

As described above, according to the present invention, a high-quality polycrystalline silicon film can be formed at low temperatures, so that high-performance three-dimensional ICs, including the stacked CMOS shown in this embodiment, can be fabricated on a Si wafer. It can be manufactured at low temperatures without damaging the device. Note that although this example shows the case where SiH2Cl2 is used as the reaction gas, the present invention is not limited to this. For example, SiCl4, SiH2Cl
2, SiHCl3, Cl2, SiF4, SiHF3, S
Si
By mixing appropriate amounts of reactive gases such as H4, Si2H6, Si3H8, etc., high-quality polycrystalline silicon can be formed at low temperatures. Further, the same effect can be obtained by using hydrogen gas instead of a reactive gas having etching properties and containing at least one of F (fluorine) and Cl (chlorine).

Also, it is extremely effective to control Vth (threshold voltage) by doping the channel region with impurities. Polycrystalline silicon TF formed by solid phase growth method
At T, the N-channel transistor tends to shift Vth in the depletion direction, and the P-channel transistor tends to shift in the enhancement direction. Moreover, when the above-mentioned TFT is hydrogenated, this tendency becomes more pronounced. Therefore, 1015 to 1019/cm3 is applied to the channel area.
By doping a certain amount of impurities, the shift in Vth can be suppressed. Therefore, by mixing a doping gas such as B2H6 in addition to a gas containing chlorine or fluorine such as SiH4 and SiH2Cl2, channel doping can be performed without using ion implantation. An example of film forming conditions is SiH4+SiH2Cl2:B
2H6=1: By mixing about 0.1 ppm to 0.1%, Vth control becomes possible. In particular, by optimizing the doping amount, Vth can be controlled so that the off-state currents of both the P-channel transistor and the N-channel transistor are minimized. Therefore, even when forming a CMOS type TFT element, Vth can be controlled for both Pch and Nch by introducing impurities at the same concentration without selectively doping the channels. Further, according to the present invention, channel doping can be performed simultaneously in the step of forming polycrystalline silicon for the channel portion.

(d) is a step of forming a gate insulating film 409. CVD is the method for forming the gate insulating film.
method, plasma CVD method, ECR-PCVD method, photoCVD
A low-temperature film formation method such as a method or a sputtering method is preferable for the purpose of preventing redistribution of impurities in an element formed on a silicon substrate.

Step (e) is a step in which after forming the upper gate electrode 410, a p- region 411 is formed by ion implantation, and then a sidewall 412 is formed. In this embodiment, a TFT having a double gate structure in which a polycrystalline silicon layer is sandwiched between an upper gate electrode and a lower gate electrode with a gate insulating film interposed therebetween is taken as an example. An example of the manufacturing method is shown below. First, the gate electrode 410 is formed of polycrystalline silicon doped with impurities and patterned into a predetermined shape. As a method for forming the polycrystalline silicon layer, plasma CVD method (
There is a method of forming a polycrystalline silicon film with a thickness of about 500 Å to 4000 Å at a low substrate temperature of about 300° C. to 450° C. using PCVD method.

An example of film forming conditions is shown below. Monosilane (SiH4), dichlorosilane (S
iH2Cl2), H2, and the mixing ratio is changed to, for example, SiH
4: SiH2Cl2 = about 1:20 to 1:200, Si
Set H4:H2=1:100 to 1:1000,
Using diborane (B2H6), phosphine (PH3), arsine (AsH3), etc. as a doping gas,
For example, SiH4:PH3=1:0.002 to 1:0.
Mix at a mixing ratio of about 0.04. Set the substrate temperature to 300℃~4
The temperature is maintained at approximately 50° C., and RF power is applied to decompose the reactive gas, thereby forming a film of low resistance polycrystalline silicon doped with impurities. The sheet resistance of the polycrystalline silicon formed in this way is 30 to 50 Ω/□ at a film thickness of 2000 Å, and a low-resistance polycrystalline silicon can be formed at a low temperature. Note that the method for forming polycrystalline silicon is not limited to this. Next, using the gate electrode 410 as a mask,
B (boron) etc. at a dose of 1×1013 to 1×1015
Ion implantation is performed to form a p- region. Finally, sidewalls 412 are formed. Normal pressure CVD method,
Insulating films such as SiOx and SiNx are deposited to a thickness of 500 Å to 300 Å by sputtering, plasma CVD, ECR-PCVD, etc.
The insulating film is formed to a thickness of approximately 0 Å, and the insulating film is etched by anisotropic etching to form a sidewall 411.

In (f), a contact hole 415 is opened in the interlayer insulating film 407, and a polycrystalline silicon thin film doped with impurities is placed on the polycrystalline silicon layer 408 and on the gate electrode 41.
4 and selectively within the contact hole to form a p+ region 413 that will become a source/drain region, and to reduce defects existing at grain boundaries, a plasma atmosphere of a gas containing at least hydrogen gas, etc. In this step, the wiring 416 is formed by hydrogenation using a method such as exposure to water. In this embodiment, polycrystalline silicon doped with impurities is used in the p+ region 41.
3, a case where the electrodes are selectively formed on the gate electrode 414 and in the contact hole will be taken as an example. An effective method for forming the polycrystalline silicon layer is to selectively grow polycrystalline silicon to a thickness of about 500 Å to 3500 Å using a plasma CVD method (PCVD method) at a low substrate temperature of about 300° C. to 450° C.

That is, polycrystalline silicon doped with impurities is selectively grown only on polycrystalline silicon 408 and 410 and in the contact hole 415, and polycrystalline silicon is grown in other regions (interlayer insulating film 407 and sidewall 412). By using a method that does not involve forming a silicon film, a self-aligned TFT with an offset gate structure can be formed at a low temperature. In particular, in the present invention, by providing sidewalls and selectively growing them, short circuits between the gate electrode and the source/drain regions can be completely prevented. The method for forming the polycrystalline silicon layer is plasma CVD (PCVD).
An effective method is to selectively grow polycrystalline silicon to a thickness of about 500 Å to 3500 Å at a low substrate temperature of about 300° C. to 450° C. An example of film forming conditions is shown below. Monosilane (SiH4), dichlorosilane (SiH2Cl2), and H2 are used as reaction gases, and the mixing ratio is set to, for example,
SiH4:SiH2Cl2 = about 1:20 to 1:200, SiH4:H2 = about 1:100 to 1:1000, and diborane (B2H6), phosphine (PH3), arsine (AsH3), etc. are used as the doping gas. , for example, SiH4:B2H6=1:0.002~
Mix at a mixing ratio of about 1:0.04. Set the board temperature to 30
The temperature is maintained at approximately 0° C. to 450° C., RF power is applied to decompose the reactive gas, and low resistance polycrystalline silicon doped with impurities is formed. The sheet resistance of the polycrystalline silicon formed in this way is 30 to 50 Ω/□ at a film thickness of 2000 Å, and a low-resistance polycrystalline silicon can be formed at a low temperature. Note that the method for forming polycrystalline silicon is not limited to this.

Note that the present invention is not limited to the embodiments shown in FIGS. 1 to 4. The present invention can be applied to insulated gate semiconductor devices in general, including poly-Si TFTs formed on insulating substrates, as well as insulated gate semiconductor devices in which at least a portion of the channel region is formed of a non-single crystal semiconductor.

[0034]

[Effects of the Invention] As described above, according to the present invention, p
The on-current characteristics and off-current characteristics of the oly-Si TFT are significantly improved. Further, according to the TFT structure and the manufacturing method thereof of the present invention, a TFT having an offset structure or an LDD structure can be formed at low temperature and by a simple process. Also,
In addition to three-dimensional ICs, the present invention can also be applied to liquid crystal display panels and contact image sensors, and these elements can be fabricated on glass substrates at low temperatures.

In addition to the poly-Si TFTs shown in the embodiments of FIGS. 1 to 4, the present invention can be applied to insulated gate semiconductor devices in general in which at least a portion of the channel region is formed of a non-single crystal semiconductor. can.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a semiconductor device in an embodiment of the present invention.

[Explanation of symbols]

Claims (11)

[Claims] Claim 1: In a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a non-single-crystalline semiconductor mainly composed of silicon, a gate electrode having a sidewall is formed in a part of the non-single-crystalline semiconductor region. 1. A semiconductor device comprising at least a region containing a low concentration of impurity, and a thin film containing a high concentration of impurity forming a source/drain region formed on the region containing the low concentration of impurity. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed as an element of a stacked part of a three-dimensional IC. 3. The semiconductor device according to claim 1, wherein the polycrystalline semiconductor layer mainly composed of silicon forming the channel region has a thickness of 50 Å to 250 Å. 4. The crystallization rate of the polycrystalline semiconductor layer is 99.
．． Claims 1 and 2 characterized in that it is 5% or more.
4. The semiconductor device according to claim 3. 5. The semiconductor device according to claim 1, wherein the thin film forming the source/drain region is made of polycrystalline silicon doped with impurities. 6. The semiconductor device according to claim 5, wherein the impurity-doped polycrystalline silicon layer has a resistivity of 5×10 −4 Ω·cm or less. 7. In a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a non-single-crystalline semiconductor layer mainly composed of silicon, a gate insulator is provided below the non-single-crystalline semiconductor layer mainly composed of silicon, which forms the channel region. a lower gate electrode formed with a film sandwiched therebetween; an upper gate electrode having sidewalls formed on top of a non-single-crystalline semiconductor layer mainly made of silicon forming the channel region with a gate insulating film sandwiched therebetween; a non-single-crystalline semiconductor region containing a low concentration of impurities formed adjacent to a non-single-crystalline semiconductor region mainly composed of silicon; a source/drain formed on the non-single-crystalline semiconductor region containing the low-concentration impurities; 1. A semiconductor device comprising at least a thin film containing a highly concentrated impurity forming a region. 8. The semiconductor device according to claim 7, wherein a gate end of the lower gate electrode is located inside an outer end of a sidewall of the upper gate electrode. 9. A method for manufacturing a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a non-single-crystalline semiconductor mainly composed of silicon, including a step of forming a non-single-crystalline semiconductor layer, and forming a gate insulating film. a step of forming a gate electrode and forming a region containing a low concentration impurity in a part of the non-single crystal semiconductor layer by a self-alignment method; a step of forming a sidewall on the gate electrode; 1. A method of manufacturing a semiconductor device, comprising at least a step of forming a thin film containing a high concentration of impurity to selectively form a source/drain region on at least a part of the region. 10. The semiconductor according to claim 9, wherein in the step of forming the thin film forming the source/drain region, the thin film is selectively formed under conditions that the thin film is not formed on at least sidewalls. Method of manufacturing the device. 11. A non-single-crystal semiconductor layer mainly composed of silicon forming a channel region is prepared by using at least a gas containing at least one of fluorine and chlorine, and further adding a doping gas such as diborane. 11. The method of manufacturing a semiconductor device according to claim 9, further comprising at least the step of exciting and decomposing into a plasma state and forming a film.