JPH04324367A - Pulse train conversion circuit for rotary encoder - Google Patents

Abstract

PURPOSE:To easily remove pulse noise by detecting the pulse noise to remove from a pulse train a pulse having timing that coincides with a pulse due to noise. CONSTITUTION:Pulses of phases A and B mixed with pulse noises are inputted into a D-flip flop F1 and F11. An output of the F1 is inverted to a L level from an H level while an output of the F11 is inverted to the H level from the L level and the pulses via F2 and F12 are supplied to NOR gates H3 and H4 and an NAND gate G15 of a noise detection circuit 7 via NAND gates G1 and G2 and G7 and G8. The gate G15 detects pulses attributed to noises alone to be outputted to NAND gates G13 and G14. On the other hand, NOR gates H1 and H2 output pulses containing the direction of a motor rotation and speed information and the pulses attributed to the noises. When the motor rotates normally, the gate G14 is kept at the L level to generate no pulse. The gate G13 cancels the pulses attributed to the noise coinciding therewith in timing thereby outputting a pulse train alone owing to the pulses of phases A and B.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides an improved pulse train conversion circuit for a rotary encoder that is capable of removing pulse noise mixed in pulses output from a rotary encoder that provide information on the rotational speed and direction of a motor. It is related to.

0002

2. Description of the Related Art FIG. 4 is a block diagram showing an outline of a conventional motor control system. In the figure, 10 is a motor, and 11 outputs A-phase and B-phase pulses (AΦ, BΦ) that are 90 degrees out of phase from each other from a magnetic or optical position sensor according to the rotation of the motor 10. It is a rotary encoder. The A-phase and B-phase pulses output from the rotary encoder 11 are sent to the pulse train conversion circuit 1.
2 is converted into a pulse train, and this pulse train is supplied to the error detection circuit 13, and the error detection circuit 13 is supplied with a motor control signal via the function generator 14. In the error detection circuit 13, the signals from the rotary encoder 11 and the function generator 14 are processed, and the encoded control signal for the motor 10 is supplied from the error detection circuit 13 to the DA converter 15. An error voltage is obtained through the servo amplifier 16 and is amplified by the servo amplifier 16 to control the rotational speed and direction of the motor 10. Such motor control systems are often used in X-Y recorders, industrial robots, and the like, and are often used together with mechanical devices, so there is a high possibility that pulse noise will be mixed in.

0003

As shown in FIG. 4, the rotary encoder 11 outputs A-phase and B-phase pulses that differ in phase by 90 degrees from each other. The rotational speed and direction of the motor are detected, and the information and the control signal supplied via the function generator 14 are processed by the error detection circuit 13 to control the motor. Therefore, rotary encoder 1
If pulse noise is mixed into the A-phase and B-phase pulses from 1, the pulse train conversion circuit 12 will shape the pulse noise and mix it into the pulse train, which will change the rotation speed and direction of the motor. This means that the information contained incorrect information. In such a case, the error detection circuit 13 cannot perform normal information processing due to the incorporation of this pulsed noise, causing the motor 10 to malfunction, resulting in insufficient control.

[0004] An object of the present invention is to provide a rotary encoder 1
The present invention relates to a pulse train conversion circuit for a rotary encoder that can remove pulse noise mixed in A-phase and B-phase pulses output from a rotary encoder.

[0005]

[Means for Solving the Problems] A pulse train conversion circuit for a rotary encoder of the present invention converts first and second pulses, which are different in phase by 90 degrees from each other, from a rotary encoder and give information on the rotational speed and direction of a motor into a pulse train. a first flip-flop to which the first pulse is supplied and a second flip-flop to which the pulse from the first flip-flop is supplied;
a third flip-flop supplied with the second pulse; a fourth flip-flop supplied with the pulse from the third flip-flop; and a third flip-flop supplied with the pulse from the third flip-flop; - A first gate that obtains a pulse synchronized with a clock pulse with a pulse width between one edge of the output pulse of the flop and the second flip-flop, and the first flip-flop and the second flip-flop. - A second gate that obtains a pulse synchronized with a clock pulse with a pulse width between the other edges of the output pulse of the flop, and one of the output pulses of the third flip-flop and the fourth flip-flop. A third gate that obtains a pulse synchronized with a clock pulse, with a pulse width between the edges and the other edge of the output pulse of the third flip-flop and the fourth flip-flop, and a clock pulse. a fourth gate that obtains a pulse synchronized with the pulse; and one of the gates is configured to generate a pulse according to the rotational direction of the motor based on the outputs from the first to fourth gates and the pulses from the first and third flip-flops. first and second gate groups that obtain pulses that are prioritized and added in time series; and a noise detection circuit that configures a noise detection circuit that outputs only synchronized pulses among the pulses from the first to fourth gates. Pulses output from the third gate group, the first gate group, the third gate group, the second gate group, and the third gate group are supplied, and a pulse is provided to remove the synchronized pulses. 5 and a sixth gate.

[0006]

[Operation] The rotary encoder pulse train conversion circuit of the present invention has nine
Pulse noise mixed in the first and second pulses having a phase difference of 0 degrees is detected, and a pulse based on the pulse noise and a pulse based on the first and second pulses are supplied to a predetermined gate, and the gate Among the pulses supplied to the
Only information about the rotational speed and rotational direction of the motor is output as a pulse train.

[0007]

Embodiment FIG. 3 is a block diagram showing an example of a motor control system using the rotary encoder pulse train conversion circuit of the present invention. The pulse train conversion circuit of the rotary encoder according to the present invention is connected to the rear stage of the rotary encoder 11, and provides information on the rotation speed and rotation direction of the motor output from the rotary encoder 11. and B
The phase pulses (AΦ, BΦ) are supplied to a noise-removal type pulse train conversion circuit 12' that includes a noise detection circuit, and this pulse train conversion circuit 12' removes pulses based on pulse noise with matching timing. Only the pulse train giving information on the rotational speed and rotational direction of the motor is supplied to the error detection circuit 13. Furthermore, by supplying a control signal from the function generator 14 to the error detection circuit 13, the coded pulse signal is supplied from the error detection circuit 13 to the DA converter 15, and the error voltage obtained from the DA converter 15 is The rotation speed, rotation direction, etc. of the motor 10 are controlled by supplying the signal to a servo amplifier 16.

FIG. 1 is a circuit diagram showing an embodiment of a pulse train conversion circuit for a rotary encoder according to the present invention, and FIG.
The pulse train conversion circuit of the rotary encoder according to the present invention will be explained with reference to the timing chart of FIG. Figure 1
At this time, A-phase and B-phase pulses (AΦ, BΦ) are supplied from the rotary encoder to input terminals 2 and 3, respectively, as shown in FIGS. 2(2) and 2(7). Terminal 1 is shown in Figure 2.
A clock pulse is supplied as shown in (1),
A reset signal is supplied to the terminal 4. An A-phase pulse AΦ is input to the input terminal 2 . The pulse AΦ is passed through the inverter I1 to the D-flip-flop F1.
A pulse PF1 synchronized with the clock pulse is obtained from the D-flip-flop F1 as shown in FIG. 2(3). The output pulse PF1 is D-
The pulse PF2 is supplied to the flip-flop F2, and a pulse PF2 as shown in FIG. 2(4) is obtained. D-Flip
The inverted pulse of flop F1 and the pulse PF2 from D-flip-flop F2 are connected to NAND gate G1.
supplied to From NAND gate G1, pulse P
Pulses PA and P as shown in Figure 2 (5) with pulse widths corresponding to the rising edges of F1 and PF2.
A1 is obtained. Also, the pulse of D-flip-flop F1 and the pulse of D-flip-flop F2 are NA
The pulse width shown in FIG. 2 (
6) A pulse PB as shown in is obtained.

On the other hand, the pulse BΦ is supplied to the D-flip-flop F11 via the inverter I11, and as shown in FIG.
A pulse PF11 synchronized with the clock pulse as shown in (8) is obtained. The pulse is supplied to the D-flip-flop F12, and the pulse PF12 shown in FIG. 2(9) is obtained. D--inverted pulse of flip-flop F11 and D-
Pulse PF12 of flip-flop F12 is NAN
The pulses Pc and PC1 are supplied to the D gate G7 and have pulse widths corresponding to the rising edges of the pulses PF11 and PF12 as shown in FIG. 2(10). Also, the pulse of D-flip-flop F11 and D
- The inverted pulse of flip-flop F12 is NAN
The pulse PD is supplied to the D gate G8, and a pulse PD corresponding to the falling edges of the pulses PF11 and PF12 is obtained as shown in FIG. 2(11). Further, the D-flip-flops F1, F2, F11F12 are supplied with clock pulses from terminal 1 via inverter I5, and are supplied with a reset signal from terminal 4. In this way, NAND gates G1, G2
, G7, G8 are shown in FIGS. 2(5), (6), (10), and (11).

The NAND gate G3 receives the output from the NAND gate G1 and the output from the D-flip-flop F11 to form a priority circuit.
Supplied via. NAND gate G4 has
The output from NAND gate G2 and the output from D-flip-flop F11 are provided. NAND gate G5 has the output from NAND gate G7 and D-
The output from flip-flop F1 is provided. The output from the NAND gate G8 and the output from the D-flip-flop F1 are supplied to the NAND gate G6 via an inverter I2. Similarly, N.A.
The ND gates G9 to G12 are also supplied with outputs from output terminals A to D, etc. NAND gate G3 to G
6, G9 to G12 are D-flip-flops F1
, F11 and outputs from inverters I2 and I12 are supplied to form a priority circuit.

The outputs from NAND gates G3 to G6 are supplied to NOR gate H1, and the outputs from NAND gates G9 to G12 are supplied to NOR gate H2. These NAND gates G3 to G6 and N
FIG. 2 (13
) The pulses PL added in time series as shown in
PL1 to PL5 are obtained. Also, NAND gate G9
The output shown in FIG. 2 (14) is obtained by the gate group consisting of G12 to G12 and the NOR gate H2. Figure 2 shows
This is an example where the motor is rotating forward, and the NOR gate H2
The output from is maintained at L level. The outputs from NOR gates H1 and H2 are respectively connected to NAND gate G13.
, G14.

On the other hand, the output pulses from output terminals A to D are as follows:
They are supplied to NOR gates H3 and H4, respectively, and their respective outputs are supplied to NAND gate G15. The output of NAND gate G15 is shown in FIG. 2(12). A gate group consisting of NOR gates H3, H4 and NAND gate G15 is a noise detection circuit 7 that detects pulse noise. The output of NAND gate G15 is connected to inverter I7.
It is supplied to NAND gates G13 and G14 via. NAND gates G13 and G14 are inverter I7
The output from the noise detection circuit 7 and the respective outputs from the NOR gates H1 and H2 are supplied through the NAN
Pulses PP1 to PP5 are obtained from the output of the D gate G13 as shown in FIG. 2(15). NAND gate G1
The respective outputs obtained from 3 and G14 are supplied to waveform shaping circuits 8 and 9 consisting of D-flip-flops F3 and F4 and F13 and F14, and inverters I3 and I
13, a pulse train is obtained from any terminal corresponding to the rotational direction of the motor. In FIG. 2, since the motor is rotating in the normal direction, a pulse train for controlling the motor is obtained from the terminal 5. The D-flip-flops F1 to F4 and F11 to F14 are supplied with clock pulses so that their output pulses are synchronized with the clock pulses, and are also provided with reset terminals.

Next, a case where pulse noise is mixed into the A-phase and B-phase pulses (AΦ, BΦ) output from the rotary encoder will be explained. The pulses P1 and P2 shown in FIGS. 2(2) and 2(7) are pulse noise mixed into the rotary encoder pulses (AΦ, BΦ) at the same timing. The output of the D-flip-flop F1 is inverted from H level to L level, a pulse P3 synchronized with the clock pulse is obtained, and a pulse P4 is obtained from the D-flip-flop F2. Also, due to the mixing of pulse noise P2, the D-flip-flop F
The output of F11 is inverted from L level to H level to obtain pulse P7, and pulse P8 is obtained from D-flip-flop F12. These pulses are supplied to NAND gates G1, G2, G7, and G8, and from their output terminals A to D, (5), (6), (10), and (11) in FIG.
The pulses P5, P6, P9, P10 as shown in
is obtained.

The NOR gate H3 is supplied with a pulse P5 that inverts from L level to H level and a pulse P6 that inverts from H level to L level from NAND gates G1 and G2, and the NOR gate H4 is supplied with a pulse P5 that inverts from L level to H level and a pulse P6 that inverts from H level to L level, respectively. , from NAND gates G7 and G8, from H level to L level.
A pulse P9 that inverts from L level to H level and a pulse P10 that inverts from L level to H level are supplied, and their outputs are N.
It is supplied to AND gate G15. NAND gate G1
5, a pulse P11 of H level is output as shown in FIG. 2 (12). The output pulse from the output terminal K of the NAND gate G15 is inverted via the inverter I7 and the pulse is supplied to the NAND gates G13 and G14. On the other hand, from the output terminals L and M of the NOR gates H1 and H2, a pulse P containing information on the rotational direction and rotational speed of the motor is output as shown in Fig. 2 (13) and (14).
A, PA1, PB, PB1 and PC, PC1, PD
, PD1 and pulses P5 and P6 due to pulse noise.
Alternatively, pulse P12 based on P9 and P10 is output.

The timing chart in FIG. 2 is an example in which the motor rotates in the forward direction, so a pulse is obtained from the output terminal L of the NOR gate H1, whereas an L level is obtained from the output terminal M of the NOR gate H2. It remains held and no pulse is obtained. Therefore, NAND gate G1
3 is supplied with a pulse P11 from the noise detection circuit 7 via an inverter I7, and also supplied with pulses PL to PL4 caused by the rotation of the motor and a pulse P12 caused by pulse noise. NAND gate G13
From then on, the pulses caused by the pulse noise having the same timing as shown in FIG. 2(15) are canceled out, and only the pulses PP1 to PP5 corresponding to the pulses PL, PL1 to PL5 are output. Pulses PP1 to PP5 from the NAND gate G13 are supplied to a waveform shaping circuit 7 consisting of D-flip-flops F3 and F4, where the waveforms are shaped, and a pulse train is obtained from the output terminal 5. on the other hand,
The NAND gate G14 is supplied with an L level output and a pulse P12 due to pulse noise, but the output is maintained at the L level.

Of course, when the rotation direction of the motor is opposite to that shown in FIG. 2, the B-phase pulse leads the A-phase pulse, the terminal L is held at L level, and A pulse train containing information on the rotational direction and rotational speed of the motor is output from the output terminal 6.

In the embodiment shown in FIG. 1, the NAND gate,
Although the NOR gate and the inverter are described using two types of symbols, positive logic and negative logic, it is clear that the structure can be configured in either case. Also, NAN
The D gate can also be replaced with a NOR gate, and is not limited to the circuit of the embodiment. The logic circuit may be constructed so that the matching pulses of the two cancel each other out.

[0018]

[Effects of the Invention] The pulse train conversion circuit for a rotary encoder of the present invention detects the pulse-like noise in the noise detection circuit even if pulse-like noise is mixed into the pulses AΦ and BΦ containing information about the rotational speed and direction of the motor. detect,
By removing the pulses whose timing coincides with the pulses caused by the noise from the pulse train, the pulses AΦ, B
Pulse noise mixed in Φ can be removed very easily. Therefore, by using the rotary encoder pulse train conversion circuit of the present invention in a motor control system, it is possible to easily eliminate malfunctions in the motor control system, and it is extremely effective in improving the reliability of the motor control system. It is.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pulse train conversion circuit for a rotary encoder according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the pulse train conversion circuit of the rotary encoder according to the present invention.

FIG. 3 is a block diagram showing one part of a motor control system in which the rotary encoder pulse train conversion circuit according to the present invention is used.

FIG. 4 is a block diagram showing an example of a conventional motor control system.

[Explanation of symbols]

1 to 4 terminals 5, 6 output terminal 7 noise detection circuits 8, 9 waveform shaping circuit 12' pulse train conversion circuits F1 to F4, F11 to F14 D-flip
Flops I1 to I3, I11 to I13 Inverters G1 to G15 NAND gates H1 to H4 NOR gates

Claims (1)

[Claims] 1. A pulse train conversion circuit to which first and second pulses having a phase difference of 90 degrees from each other giving information on the rotational speed and direction of the motor are supplied from a rotary encoder, to which the first pulses are supplied. a first flip-flop, a second flip-flop supplied with a pulse from the first flip-flop, a third flip-flop supplied with the second pulse; A fourth flip-flop to which the pulse from the flip-flop is supplied, and a pulse width between one edge of each output pulse of the first flip-flop and the second flip-flop, and a clock The pulse width is between a first gate that obtains a pulse synchronized with the pulse and the other edge of each output pulse of the first flip-flop and the second flip-flop, and the pulse is synchronized with the clock pulse. the second gate to obtain and the third flip gate;
a third gate that obtains a pulse synchronized with a clock pulse with a pulse width between one edge of each of the output pulses of the flop and the fourth flip-flop; A fourth gate whose pulse width is between the other edges of each output pulse of the flip-flop and obtains a pulse synchronized with a clock pulse, and the output pulses from the first to fourth gates are supplied to the fourth gate. 1 and the third flip-flop, one of which is prioritized according to the rotational direction of the motor to obtain pulses added in time series; - a third gate group constituting a noise detection circuit that detects only mutually synchronized pulses mixed in the output from the fourth gate, the first gate group, the third gate group, and the second gate group; and fifth and sixth gates to which the output from the third gate group is supplied, respectively, and information on the rotation speed and rotation direction of the motor is provided through the fifth and sixth gates. A pulse train conversion circuit for a rotary encoder, characterized in that it outputs a pulse train that gives .