JPH04324716A - frequency synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a phase locked loop (PLL) which has a function of arbitrarily variably setting the output frequency and can speed up frequency switching time.
This invention relates to an improvement of a frequency synthesizer using an ed Loop configuration.

0002

2. Description of the Related Art Conventionally, a voltage controlled oscillator (VCO) is used as a frequency synthesizer using a phase-locked loop (PLL) configuration that allows the output frequency to be arbitrarily set variably.
Voltage Controlled Oscill
A feedback signal obtained by frequency-dividing the output of ator) using a variable frequency divider and a reference signal with a constant frequency are input to a phase comparator, and the output of the phase comparator is passed through a loop filter to VC.
A configuration in which the light returns to O is widely used. FIG. 7 is a diagram showing an example of such a conventional configuration. In the figure, 201 is a VC
O, 202 is a frequency divider, 203 is a reference oscillator (OSC),
204 is a phase comparator, and 205 is a loop filter.

0003

However, in the conventional configuration described above, the phase comparator 204 is generally configured to perform multiplication processing by the reference signal and the feedback signal, and the low frequency output of the phase comparator 204 is Since the components include phase error information, a loop filter 205 is essential to sufficiently suppress and remove unnecessary harmonics. However, the frequency switching time of the frequency synthesizer depends on the time constant of the loop filter 205, and in order to ensure that the S/N (signal-to-noise power ratio) of the frequency synthesizer output is above a certain value, the loop filter 205 is It is necessary to set a large time constant.

As described above, in the conventional configuration, improving the S/N by removing unnecessary harmonics and speeding up the frequency switching time are contradictory to each other, so it is impossible to satisfy both at the same time. The problem arises that it cannot be done. In order to remedy this problem, in the configuration shown in FIG. 7, the time constant of the loop filter 205 is changed from a small value (high-speed pull-in) to a large value (high S/N) for the pull-in operation during frequency switching and the steady operation after the pull-in. A method has also been devised to switch to However, in this method, the output value of the phase comparator 204 fluctuates due to frequency fluctuations caused by fluctuations in the input voltage of the VCO 201 that occur when the loop filter 205 is switched, resulting in a long-time transient response. Therefore, additional countermeasures such as suppressing fluctuations in the output of the loop filter at the time of frequency switching and temporarily storing the output value of the phase comparator are required, resulting in a problem that the circuit scale increases. SUMMARY OF THE INVENTION An object of the present invention is to avoid the problem of the contradictory relationship between speeding up the frequency switching time and increasing the S/N ratio in the conventional configuration, and to provide a frequency synthesizer that is suitable for miniaturization and integration into an IC.

[0005]

[Means for Solving the Problems] The frequency synthesizer of the present invention has a phase-locked loop configuration and includes a voltage-controlled oscillator whose output frequency can be arbitrarily set in accordance with a control voltage. , the reference clock from the reference oscillator is input to one side, and the output of the reference clock is output during closed-loop operation, and the output of the reference clock is stopped during open-loop operation, according to an open-loop/closed-loop switching signal applied to the other input terminal. an AND gate circuit, a counter that divides the frequency of the reference clock and generates and outputs a reference phase signal ψ, and divides the output frequency of the voltage controlled oscillator by 1/P (P≧1) and outputs the divided clock. A fixed frequency divider that takes the frequency divided clock as one input, and outputs the frequency divided clock during closed loop operation according to the open loop/closed loop switching signal given to the other input terminal, and outputs the frequency divided clock during open loop operation. a second AND gate circuit that stops the output of the second A;
2π of the phase integration output obtained by integrating the predetermined phase increase step value according to the timing of the output clock of the ND gate circuit
A numerically controlled oscillator outputs a value modulo radian as a feedback phase signal φ, and the reference phase signal ψ and the feedback phase signal φ are expressed by the formula ε=[{(ψ−φ)+3π}mod2π]
-π (however, {・}mod2π is the remainder when divided by 2π radians), and the output range is (-π to π)
a phase comparator circuit that outputs a phase error signal ε in radians;
an averaging circuit that averages the phase error signal ε and outputs the phase error average value 1 outside the average value in a predetermined time period after the start of the open loop operation according to the open loop/closed loop switching signal; A switch that inputs the average value outside the average value 1 and outputs the phase error signal ε during closed loop operation and outputs the phase error outside the average value 1 during the open loop operation according to the open loop/closed loop switching signal; A D/A converter that converts the output into an analog value, and a low-pass filter that provides an output obtained by removing quantization noise components contained in the output of the D/A converter as the control voltage of the voltage controlled oscillator. It is characterized by:

[0006]

Embodiment [Configuration] FIG. 1 is a diagram showing an example of the configuration of a first embodiment of the present invention. In the figure, reference oscillator 1 outputs a reference clock. 2 is an AND gate circuit, which takes the reference clock as one input and outputs the reference clock during closed loop operation and outputs the reference clock during open loop operation according to the open loop/closed loop switching signal supplied to the other input terminal. stop. 3 is a counter, which divides the frequency of the reference clock from the AND gate circuit 2 to generate and output a reference phase signal ψ.

4 is a voltage controlled oscillator (VCO: Volta
ge Controlled Oscillator)
and outputs an oscillation frequency f0 according to an externally applied control voltage. 5 is a fixed frequency divider, and the VC
The output frequency f0 of O4 is fixedly divided to 1/P (P≧1), and fCLK (=f0/P) is output. 6 is an AND gate circuit similar to 2, which takes fCLK which is the output of the fixed frequency divider 5 as one input, and uses the open loop/closed loop switching signal given to the other input terminal to switch fCLK during closed loop operation. fCLK output, and stops fCLK output during open-loop operation.

7 is a numerically controlled oscillator (NCO).
ical Controlled Oscillato
r), and the phase increase step value (digital value) Δφ set externally according to the timing of the output fCLK of the AND gate circuit 6 is integrated, and the feedback phase signal φ(0
≦φ≦2π, φ is a digital value). This NC
O7 can be easily configured with an adder and a register.

8 is a phase comparator circuit, and the counter 3
An addition operation is performed using the reference phase signal ψ from the NCO 7 as one input (addition value) and the feedback phase signal φ from the NCO 7 as the other input (subtraction value), and the phase error is calculated according to the following equation (1). A signal ε (−π≦ε≦π) is output.

[Equation 1] ε=[{(ψ−φ)+3π}mod2π]−π
……………(1) (However, {・}mo
(d2π is the remainder when divided by 2π radians) This phase comparator circuit 8 can be easily constructed using an adder.

Reference numeral 9 denotes an averaging circuit, which averages the phase error signal ε from the phase comparator circuit 8 in accordance with the open loop/closed loop switching signal, and detects a phase error outside the average value in a predetermined time period after the start of the open loop operation. Outputs 1. This averaging circuit 9
can be easily configured with adders and registers.

FIG. 3 is a diagram showing an example of the structure of the above-mentioned averaging circuit 8. In the figure, reference numeral 101 denotes an adder that performs an addition operation using a phase error signal ε as one input and a value fed back from a register 102 (described later) as the other input, and outputs the result. 102 is a register that temporarily stores the output of the adder 101 and outputs it according to timing supplied from the outside. The output of register 102 is fed back to adder 101. With the above configuration, ε by the adder 101
The number of times of integration is 2m times, and the value obtained by dropping m bits from the obtained integrated value, that is, the value multiplied by 2-m, is set as 1 outside the average value (phase error average output). Average behavior can be obtained.

Returning to FIG. 1 again, 10 is a switch;
The phase error signal ε from the phase comparison circuit 8 and the phase error average value outside 1 from the averaging circuit 9 are input, and according to the open loop/closed loop switching signal, the phase error signal ε is output during closed loop operation, and the phase error signal ε is output when the loop is open. During loop operation, a value of 1 outside the average phase error value is output. 11 is a D/A converter, which converts the output digital value of the switch 10 into an analog value. A low pass filter (LPF) 12 removes quantization noise components contained in the output of the D/A converter 11 and inputs the control voltage to the VCO 4.

Next, FIG. 2 is a diagram showing a configuration example of a second embodiment of the present invention. All the components in the configuration example of FIG. 2 are exactly the same as components 1 to 12 of FIG.
The only difference from the first embodiment shown in FIG. 1 is that the inputs of AND gate circuits 2 and 6 are connected to the outputs of fixed frequency divider 5 and reference oscillator 1, respectively.

[Operation] The operation of the first embodiment of the present invention shown in FIGS. 1 and 3 will be explained below with reference to FIGS. 4, 5, and 6. FIGS. 4A, 4B, and 4C are time charts showing operation examples of the feedback phase signal φ, reference phase signal ψ, and phase error signal ε during closed loop operation. First, the effect of synchronous pull-in during closed loop operation will be explained with reference to FIG. Now, at time 0, the output of NCO7 is φ=0
shall be. Thereafter, NCO7 is the output signal fCL of fixed frequency divider 5.
The phase increase step value Δφ continues to be integrated every cycle of K (1/fCLK), and the output of the NCO 7 due to the integration increases stepwise in steps of Δφ, as shown in FIG. 4(A). Next, at time t1, when the value of φ reaches 2π or more, it exceeds the 2π value and changes from the provisional integrated value shown by the broken line to 2
The value decreases to the value obtained by subtracting π, and then increases again in steps of Δφ. After time t1, the same operation as after time 0 is repeated to obtain a feedback phase signal φ having a sawtooth waveform. on the other hand,
Since the reference phase signal ψ is given as a numerical value obtained by integrating the output of the reference oscillator 1 with the counter 3, it is shown in FIG.
), it becomes a sawtooth waveform similar to φ.

Now, consider the case where the feedback phase signal φ is in a leading phase with respect to the reference phase signal φ, as shown in FIG. At this time, the simple numerical difference (ψ-φ) between the reference phase signal ψ and the feedback phase signal φ shown by the broken line in FIG. A phase jump occurs. This phase jump is corrected by calculation based on equation (1), and a phase error signal ε as shown by the solid line in FIG. 4(C) is obtained.

From the above, in the configuration according to the present invention, in synchronous pull-in by closed loop operation, the reference phase signal ψ
and the feedback phase signal φ are direct phase information, and the true phase error can be obtained in the phase error signal ε.Theoretically, the phase error signal ε does not contain harmonic components, which is necessary for the conventional configuration. It can be seen that the loop filter for suppressing harmonic components is essentially unnecessary. Therefore, the time constant of the loop filter, which was a factor in increasing the frequency switching time in the conventional configuration, can be set to a small value in the present invention, thereby enabling high-speed frequency switching. The phase error signal ε is converted into an analog value by the D/A converter 11, and after the quantization noise component is removed by the LPF 12, it is fed back as a control voltage input to the VCO 4. The desired output frequency f0 is determined by the configuration of this negative feedback loop.
can be obtained.

Here, the relationship between the output frequency f0 and the phase increase step value Δφ of the NCO 7 will be derived. first,
When the reference clock input to the counter 3 is fc and the frequency division number of the counter 3 is N, the period Tc in FIG. 4(B) is expressed by the following equation (2).

##EQU00002## Also, the period TNCO of the NCO 7 is given by the following equation (3).

[Equation 3] Period Tc of the reference phase signal and period T of the feedback phase signal
Since NCO is Tc=TNCO in the phase synchronization state, the following equation (4) is obtained from equations (2) and (3).

[Equation 4] Furthermore, the output clock fCLK of the fixed frequency divider 5 is as follows (
5) It is shown by the formula.

[Equation 5] Therefore, from equations (4) and (5), the output frequency f0
can be expressed by the following equation (6).

[Formula 6] From equation (6), it can be seen that if P, N, and fc are constant, the output frequency f0 can be uniquely determined in a relationship that is inversely proportional to Δφ.

Next, FIG. 5 is a flowchart of frequency switching operation in the configuration of the present invention. In the figure, after the start of operation (START), first in step 1 (6)
The output frequency is set by setting Δφ based on the relationship in the equation, and the closed loop operation of step 2 is entered. After locking in synchronization in step 3 through the closed loop operation, the process enters step 4, where the averaging circuit 9 averages the phase error signal ε, and when the average value 1 is obtained, the average value 1 is obtained.
Open-loop operation is entered with a control voltage that is the holding value.

The above series of operations will be further explained using FIG. 6. FIG. 6 is a time chart of the frequency switching operation based on the flowchart shown in FIG. The upper part of the figure is V
CO4 output frequency, middle stage is AND gate circuit 2 and 6
, the open loop input to the averaging circuit 9 and the switching device 10/
The closed loop switching signal, the bottom row is the integrated output of the averaging circuit 9,
are shown respectively. In the figure, the output frequency is f1
Consider the case of switching from f2 to f2. At this time, in the process from step 1 to step 3 in FIG.
The output frequency of changes from f1 to f2 due to closed-loop operation. Next, from the time when the synchronization pull-in is completed, the output of the averaging circuit 9 is first reset in step 4, and the averaging (integration) process is immediately started. In step 5, the operation is switched to open loop operation, and the averaging circuit output 1 is supplied to the D/A converter 11 and LPF 12. Outside 1
Since it remains constant during open-loop operation, a stable output frequency can be obtained. During open loop operation, the AND gate circuits 2 and 6 stop the reference clock and the output fCLK of the fixed frequency divider 5 to be supplied to the counter 3 and NCO 7, respectively, thereby generating the reference phase signal ψ and the feedback phase signal φ. is maintained to prevent phase slip of ψ and φ. This results in a phase error signal ε at the start of the next closed-loop operation.
is held at the final value of the previous closed-loop operation, allowing high-speed synchronization pull-in by the next channel switch.

Next, the operation of the present invention based on the second embodiment shown in FIG. 2 will be described. In FIG. 2, the reference phase signal ψ is obtained by the NCO 7, and the feedback phase signal φ is obtained by the counter 3, contrary to the first embodiment shown in FIG. Therefore, since fc and fCLK in equations (2), (3), and (4) derived in the configuration of FIG. 1 are exchanged with each other, the following equations are obtained.

[Formula 7] On the other hand, the above-mentioned equation (5) also holds true in the configuration of FIG. It can be expressed by the following equation corresponding to Eq.

[Formula 8] From the above equation (6)', if P, N, and fc are constant, the output frequency f0 was inversely proportional to Δφ in the configuration of FIG. 1 according to equation (6), whereas, It can be seen that in the configuration of FIG. 2, the relationship can be uniquely determined in proportion to Δψ.

[0021]

[Effects of the Invention] As explained in detail above, in the configuration of the frequency synthesizer of the present invention, the extraction of the feedback phase signal or the generation of the reference phase signal is realized directly by using the NCO. Direct phase comparison becomes possible through signal processing. Therefore, harmonic components that occur in the conventional configuration are not generated, and the time constant of the loop filter can be set to a small value, so that the frequency pull-in time during closed loop operation can be accelerated. Further, after the frequency is pulled in by the closed-loop operation, a signal with high frequency stability can be obtained by averaging the phase error components using an averaging circuit, and performing the open-loop operation while holding the average value. Furthermore, since most of the circuits are digital signal processing, there are advantages such as miniaturization of the circuits and suitability for integration into ICs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

[Figure 2
]Block diagram showing a second embodiment of the present invention

[Figure 3] Figure 1
and a block diagram showing an example of the configuration of the averaging circuit in FIG.

[Figure 4] Time chart of feedback phase signal, reference phase signal, and phase error signal

[Figure 5] Flowchart of frequency switching operation

[Figure 6] Time chart of frequency switching

[Figure 7] Block diagram of a frequency synthesizer with a conventional PLL configuration

[Explanation of symbols]

1 Reference oscillator 2 AND gate circuit 3 Counter 4 VCO 5 Fixed frequency divider 6 AND gate circuit 7 NCO 8 Phase comparison circuit 9 Averaging circuit 10 Switcher 11 D/A converter 12 LPF 101 Adder 102 Register 201 VCO 202 Frequency divider 203 Reference oscillator 204 Phase comparator 205 Loop filter

Claims (2)

[Claims] Claim 1. A frequency synthesizer having a phase-locked loop configuration, which includes a voltage-controlled oscillator whose output frequency can be arbitrarily set in accordance with a control voltage. a first AND gate circuit that outputs the reference clock during closed loop operation and stops outputting the reference clock during open loop operation according to an open loop/closed loop switching signal applied to the other input terminal; a counter that generates and outputs a reference phase signal ψ, a fixed frequency divider that divides the output frequency of the voltage controlled oscillator by 1/P (P≧1) and outputs a divided clock, and the divided clock. a second AND gate circuit which takes as one input and outputs the frequency-divided clock during closed-loop operation and stops outputting the frequency-divided clock during open-loop operation according to the open-loop/closed-loop switching signal applied to the other input terminal. a numerically controlled oscillator that outputs, as a feedback phase signal φ, a value modulo 2π radian of a phase integrated output obtained by integrating a predetermined phase increase step value according to the timing of the output clock of the second AND gate circuit; The phase signal ψ and the feedback phase signal φ are expressed by the formula ε=[{(ψ−φ)+3π}mo
d2π]-π (where {・}mod2π is the remainder when divided by 2π radians), and the output range is (-
a phase comparison circuit that outputs a phase error signal ε of π to π) radians; An averaging circuit that outputs in a time period, the phase error signal ε and the phase error average value outside 1 are input, and the open loop/closed loop switching signal causes a phase error signal ε to be output during closed loop operation, and a phase error signal ε during open loop operation. A switch that switches and outputs 1 outside the average value, a D/A converter that converts the output of the switch to an analog value, and an output that removes quantization noise components contained in the output of the D/A converter. A frequency synthesizer comprising: a low-pass filter that provides the control voltage of the voltage controlled oscillator. [Outside 1] 2. The first AND gate circuit according to claim 1, which receives the divided clock from the fixed frequency divider as one input and outputs a feedback phase signal φ from the counter; 2. The frequency synthesizer according to claim 1, wherein the reference clock from the reference oscillator is given as one input of the AND gate circuit, and the reference phase signal ψ is output from the numerically controlled oscillator.