JPH04324775A - Picture memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device.

0002

2. Description of the Related Art In an image signal processing circuit for a video signal, a digital video signal obtained by digitizing an analog video signal is usually written as is for one screen or multiple screens into an image memory, and predetermined processing is performed on the digital video signal. Ta. The address of the image memory was controlled by the timing of the synchronization signal of the image signal to be written.

0003

[Problems to be Solved by the Invention] In the conventional example, the address control of the image memory was defined by the synchronization timing of the image signal, so there was a considerable amount of unused portions as shown by diagonal lines in FIG. It had become. This unused portion becomes quite large depending on the number of horizontal pixels and horizontal lines.

An object of the present invention is to provide an image memory device that saves such unused memory.

[0005]

[Means for Solving the Problems] An image memory device according to the present invention provides a buffer memory between a memory means and an input/output means, and transfers data between the memory means and each buffer memory, and The present invention is characterized in that data transfer between the buffer memory and the input/output means is controlled at different timings.

[0006]

[Operation] With the above means, address control of the memory means can be performed at a unique timing independent of the input image or the output image. This reduces the unused portion of the memory means.

[0007]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. 10 is an input terminal for an image signal (moving image or still image) from a video camera or video playback device, 12 is an input circuit consisting of an A/D converter that digitizes the image signal from the input terminal 10, and 14 is an input terminal. FIFO (first in, first out) that asynchronously supplies the output of circuit 12 to bus 16
Memory (buffer buffer), 18 image memory, 20
is an address generation circuit that generates an address for the image memory 18. Bus 16 consists of a data bus, a plurality of control signal lines, and a clock line.

22 and 24 are FIFO memories that supply image data read from the image memory 18 and input via the bus 16 to output circuits 26 and 28, respectively. The output circuits 26 and 28 are composed of, for example, D/A converters. 30,
32 is an output terminal connected to a monitor or a video recording device.

34, 36, 38 are input/output circuits 12, 26
, 287 and the FIFO memories 14, 22, 24, and the FIFO memories 14, 287 via the bus 16.
a pulse generation circuit 40 that generates clocks and control signals necessary for data transfer between 22, 24 and the image memory 18;
, 42, 44 are input/output circuits 12, 44 for each predetermined amount of data.
Trigger generation circuit 46, 4 that generates a data transfer request between 26, 287 and the FIFO memory 14, 22, 24;
8 and 50 are trigger counters that count the number of triggers generated by the trigger generation circuits 40, 42, and 44.

52 arbitrates data transfer requests in each input/output circuit 12, 26, 28, and connects the image memory 18 and FIF
A memory control circuit 54 controls data transfer between the O-memories 14, 22, and 24, and a control device 54 inputs instructions for the overall operation mode.

The operation of this embodiment will be explained by taking as an example the case where an image signal input to the input terminal 10 is stored in the image memory 18.

The user instructs the memory control circuit 52 to store the input image data in the image memory 18 from the operating device 54 . The memory control circuit 52 controls writing of the output of the input circuit 12 to the FIFO memory 14 using the pulse generation circuit 34.
The pulse generation circuit 34 outputs a command to the FIFO memory 14.
A write control signal is generated in synchronization with the synchronization signal of the image signal input from the input terminal 10. Further, the trigger generation circuit 40 generates a message every time a predetermined amount (hereinafter referred to as a memory unit) of image data is written to the FIFO memory 14.
A trigger signal is sent to trigger counter 46 and memory control circuit 52. Trigger counter 46 counts this trigger signal and provides the count to memory control circuit 52.

The memory control circuit 52 is connected to the trigger generation circuit 40.
In response to a trigger signal from the trigger counter 46, the trigger count number from the trigger counter 46 is outputted to the address generation circuit 20, and simultaneously transferred from the FIFO memory 14 to the image memory 18 via the bus 16. Address generation circuit 20
generates an address for each memory unit of data, thereby writing the image data from the FIFO memory 14 into the image memory 18.

By doing this, the image memory 1
In No. 8, the image data is densely written, and the unused portion is only the portion corresponding to the diagonal line in FIG. 3, which can be extremely reduced.

Reading of image data from the image memory 18 to the output circuits 26 and 28 is similarly executed by generating a data transfer request trigger signal for each memory unit. However, the image memory 18 and the FIFO memory 22,2
Since data transfer to and from FIFO memory 4 can only be performed with one FIFO memory at a time, memory control circuit 52 arbitrates between each transfer request to prevent transfer requests from colliding.

[0017]

As can be easily understood from the above description, according to the present invention, it is possible to provide an image memory device with a small amount of unused portions and high utilization efficiency.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of memory usage in a conventional example.

FIG. 3 is an explanatory diagram of memory usage according to the present embodiment.

[Explanation of symbols]

10: Image signal input terminal 12: Input circuit 14:
FIFO memory 16: Bus 18: Image memory 2
0: Address generation circuit 22, 24: FIFO memory 26, 28: Output circuit 30, 32: Output terminal 3
4, 36, 38: Pulse generation circuit 40, 42, 44: Trigger generation circuit 46, 48, 50: Trigger counter 52: Memory control circuit 54: Operating device

Claims (1)

[Claims] Claim 1: A buffer memory is provided between the memory means and the input/output means, and data transfer between the memory means and each buffer memory and data transfer between the buffer memory and the input/output means is provided. An image memory device characterized in that data transfer is controlled at different timings.