JPH04324830A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To relieve a liquid crystal display device as acceptacle product even though pinholes are formed in an insulating layer over the gate. CONSTITUTION:An insulative layer 8 is divided into two layers, which are produced by different processes, so that generation of pinholes 10 is decreased or nullified completely. Even though pinhole 10 is yet produced, any part of eventually attached Cr film 14 or electrodes 11, 12 coveringly is precluded from contacting a gate 3 in layer 8 mating with the pinhole 10 through the action of a pinhole 16 which is greater than the pinhole 10 and provided in the gate 3 and with which the surface of glass base board 2 is exposed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a liquid crystal display device.
In particular, the present invention relates to a structure that prevents a decrease in yield due to pinholes in an interlayer insulating layer.

0002

2. Description of the Related Art In general, development and mass production of liquid crystal display devices are actively progressing, mainly for color TVs. "Flat Panel Display 1991" published by Nikkei BP provides a detailed explanation of these technological trends.
There is. This document discloses liquid crystal display devices with various structures, but here we will discuss active display devices using TFTs.
A matrix liquid crystal display device will be explained below.

This active matrix liquid crystal display device has a configuration as shown in FIG. 2, for example. First, there is a transparent insulating substrate, for example a glass substrate (51). On this glass substrate (51), a gate (52) and an auxiliary capacitance electrode (53), which are components of a TFT, are mounted, for example, using Mo-
It is made of Ta alloy or the like. Furthermore, SiNx is applied to the entire surface.
A film (54) consisting of is laminated. Subsequently, an amorphous silicon film (55) and an N+ type amorphous silicon film (56) are laminated on the SiNx film (54) corresponding to the gate (52), and these two layers of amorphous silicon film ( A semiconductor protective film (57) is provided between 55) and (56). Subsequently, on the N+ type amorphous silicon film (56), a source electrode (58) and a drain electrode (59) are provided, respectively, as a laminate of, for example, Mo and Al. Furthermore, the SiNx film (54) corresponding to the auxiliary capacitance electrode (53)
A display electrode (60) made of ITO, for example, is provided on top and is electrically connected to the source electrode (58).

On the other hand, although not shown, a glass substrate is provided opposite the glass substrate (51), and a counter electrode is provided on this glass substrate. Furthermore, liquid crystal is injected between the pair of glass substrates to form a liquid crystal display device.

[0005]

[Problem to be solved by the invention] In the above configuration,
There was a problem in that a pinhole was generated in the SiNx film (54), and the display electrode (60) came into contact with the auxiliary capacitor electrode (53) through the pinhole. In recent years, liquid crystal display devices have 300,000 to 1,000,000 pixels, and the number of pixels tends to increase more and more. However, under such circumstances, even one point defect is not acceptable, and even if only one pinhole occurs, it becomes a major factor in reducing the yield.

[0006]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned problems, and includes at least a layer (15) that is in contact with the source electrode (11) and drain electrode (12) of the TFT (1) in the lower layer. By providing a pinhole (16) larger in size than the pinhole (10) in the gate (3) corresponding to the pinhole (10) that extends to the surface of the gate (3) of the TFT (1). It is something to be solved.

Furthermore, the gate (3) of the TFT (1)
and the amorphous silicon active layer (1) of the TFT (1).
This problem can be solved by making the insulating layer (8) formed between the two layers (3) and (8) have a two-layer structure and forming them in different steps.

[0008]

[Operation] The pinhole (10) is connected to the source electrode (11).
) and the lower layer of the drain electrode (12), that is, the amorphous silicon layer (13), to the surface of the gate (3).
If a pinhole (16) larger than 10) is provided, even if the electrode material is deposited, this electrode will only come into contact with the glass substrate (2) underlying the gate (3).
electrically separated from the

On the other hand, if the insulating layer (8) has a two-layer structure and is formed in different steps, pinholes generated in the first insulating layer can be filled with the second insulating layer. However, in reality, it is impossible to completely fill the pinholes (10), and the pinholes (10) that cannot be filled grow directly to the amorphous silicon contact layer (13), just like crystal growth. Yes. However, since a large pinhole (16) is provided in the gate (3), the electrode and the gate (3) are electrically isolated.

0010

[Example] The present invention will be explained below. First, the configuration will be explained in detail with reference to FIG. Here, FIG. 1 is divided into three parts for convenience of drawing, and the leftmost one is TFT (1).
The center part shows the configuration of the drain terminal formed in the right and left terminal areas of the substrate, and the rightmost part shows the configuration of the gate terminal formed in the upper and/or lower terminal areas of the substrate. This shows the configuration.

First, there is a transparent insulating substrate (2). Here, this substrate (2) is, for example, a glass substrate. On this glass substrate (2), 500 Å of Cr and 1500 Å of Cu containing 1% Fe are laminated, and a gate (3) and an auxiliary capacitor electrode (4) are provided. Also gate (3
), a gate line (6) is provided that extends to the gate terminal (5) of the substrate (2), and is electrically connected to the surface of the gate terminal (5). Further, a drain terminal (7) and a gate terminal (5) are provided around the substrate (2), and are made of ITO here.

Subsequently, a silicon nitride film SiNx (8) is provided over the entire surface by plasma CVD. Here, the SiNx film (8) is configured to be able to establish contact with the drain line (9) without covering one surface of the drain terminal (7). In addition, at the gate terminal (5), when etching the pinhole (10) described later, the gate line (6) is removed so that the gate line is not etched.
It also covers the contact area.

In the above description, the SiNx film (8) and the gate (3) have one configuration that is the key point of the present invention. In general, efforts are made to eliminate pinholes and the like in production lines in order to improve yield. However, it is extremely difficult to eliminate pinholes and dust adhesion, even if the cleanliness within the factory is improved.

For example, when it is assumed that the SiNx film (8) is formed by CVD, this step includes insertion of a glass substrate, evacuation, heating, movement, gas adjustment, film formation, movement, cooling, air release, and glass The process involves taking out the board and going through a number of steps. Therefore, if there is a problem in even one of these steps, pinholes are likely to occur. This pinhole (10) is
If it occurs on the gate (3), gate line (6), or auxiliary capacitor electrode (4), it will short-circuit with the conductor formed in the upper layer.

For example, the pinhole (1) on the gate (3)
0), as shown in Figure 2, as if a crystal seed grows.
It may grow to the lower layer of the source electrode (11) and drain electrode (12), that is, to the amorphous silicon contact layer (13). Therefore, the deposition process of the source electrode (11) and drain electrode (12) material and the
, (12), a short circuit occurs during the deposition process of Cr (14) formed under the layers.

[0016] Therefore, first of all, in the present application, the SiNx film (8)
is formed in two steps. The first layer is a SiNx film with a thickness of about 2000 Å, followed by a second SiNx film with a thickness of about 2000 Å.
It is provided with a thickness of 000 Å. Here, the first layer and the second layer
Although both layers are formed of a silicon ticker film, the first layer may be a SiO2 film. Here, the film is formed by LP-CVD. Since the SiO2 film is similar in composition and other properties to the glass substrate, it is possible to prevent defects from occurring. Further, both may be formed of a SiO2 film.

[0017] As a result, a part of the pinhole generated in the first layer SiNx film can be filled with the second layer SiNx film. If pinholes can be completely eliminated, the above-mentioned two-layer structure can eliminate the short circuit phenomenon. However, some of these pinholes may grow directly to the amorphous silicon active layer (15) and the amorphous silicon contact layer (13) like crystal growth.

Therefore, after forming the first layer SiNx film and the second layer SiNx film, the gate (3) is etched through the pinhole, and the gate (3) is larger than the pinhole (10) and the glass substrate ( 2) exposed pinhole (1
6). A wet etching method is preferable, for example, etching with ceric ammonium nitrate and HClO4.
Use an etching solution containing

As a result, even if a conductive material, such as amorphous silicon or a metal such as Al, is deposited on the SiNx film (8), the glass substrate (2) will pass through the pinhole (10).
) The conductive material deposited on the surface does not come into contact with the gate (3), gate line (6) and auxiliary capacitance electrode (4), thereby preventing short circuits. Subsequently, TF on the SiNx film (8)
In the region corresponding to T(1), an amorphous silicon active layer (15) and an N+ type amorphous silicon film (13) are stacked. Also, the source electrode (11)
A Cr film (14) is laminated on the silicon film (13) for adhesion to the drain electrode (12). Further, in order to extract signals from the source and drain of the amorphous silicon active layer (15), the channel regions of the N+ type amorphous silicon film (13) and the Cr film (14) are removed by etching.

Further, in the upper layer, there is a drain electrode (12) and a drain line (9) integrated with this drain electrode (12).
, a source electrode (11) and a display electrode (17) integrated with this source electrode (11), respectively, are provided with an I
A TO film (18) is provided. In the figure, the points are hatched. The drain electrode, the drain line integrated with the drain electrode, and the source electrode are covered with ITO.
In order to reduce the resistance value of the film (18), Cr film and Fe
Cu films containing approximately 1% of However, it is not deposited on the display electrode (17).

Although not shown below, an alignment film made of, for example, polyimide is provided in the upper layer. on the other hand,
A counter glass substrate paired with the glass substrate (2) is provided, and the counter glass substrate is provided with a light shielding film at a position corresponding to the TFT and a counter electrode. Furthermore, the above-mentioned alignment film is provided. Furthermore, a spacer is provided between the pair of glass substrates, the periphery is sealed with a sealing material, and liquid crystal is injected through the injection hole to obtain the present device.

[0022]

[Effects of the Invention] As is clear from the above explanation, even if a pinhole is formed in the insulating layer on the gate, the surface of the glass substrate is exposed at the position corresponding to the pinhole in the insulating layer, and a large pin is formed in the gate. By forming the holes, short circuits between the gate and the amorphous silicon film or electrode can be prevented. Similarly, it is possible to prevent a short circuit at the cross section between the gate line and the drain line.

Moreover, since the insulating layer is provided in two layers, the pinholes in the first insulating layer can be filled with the second insulating layer, and the pin holes generated in the second insulating layer can be filled. Holes can be reduced or eliminated. Furthermore, even in this structure consisting of two insulating layers, when a pinhole occurs,
Since the gate has a large pinhole, short circuits with the gate can be eliminated as described above.

[0024] Therefore, it is possible to prevent the TFT from stopping or malfunctioning due to short circuits, and it is possible to improve the yield. Furthermore,
Since the connecting portion between the gate line and the gate terminal is covered with an insulating layer, the gate line is not etched when etching the pinhole, thereby preventing a decrease in yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a liquid crystal display device of the present invention.

FIG. 2 is a cross-sectional view of a conventional liquid crystal display device.

[Explanation of symbols]

(1) TFT (2) Glass substrate (3) Gate (5) Gate terminal (6) Gate line (8) SiNx film (10) Pinhole (16) Pinhole

Claims (4)

[Claims] 1. A liquid crystal display device in which a plurality of gate lines and a plurality of drain lines are formed on a transparent insulating substrate, and a TFT switching element and a display electrode are formed at the intersections of the gate lines, at least the source electrode of the TFT. and the TF from the layer contacting the drain electrode in the lower layer.
A liquid crystal display device characterized in that a gate corresponding to a series of pinholes up to the surface of the T gate is provided with a pinhole larger in size than the pinhole. 2. A liquid crystal display device in which a plurality of gate lines and a plurality of drain lines are formed on a transparent insulating substrate, and a switching element of a TFT and a display electrode are formed at the intersections of the gate lines and a plurality of drain lines. TFT
A liquid crystal display device characterized in that an insulating layer formed between the amorphous silicon active layer and the amorphous silicon active layer has a two-layer structure and is formed in different steps. 3. The liquid crystal display device according to claim 2, wherein the insulating layer is comprised of a silicon oxide film and a silicon ticker film from the bottom. 4. At least the insulating layer, the amorphous silicon active layer, and the amorphous silicon contact layer are laminated between the gate of the TFT and the source and drain electrodes of the TFT. The liquid crystal display device according to claim 1 or claim 3.