JPH04326436A - Cache controller - Google Patents

Abstract

PURPOSE:To reduce the quantity of a memory to exchange at the time of the occurrence of an error, to improve the efficiency of memory use and to shorten time to write into the memory by substituting only an address in which the error occurs. CONSTITUTION:An address retrieving circuit 10 inspects whether there is the address of a cache memory 2 outputted from a DMA controller 6 in a faulty address table 9. When it does not exist, the inputted address is given to the cache memory 2 as it is. When the address exists, an address conversion circuit 11 reads an alternative address from the faulty address table 9 and gives it to the cache memory 2. Afterward, an alternative memory area 8 is used by an address unit. When the error occurs at the time of reading from the cache memory 2, a microprocessor 7 registers the address in which the error occurs and the alterative address in the faulty address table 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of a cache memory in a data processing device.

0002

2. Description of the Related Art Conventionally, there is a device shown in FIG. 2 that incorporates a cache memory. In the figure, 1 is a disk device, 2 is a cache memory, 3 is a cache controller that manages the cache memory 2, and 4 is a disk I/F that controls the disk device. 5 is a host adapter that controls transfer with a host computer (not shown); 6 is a cache memory 2 and host adapter 5;
, D that controls data transfer between disk I/F4
It is an MA controller. 7 is a microprocessor that manages the entire disk cache device.

Next, the operation will be explained. Assume that there is a read request to the disk device 1 from a host computer (not shown) through the host adapter 5. If the requested data is in the cache memory 2, the data is stored in the cache memory 2 without accessing the disk device 1.
(This is called a cache hit). If the requested data does not exist in the cache memory 2, the disk device 1 is accessed to read the data. Then, the area on the cache memory 2 is designated as LRU (Least Recently Used).
algorithm, i.e. the longest unused algorithm)
The data is stored and transferred to the host according to the following algorithm (this is called a cache miss).

[0004] In the case of a cache hit, if an error occurs while reading data from the cache memory 2, the entire block, which is a cache management unit, is deemed to be defective and unusable. Then, a new area is secured on the cache memory, data is read from the disk device 1, and data is written. It also transfers data to the host. In other words, the entire block was replaced by processing similar to a cache miss.

However, in this method, even normal areas in which no errors have occurred are separated all at once, resulting in poor memory utilization efficiency. As one solution to this problem, Japanese Patent Application Laid-Open No. 2-168314 proposes that the memory address where the error occurred is memorized during initial diagnosis, and if this address is subsequently accessed, 1 is added to the address and the memory is stored. access, and from now on, all consecutive accesses within the block containing this address will be set to 1 at the address.
By adding and accessing it, it was possible to isolate only the address where the error occurred.

[0006] The above method is applied to the address of an error detected at the time of initial diagnosis, and does not take into account errors that occur during use. In other words,
With this method, when an error occurs, it is necessary to sequentially shift the data at subsequent addresses, but it is impossible to rewrite the large amount of data that has already been stored, so it is not possible to It cannot be applied to time errors.

[0007]

[Problems to be Solved by the Invention] Conventional cache memory control circuits are configured as described above, so that when a memory error occurs during normal use, the entire block is replaced with an alternative block. There was a problem that it was inefficient and required time to rewrite the whole thing.

The present invention has been made to solve the above-mentioned problems, and aims to reduce the amount of memory to be replaced when an error occurs, improve memory usage efficiency, and shorten the writing time to cache memory. With the goal.

[0009]

[Means for Solving the Problems] A cache controller according to the present invention includes a storage table for addresses where a memory error has occurred, and defective address search means for searching the table when accessing data. , address conversion means is provided for specifying and accessing an alternative address for an address found to be defective through a search.

0010

[Operation] The cache controller in this invention is
Thereafter, an alternative memory area is used in address units for the address for which an error was detected during access.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an example in which the present invention is applied to a disk cache. In FIG. 1, 2 is a cache memory, and 8 is a new alternative area provided within the cache memory 2. In FIG. 13 is a cache controller, and the following new circuit has been added. That is, 9 is a defective address table that stores a plurality of pairs of the address of a defective memory cell in the cache memory 2 and the address of its replacement cell, and 10 is a DMA.
a defective address search circuit for searching whether the output address from the controller 6 is a defective address; 11 is a DM;
This is a circuit for converting to an alternative address when the A output address is in the defective address table. In the case of an example in which an alternative address already exists in the defective table, a circuit for simply reading it may be sufficient. 7 is the same microprocessor as in the conventional example.

Next, the operation will be explained. Cache memory 2
When accessing the cache memory 2, the address of the cache memory 2 output from the DMA controller 6 is first input to the address search circuit 10. Address search circuit 1
0 checks whether this address exists in the defective address table 9, and if it does not exist, the input address is given as is to the cache memory 2, but if the address exists, an alternative address is given as a defective address. It is read from the address table 9 and applied to the cache memory 2. On the other hand, if an error occurs when reading from the cache memory 2, the microprocessor 7 registers the address where the error occurred and an address to replace it in the defective address table 9.

In this way, re-storing of data from the disk device 1 to the block containing the defective memory cell and reading of data thereafter are performed by the address search circuit 10 described above, and access to the defective memory cell is substituted. Access to memory cells.

In the above embodiments, a disk cache has been described, but a CPU cache or a main storage device may also be used, and the same structure as in the disk cache embodiment described above can produce the same effects.

[0015]

[Effects of the Invention] As described above, according to the present invention, the error
Since only the address where the error occurred is replaced, the memory is used more efficiently and the rewrite time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a cache controller that is an embodiment of the present invention.

FIG. 2 is a block diagram of a device incorporating a conventional cache memory.

[Explanation of symbols]

8 Alternative area 9 Defective address table 10 Defective address search circuit 11
address conversion circuit

Claims (1)

[Claims] 1. A table for storing addresses where memory errors occur when reading or writing data to the cache memory, and a defective address for searching the table when reading or writing data to the cache memory. A cache controller comprising a search means, and an address conversion means for instructing an alternative address and reading or writing data to the alternative address if a defective address is found as a result of the above search.