JPH04326519A - Etching method of polysilicon on vertical high step-difference - Google Patents
Etching method of polysilicon on vertical high step-differenceInfo
- Publication number
- JPH04326519A JPH04326519A JP12183591A JP12183591A JPH04326519A JP H04326519 A JPH04326519 A JP H04326519A JP 12183591 A JP12183591 A JP 12183591A JP 12183591 A JP12183591 A JP 12183591A JP H04326519 A JPH04326519 A JP H04326519A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- polysilicon
- difference
- deposited
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052736 halogen Inorganic materials 0.000 claims description 6
- 150000002367 halogens Chemical class 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、電子デバイス等の製造
プロセスに用いられるポリシリコンのドライエッチング
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dry etching polysilicon used in the manufacturing process of electronic devices and the like.
【0002】0002
【従来の技術】従来、段差構造をもつSiデバイスの段
差はなだらかな構造を持ち、段差全面に堆積したポリシ
リコンをハロゲンガスでドライエッチングする際、段差
側壁に残渣を残さないための追加エッチングをそのまま
実行しても段差側壁部近傍に柵状堆積膜が生ずる問題は
起きなかった。しかしながら、集積度が上がるとデバイ
スの段差構造がほぼ垂直になり、段差側壁に残渣を残さ
ないために追加のエッチングを実行すると、図1に示す
ように半導体基板1上の垂直段差2の側壁からポリシリ
コン膜厚と同程度離れた場所に、酸化膜と推測される柵
状の堆積膜3が生成し、その結果、ポリシリコン残渣4
が生じやすくなる。[Prior Art] Conventionally, the steps of a Si device with a step structure have a gentle structure, and when polysilicon deposited on the entire surface of the step is dry-etched with halogen gas, additional etching is required to avoid leaving residue on the side walls of the step. Even if the process was carried out as is, there was no problem of formation of a fence-like deposited film near the step sidewall. However, as the degree of integration increases, the step structure of the device becomes almost vertical, and if additional etching is performed to avoid leaving residue on the sidewalls of the step, as shown in FIG. A fence-shaped deposited film 3, which is presumed to be an oxide film, is formed at a distance about the same as the thickness of the polysilicon film, and as a result, polysilicon residue 4
becomes more likely to occur.
【0003】0003
【発明が解決しようとする課題】このように、素子の微
細化が進むとデバイスの構造が立体化し、急峻な段差構
造を持つようになるが、垂直段差上に成長させたポリシ
リコンをドライエッチングすると、段差近傍に柵状堆積
膜が形成され、その結果、ポリシリコン残渣が生じ、デ
バイスの製造歩留まりや信頼性を低下させるという欠点
がある。本発明の目的は、上記のような課題が解決され
た垂直高段差上のポリシリコンエッチング方法を提供す
ることにある。[Problems to be Solved by the Invention] As the miniaturization of elements progresses, the structure of the device becomes three-dimensional and has a steep step structure, but dry etching of polysilicon grown on the vertical step structure As a result, a fence-like deposited film is formed near the step, resulting in polysilicon residue, which has the disadvantage of lowering the manufacturing yield and reliability of the device. An object of the present invention is to provide a method for etching polysilicon on a vertical high step, which solves the above-mentioned problems.
【0004】0004
【課題を解決するための手段】本発明は、半導体基板上
の段差上に堆積したポリシリコンを、ハロゲンを含んだ
エッチングガスでエッチング完了直前まで選択的にエッ
チングし、次いで所定濃度のフッ酸で所定時間エッチン
グした後、前記エッチングガスで所望の時間引き続きエ
ッチングして段差側壁に堆積したポリシリコンを除去す
ることを特徴とする垂直高段差上のポリシリコンのエッ
チング方法である。[Means for Solving the Problems] The present invention selectively etches polysilicon deposited on a step on a semiconductor substrate with an etching gas containing halogen until just before etching is completed, and then etches it with hydrofluoric acid at a predetermined concentration. This method of etching polysilicon on a vertical high step includes etching for a predetermined time and then continuing etching for a desired time using the etching gas to remove polysilicon deposited on the sidewall of the step.
【0005】[0005]
【作用】本発明においては、ほぼ垂直な段差上に堆積し
たポリシリコンをハロゲンガスでドライエッチングする
際、エッチング完了の直前に所定濃度のフッ酸で所定時
間ウェットエッチングし、段差側壁のポリシリコン残渣
表面に堆積している酸化物と考えられる堆積膜を除去す
ることによって、柵状堆積膜の発生を未然に防ぐ。しか
る処理の後に、段差側壁のポリシリコン残渣を除去する
ための追加ドライエッチングを行うことで、段差側壁の
ポリシリコンは完全にエッチング除去される。[Operation] In the present invention, when dry etching polysilicon deposited on a substantially vertical step with halogen gas, wet etching is performed for a predetermined period of time with hydrofluoric acid at a predetermined concentration immediately before the completion of etching to remove polysilicon residues on the side walls of the step. By removing the deposited film that is considered to be an oxide deposited on the surface, the formation of a fence-like deposited film is prevented. After such treatment, additional dry etching is performed to remove polysilicon residue on the sidewalls of the step, thereby completely etching away the polysilicon on the sidewalls of the step.
【0006】[0006]
【実施例】次に、本発明の実施例について、図面を参照
して説明する。図2は、本発明の方法に用いられる試料
の断面図である。試料はシリコン基板1上にSi酸化膜
をLPCVD法で堆積し、その後、フォトレジスト層を
形成した後、光リソグラフィー技術によりパタ−ニング
してマスクを形成し、ドライエッチングしてSi酸化膜
の段差2を形成した。この段差上にLPCVD法で堆積
したポリシリコンに燐を熱拡散した20Ω/□のシ−ト
抵抗を有するn+ポリシリコン膜5があり、その上にn
+ポリシリコン膜5のエッチングマスクとなるSi酸化
膜6を光リソグラフィー技術とドライエッチング技術に
より形成した。n+ポリシリコン膜5をエッチングする
ためのドライエッチング装置は、13.56MHzのカ
ソ―ドカップル方式でバッチ処理式の平行平板型エッチ
ャ―を用いた。エッチングガスとしてはHBrガスを用
い、HBrガスはマスフロ−コントロ−ラにより20S
CCM流し、圧力7Pa、RFパワ550Wにてエッチ
ングし、そのエッチング完了直前に希釈したフッ酸(H
F:H2O=1:400)でウェットエッチングを2分
30秒施し、その後段差側壁に堆積したポリシリコン残
渣をエッチング除去するため、被エッチング膜厚の25
0%の追加エッチングを行った。得られた試料は図3に
示すように、図2における柵状堆積膜3がきれいに除去
され、段差側壁にはポリシリコン残渣も認められない。
フッ酸の濃度はHF:H2O=1:200、1:100
でも当然上記の効力はあり、ウェットエッチング時間は
フッ酸の濃度に対して任意に変えることができる。本実
施例では、n+ポリシリコンを用いたが、p+ポリシリ
コン、ノンド―プドポリシリコンを用いても本発明の効
果に変わりはない。また本発明では、ハロゲンガスにH
Brを使用したが、HCl,HF等、他のハロゲンガス
を使用しても本発明は効力を発揮する。また、ドライエ
ッチング装置はRF高周波放電を用いているが、磁場を
有する放電を用いたエッチング装置を用いても、本発明
の効果に変わりはない。Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view of a sample used in the method of the present invention. For the sample, a Si oxide film is deposited on a silicon substrate 1 by the LPCVD method, then a photoresist layer is formed, a mask is formed by patterning by photolithography technology, and the steps of the Si oxide film are removed by dry etching. 2 was formed. On this step, there is an n+ polysilicon film 5 having a sheet resistance of 20Ω/□, which is made by thermally diffusing phosphorus into polysilicon deposited by the LPCVD method.
+Si oxide film 6, which serves as an etching mask for polysilicon film 5, was formed by photolithography and dry etching. As a dry etching apparatus for etching the n+ polysilicon film 5, a 13.56 MHz cathode couple batch processing type parallel plate etcher was used. HBr gas was used as the etching gas, and the HBr gas was heated at 20S by a mass flow controller.
Etching was performed using CCM flow, a pressure of 7 Pa, and an RF power of 550 W. Immediately before the etching was completed, diluted hydrofluoric acid (H
Wet etching was performed for 2 minutes and 30 seconds using F:H2O=1:400), and then the thickness of the film to be etched was 25 mm in order to remove the polysilicon residue deposited on the side walls of the step.
0% additional etching was performed. In the obtained sample, as shown in FIG. 3, the fence-like deposited film 3 in FIG. 2 was completely removed, and no polysilicon residue was observed on the step sidewalls. The concentration of hydrofluoric acid is HF:H2O=1:200, 1:100
However, the above effects are of course present, and the wet etching time can be changed arbitrarily depending on the concentration of hydrofluoric acid. In this embodiment, n+ polysilicon is used, but the effects of the present invention will not change even if p+ polysilicon or non-doped polysilicon is used. Further, in the present invention, H is added to the halogen gas.
Although Br was used, the present invention is effective even if other halogen gases such as HCl and HF are used. Further, although the dry etching apparatus uses RF high-frequency discharge, the effects of the present invention will not change even if an etching apparatus using discharge with a magnetic field is used.
【0007】[0007]
【発明の効果】以上説明したように、本発明によれば柵
状堆積膜の発生を未然に防ぐことができ、段差側壁のポ
リシリコンは完全にエッチング除去される。従って、今
後の立体化したデバイス構造に対し、デバイスの製造歩
留まりおよび信頼性を向上させることができる。As explained above, according to the present invention, it is possible to prevent the formation of a fence-like deposited film, and the polysilicon on the step sidewalls is completely etched away. Therefore, it is possible to improve device manufacturing yield and reliability for future three-dimensional device structures.
【図1】従来例によるエッチング方法を説明するための
半導体チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a conventional etching method.
【図2】本発明の方法を説明するための半導体チップの
断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining the method of the present invention.
【図3】本発明の方法によって得られた半導体チップの
断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip obtained by the method of the present invention.
1 基板
2 段差3 柵状堆積膜
4 ポリシリ
コン残渣1 board
2 Step 3 Palisade-like deposited film
4 Polysilicon residue
Claims (1)
シリコンを、ハロゲンを含んだエッチングガスでエッチ
ング完了直前まで選択的にエッチングし、次いで所定濃
度のフッ酸で所定時間エッチングした後、前記エッチン
グガスで所望の時間引き続きエッチングして段差側壁に
堆積したポリシリコンを除去することを特徴とする垂直
高段差上のポリシリコンのエッチング方法。1. Selectively etching polysilicon deposited on a step on a semiconductor substrate with an etching gas containing halogen until immediately before etching is completed, then etching with hydrofluoric acid at a predetermined concentration for a predetermined time, and then etching the polysilicon deposited on a step on a semiconductor substrate. 1. A method for etching polysilicon on a vertical high level difference, characterized in that polysilicon deposited on the sidewall of the level difference is removed by continuing etching with a gas for a desired time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12183591A JPH04326519A (en) | 1991-04-25 | 1991-04-25 | Etching method of polysilicon on vertical high step-difference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12183591A JPH04326519A (en) | 1991-04-25 | 1991-04-25 | Etching method of polysilicon on vertical high step-difference |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04326519A true JPH04326519A (en) | 1992-11-16 |
Family
ID=14821112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12183591A Pending JPH04326519A (en) | 1991-04-25 | 1991-04-25 | Etching method of polysilicon on vertical high step-difference |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04326519A (en) |
-
1991
- 1991-04-25 JP JP12183591A patent/JPH04326519A/en active Pending
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