JPH04326544A - Equipment and method for inspecting external appearance of wafer - Google Patents

Abstract

PURPOSE:To easily inspect in a short time the deviation of integrated circuit patterns in the wafer surface and an exposure region. CONSTITUTION:A storage device is installed in a control part 6 control- commanding a controller 7 moving a stage 2 mounting a wafer 8. An integrated circuit pattern transferred on the outer side and the central part in the surface of the wafer 8 and an integrated circuit pattern in an exposure region in the surface of the wafer 8 are arbitrarily extracted. Position for each wafer is previously stored by the control part 6, and automatically positioned in the visual field of a microscope in order. Thereby the deviation of integrated circuit patterns are inspected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a wafer visual inspection apparatus and method for inspecting a large number of integrated circuit patterns formed on a wafer in a lithography process.

0002

[Prior Art] Conventionally, although not shown in the drawings, this type of wafer visual inspection apparatus has a stage for mounting a wafer, a transfer mechanism for transferring the wafer from a carrier to the stage, and a transfer mechanism for transferring the wafer mounted on the stage. It consists of an optical microscope for observation.

When performing a wafer appearance inspection in a lithography process using this wafer appearance inspection apparatus, first,
The stage is manually operated by an operator, and an unspecified integrated circuit pattern is uniformly selected from among the large number of integrated circuit patterns formed on the wafer from the top, center, bottom, right, and left of the wafer surface. A number of integrated circuit patterns were selected, and the integrated circuit patterns were inspected for appearance and measured for pattern misalignment.

0004

[Problems to be Solved by the Invention] In the visual inspection method using this conventional wafer visual inspection apparatus, one integrated circuit pattern is selected and measured from each of the top, bottom, center, left, and right sides of the wafer. Therefore, it is possible to inspect the positional deviation of the circuit pattern and the deviation in the degree of pattern reduction within the wafer surface. However, on a wafer where multiple integrated circuit patterns are transferred in one exposure, that is, in one shot, the difference between each integrated circuit pattern can be inspected. The inclination and distortion of is difficult to measure. If this were to be measured, it would be necessary to position each integrated circuit pattern within one shot, measure the amount of misalignment of each integrated circuit pattern, and measure the amount of misalignment within the wafer plane and the amount of misalignment of each integrated circuit pattern within one shot. It is necessary to estimate the slope and distortion between patterns, which not only wastes a large amount of man-hours but also causes errors.

SUMMARY OF THE INVENTION In order to solve this problem, it is an object of the present invention to provide a wafer appearance inspection apparatus and a wafer visual inspection apparatus that can easily inspect misalignment between integrated circuits within one shot and misalignment of integrated circuit patterns within a wafer surface in a short time. The purpose is to provide a method for doing so.

[0006]

[Means for Solving the Problems] The wafer appearance inspection apparatus of the present invention includes a microscope for observing the wafer surface, a stage on which the wafer is placed, a controller for moving the stage, and a control unit for controlling the controller. , and a storage unit that stores the positions of a plurality of areas of the integrated circuit pattern within the wafer plane with respect to the wafer.

The wafer visual inspection method of the present invention includes the steps of extracting an arbitrary integrated circuit pattern from among a plurality of patterns arranged in columns and rows on the wafer surface, and storing the position of the extracted integrated circuit pattern. , sequentially positioning the integrated circuit pattern within a microscope field of view.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a wafer visual inspection apparatus showing an embodiment of the present invention. As shown in FIG. 1, this wafer appearance inspection apparatus includes a light source unit 1 that projects light onto the wafer surface via a rear mirror 4 and a lens 3, and lenses 3 and 3a that form an enlarged image using reflected light from the wafer 8. an optical microscope, a stage 2 on which the wafer 8 is mounted, a transport mechanism 5 for transferring the wafer 8 onto the stage 2, a controller 7 for controlling the movement of the stage 2, and 8 wafers in the pattern area to be inspected. It has a control section 6 which stores the position of the stage and instructs the controller to move the stage. FIG. 2 is a diagram showing a wafer surface for explaining the operation of the wafer visual inspection apparatus shown in FIG. Next, the operation of this wafer visual inspection apparatus and the wafer visual inspection method will be explained. As a preparatory work before performing the initial visual inspection, first, as shown in FIG. Certain integrated circuit patterns 9a, 9b, 9c, 9d, and 9e are selected and their coordinate values are stored in the control section 6. Next, in order to measure the amount of misalignment in one-shot exposure, the integrated circuit patterns in the one-shot area 10 are compared to the integrated circuit patterns 11a on the right, left, top and bottom of that area.
, 11b, 11c, and 11d, and their coordinate values are stored in the control unit.

[0010] In order to inspect a wafer using the wafer visual inspection apparatus prepared in this manner, first, a wafer carrier containing a wafer to be inspected is placed at a transport start position. Here, the wafers 8 in the wafer carrier are automatically transferred onto the stage 2 one by one by the transfer mechanism 5. Next, integrated circuit patterns 9a, 9b, 9c, 9d, and 9e stored in advance in the control unit 6 for each product type.
The wafer 8 is positioned within the field of view of the microscope by the controller 7 based on the coordinate values of , and the misalignment of the integrated circuit patterns within the plane of the wafer 8 is inspected by sequentially measuring the misalignment using the microscope. Next, the coordinate values of the integrated circuit patterns 11a, 11b, 11c, and 11d stored in the control unit 6 are read out, and the stage 2 is moved by the controller 7, so that the integrated circuit patterns 11a, 11b, 11c, and 11d are placed within the field of view of the microscope. After positioning, the amount of misalignment is sequentially measured, and the integrated circuit pattern within the one-shot area is inspected.

The wafer 8 that has been inspected is transferred to the transport mechanism 5.
The wafer 8 is stored in the wafer carrier, and the next wafer 8 is placed on the stage 2. In this way, the wafers are placed one after another, the integrated circuit patterns to be inspected are automatically positioned within the field of view of the microscope, and the operator can check the misalignment of the integrated circuit patterns within the plane of the wafer by simply observing with the microscope. It is also possible to inspect misalignment of integrated circuit patterns within one shot.

0012

Effects of the Invention As explained above, the present invention provides a storage section in the control section that commands and controls the controller that moves the stage on which the wafer is mounted, and the integrated circuit pattern to be transferred to the outside and center of the wafer surface. By extracting the outer integrated circuit pattern within one exposure area in advance and storing the position of the integrated circuit pattern in the storage unit, the misalignment of the integrated circuit pattern within the wafer surface and within one exposure area can be prevented for a short time. This has the effect of providing a wafer appearance inspection device that can easily inspect wafers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a wafer visual inspection apparatus showing an embodiment of the present invention.

FIG. 2 is a diagram showing a wafer surface for explaining the operation of the wafer visual inspection apparatus of FIG. 1;

[Explanation of symbols]

1 Light source section 2 Stage 3,3a Lens 4 Half mirror 5 Conveyance mechanism 6 Control section 7 Controller 8 Wafer

Claims (2)

[Claims] 1. A microscope for observing a wafer surface, a stage for placing a wafer, a controller for moving this stage, and a control section for controlling this controller.
A wafer visual inspection apparatus comprising: a storage unit that stores positions of a plurality of areas of integrated circuit patterns within the wafer plane with respect to the wafer. 2. A step of extracting an arbitrary integrated circuit pattern from among a plurality of patterns arranged in columns and rows on the wafer surface, a step of storing the position of the extracted integrated circuit pattern, and sequentially placing the integrated circuit pattern within the field of view of the microscope. A wafer appearance inspection method comprising the step of positioning the integrated circuit pattern.