JPH04326568A - Capacity element - Google Patents

Capacity element

Info

Publication number
JPH04326568A
JPH04326568A JP12240891A JP12240891A JPH04326568A JP H04326568 A JPH04326568 A JP H04326568A JP 12240891 A JP12240891 A JP 12240891A JP 12240891 A JP12240891 A JP 12240891A JP H04326568 A JPH04326568 A JP H04326568A
Authority
JP
Japan
Prior art keywords
film
melting point
high melting
point metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12240891A
Other languages
Japanese (ja)
Inventor
Minoru Nakamura
稔 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP12240891A priority Critical patent/JPH04326568A/en
Publication of JPH04326568A publication Critical patent/JPH04326568A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To enable a dielectric film to be thinned so as to enlarge the capacity per unit area, in an MIM-type capacity element being made in an IC. CONSTITUTION:A dielectric film 5 is made on the section of the lower electrode 3a consisting of the high melting point metallic film 3 (Ti, W, Mo, TiN, WSi, and MoSi) at the first layer on the field insulating film 2 on a semiconductor substrate 1, and wiring film 4 is made on other part, and an upper electrode 6 consisting of high melting point metal at the second layer is made on the above dielectric film 5. An Al film 7 made on the topside of the upper electrode 6 prevents the upper electrode 6 from being corroded by the selective etching to a layer insulating film 8. Contact holes 9 and 10 are made in the layer insulating film 8, and Al films 11 and 12 for taking out the upper and lower electrodes are made. Even if it is heat-treated, hyrocs or voids do not occur in the electrode consisting of high melting point metal, so the dielectric film can be thinned, and the capacity per unit area can be made large.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、容量素子、特にIC内
に形成される容量素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element, and particularly to a capacitive element formed within an IC.

【0002】0002

【従来の技術】IC内に形成される通常の容量素子は、
図9の(A)に示すようにMIS構造を有していた。図
面において、aはp型半導体基板、bはn型エピタキシ
ャル層、cはp+ 型アイソレーション層、dは上記エ
ピタキシャル層の表面部に形成されたn+ 型拡散層で
、容量素子の下側電極を成す。eは絶縁膜fの開口gに
形成された誘電体膜で、例えばLPSiN(減圧CVD
により形成されたSiN)あるいはSiO2 からなり
、上記拡散層dに直接接している。
[Prior Art] A normal capacitive element formed in an IC is
It had an MIS structure as shown in FIG. 9(A). In the drawing, a is a p-type semiconductor substrate, b is an n-type epitaxial layer, c is a p+-type isolation layer, and d is an n+-type diffusion layer formed on the surface of the epitaxial layer, which connects the lower electrode of the capacitive element. I will do it. e is a dielectric film formed in the opening g of the insulating film f, and is made of, for example, LPSiN (low pressure CVD).
It is made of SiN) or SiO2, and is in direct contact with the diffusion layer d.

【0003】hは絶縁膜fの別の開口g部に形成された
アルミニウムからなる電極膜、iは上記誘電体膜e上に
形成されたアルミニウムからなるところの上側電極であ
る。このようなMIS構造の容量素子は、寄生抵抗を下
げるべく高濃度の拡散層dにより容量素子の下側電極を
形成するが、10−2Ωcm程度の寄生抵抗rができる
ことは避け得ない。また、p型の半導体基板aとn型エ
ピタキシャル層bとの間のpn接合によって1×10−
8F/cm2 の寄生容量Caが生じるのも避け得ない
。図9の(B)はMIS型容量素子の等価回路である。 このように寄生抵抗、寄生容量が大きいと、周波数特性
の向上を図ることが難しい。
Reference character h is an electrode film made of aluminum formed in another opening g of the insulating film f, and i is an upper electrode made of aluminum formed on the dielectric film e. In such a capacitive element having an MIS structure, the lower electrode of the capacitive element is formed by a highly doped diffusion layer d in order to reduce parasitic resistance, but it is unavoidable that a parasitic resistance r of about 10 -2 Ωcm is generated. In addition, the pn junction between the p-type semiconductor substrate a and the n-type epitaxial layer b provides 1×10−
It is also unavoidable that a parasitic capacitance Ca of 8 F/cm2 occurs. FIG. 9B shows an equivalent circuit of the MIS type capacitive element. If the parasitic resistance and capacitance are large as described above, it is difficult to improve the frequency characteristics.

【0004】そこで、高周波用容量素子として図10に
示すようなMIM構造の容量素子が開発された。この容
量素子は、半導体基板aのフィールド絶縁膜f上にアル
ミニウムからなる下側電極kを形成し、該下側電極k上
に誘電体膜lを介してアルミニウムからなる上側電極m
を形成したものである。nは下側電極kの端子電極であ
る。このような容量素子は、寄生抵抗が3×10−9F
/cm2 、寄生容量が3×10−6Ωと、MIS型容
量素子に比較して寄生抵抗、寄生容量が非常に小さく、
その点で優れているといえる。
[0004] Therefore, a capacitive element having an MIM structure as shown in FIG. 10 was developed as a high frequency capacitive element. This capacitive element has a lower electrode k made of aluminum formed on a field insulating film f of a semiconductor substrate a, and an upper electrode m made of aluminum formed on the lower electrode k via a dielectric film l.
was formed. n is a terminal electrode of the lower electrode k. Such a capacitive element has a parasitic resistance of 3 x 10-9F.
/cm2, and the parasitic capacitance is 3 x 10-6Ω, which is extremely small compared to MIS type capacitive elements.
It can be said that it is excellent in that respect.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、MIM
型の容量素子は、下側電極、上側電極としてアルミニウ
ムあるいはアルミニウム系の金属を用いるので、下側電
極、上側電極の形成後の熱処理によりヒロックやボイド
が発生し、誘電体膜lを破ってしまい、下側電極kと上
側電極mとの間がショートしてしまう虞れがあった。そ
こで、それを回避するために誘電体膜lの膜厚を厚くす
る必要があった。具体的には4000オングストローム
以上の膜厚にする必要があった。しかし、誘電体膜の厚
さをそのように厚くすると容量素子の単位面積当りの容
量が小さくなり、延いては誘電体膜の占有面積が広くな
るという問題があった。これはIC、LSI、VLSI
の高集積化を阻む要因となるので好ましくないのである
[Problem to be solved by the invention] However, MIM
This type of capacitive element uses aluminum or aluminum-based metal for the lower and upper electrodes, so heat treatment after forming the lower and upper electrodes can cause hillocks and voids that can break the dielectric film. , there was a risk that a short circuit would occur between the lower electrode k and the upper electrode m. Therefore, in order to avoid this, it was necessary to increase the thickness of the dielectric film l. Specifically, the film thickness needed to be 4000 angstroms or more. However, if the thickness of the dielectric film is increased in this way, the capacitance per unit area of the capacitive element becomes smaller, and as a result, the area occupied by the dielectric film becomes larger. This is IC, LSI, VLSI
This is undesirable because it becomes a factor that hinders high integration.

【0006】本発明はこのような問題点を解決すべく為
されたものであり、容量素子の単位面積当りの容量を大
きくすることを目的とする。
The present invention has been made to solve these problems, and an object of the present invention is to increase the capacitance per unit area of a capacitive element.

【0007】[0007]

【課題を解決するための手段】本発明容量素子は、第1
層目の高融点金属膜の下側電極となる部分上に誘電体膜
を形成し、他部上に配線膜を形成し、上記誘電体膜上に
第2層目の高融点金属からなる上側電極を形成したこと
を特徴とする。
[Means for Solving the Problems] The capacitive element of the present invention has a first
A dielectric film is formed on a portion of the high-melting point metal film that will become the lower electrode, a wiring film is formed on the other portion, and a second upper layer of the high-melting point metal film is formed on the dielectric film. It is characterized by forming an electrode.

【0008】[0008]

【実施例】以下、本発明容量素子を図示実施例に従って
詳細に説明する。図1(A)、(B)は本発明容量素子
の一つの実施例を示すもので、(A)は断面図、(B)
は下側電極を示す平面図である。図面において、1は半
導体基板、2はフィールド絶縁膜、3は第1層目の高融
点金属膜で、例えば、チタンTi、チタンナイトライド
TiN、タングステンW、モリブデンMo、タングステ
ンシリサイドWSiあるいはモリブデンシリサイドMo
Siからなる。3aは該高融点金属膜3のうちの下側電
極部分、3bは高融点金属膜3のうちの配線膜部分であ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the capacitive element of the present invention will be explained in detail according to the illustrated embodiments. FIGS. 1(A) and 1(B) show one embodiment of the capacitive element of the present invention, where (A) is a cross-sectional view and (B) is a cross-sectional view.
FIG. 3 is a plan view showing the lower electrode. In the drawings, 1 is a semiconductor substrate, 2 is a field insulating film, and 3 is a first layer high-melting point metal film, such as titanium Ti, titanium nitride TiN, tungsten W, molybdenum Mo, tungsten silicide WSi, or molybdenum silicide Mo.
Consists of Si. 3a is a lower electrode portion of the high melting point metal film 3, and 3b is a wiring film portion of the high melting point metal film 3.

【0009】4は第1層目の高融点金属膜3の配線膜部
分上に形成されたアルミニウムからなる配線膜で、高融
点金属膜3の配線膜部分3b上に形成されている。5は
下側電極3a上を完全に覆うように形成された誘電体膜
で、例えばプラズマナイトライドP−SiN、プラズマ
一酸化シリコンP−SiO、二酸化シリコンSiO2 
、PSG等からなる。該誘電体膜5は例えば1000オ
ングストオーム程度に薄くされている。6は誘電体膜5
上に形成された第2層目の高融点金属からなる上側電極
で、上記下側電極3aに上記誘電体膜5を介して対向し
ており、該対向電極3a、6及びその間の誘電体膜5に
より本容量素子の主部(要部)である容量部が形成され
ている。
Reference numeral 4 denotes a wiring film made of aluminum formed on the wiring film portion of the first layer high melting point metal film 3, and is formed on the wiring film portion 3b of the high melting point metal film 3. 5 is a dielectric film formed to completely cover the lower electrode 3a, for example, plasma nitride P-SiN, plasma silicon monoxide P-SiO, silicon dioxide SiO2.
, PSG, etc. The dielectric film 5 is made as thin as, for example, about 1000 angstroms. 6 is a dielectric film 5
An upper electrode made of a second layer of high-melting point metal formed above is opposed to the lower electrode 3a with the dielectric film 5 in between, and the opposing electrodes 3a, 6 and the dielectric film therebetween. 5 forms a capacitive part which is the main part (principal part) of this capacitive element.

【0010】7は上側電極6の上面に形成されたアルミ
ニウム膜(あるいはシリコン含有アルミニウム膜)で、
次に述べる層間絶縁膜8に対する選択的エッチングによ
り上側電極を成す高融点金属6が侵蝕されるのを防止す
る役割を果す。即ち、エッチングストッパとなるのであ
る。9、10は層間絶縁膜8に形成されたコンタクトホ
ール、11、12は上側電極、下側電極取り出し用のア
ルミニウム膜である。
7 is an aluminum film (or silicon-containing aluminum film) formed on the upper surface of the upper electrode 6;
The selective etching of the interlayer insulating film 8 described below serves to prevent the high melting point metal 6 forming the upper electrode from being corroded. In other words, it serves as an etching stopper. 9 and 10 are contact holes formed in the interlayer insulating film 8, and 11 and 12 are aluminum films for taking out the upper and lower electrodes.

【0011】本容量素子によれば、誘電体膜5を挟んで
対向して要部を成す対向電極3a、6が高融点金属から
なるので、対向電極形成後の熱処理によってヒロックや
ボイドが発生する虞れがない。従って誘電体膜5を従来
のよりも相当に薄くしても対向電極3a・6間に短絡事
故が生じる虞れがない。依って、容量素子の単位占有面
積当りの静電容量を大きくすることができ、延いては容
量素子の小型化を図ることができる。具体的には、容量
素子の主部である容量部の占有面積を比較すると従来の
MIM型容量素子の4分の1程度にできる。
According to the present capacitive element, since the counter electrodes 3a and 6, which are the main parts and face each other with the dielectric film 5 in between, are made of a high melting point metal, hillocks and voids are generated by heat treatment after forming the counter electrodes. There is no danger. Therefore, even if the dielectric film 5 is made considerably thinner than the conventional one, there is no risk of a short circuit occurring between the opposing electrodes 3a and 6. Therefore, the capacitance per unit occupied area of the capacitor can be increased, and the capacitor can be downsized. Specifically, the area occupied by the capacitive part, which is the main part of the capacitive element, can be reduced to about one-fourth that of a conventional MIM type capacitive element.

【0012】図2乃至図8は図1に示した容量素子の製
造方法の一例を工程順に示す断面図である。 (1)シリコン半導体基板1上のフィールド絶縁膜2の
表面に第1層目の高融点金属膜3を形成し、該高融点金
属膜3上に第1層目のアルミニウム配線膜4を形成する
。該配線膜4及び高融点金属膜3はスパッタリングによ
り形成する。図2は該配線膜4及び高融点金属膜3形成
後の状態を示す。
FIGS. 2 to 8 are cross-sectional views showing an example of a method for manufacturing the capacitive element shown in FIG. 1 in the order of steps. (1) A first layer of high melting point metal film 3 is formed on the surface of field insulating film 2 on silicon semiconductor substrate 1, and a first layer of aluminum wiring film 4 is formed on the high melting point metal film 3. . The wiring film 4 and the high melting point metal film 3 are formed by sputtering. FIG. 2 shows the state after the wiring film 4 and the high melting point metal film 3 are formed.

【0013】(2)次に、図3に示すように該配線膜4
及び高融点金属膜3に対してウェットエッチングにより
パターニングする。これは容量部の下側電極と該下側電
極と接続される配線部分のみが残存するようにパターニ
ングする。 (3)次に、図4に示すように高融点金属膜3上の第1
層目のアルミニウム膜4を、下側電極を形成すべき部分
上に位置する部分を除きエッチングする。3aは第1層
目高融点金属膜3のこのエッチングにより露出するに至
った下側電極を示し、3bは第1層目のアルミニウム膜
4下の部分を示す。
(2) Next, as shown in FIG.
Then, the high melting point metal film 3 is patterned by wet etching. This patterning is performed so that only the lower electrode of the capacitor portion and the wiring portion connected to the lower electrode remain. (3) Next, as shown in FIG.
The layered aluminum film 4 is etched except for the portion located above the portion where the lower electrode is to be formed. 3a shows the lower electrode exposed by this etching of the first layer high melting point metal film 3, and 3b shows the part under the first layer aluminum film 4.

【0014】(4)次に、例えばCVDにより図5に示
すように誘電体膜5を形成する。 (5)次に、図6に示すように第2層目の高融点金属膜
6及び第2層目のアルミニウム膜7を形成する。 (6)次に、図7に示すように第2層目の高融点金属膜
6及び第2層目のアルミニウム膜7をパターニングする
。これにより第2層目の高融点金属により上側電極6が
形成される。 (7)次に、図8に示すように層間絶縁膜8を形成する
(4) Next, as shown in FIG. 5, a dielectric film 5 is formed by, for example, CVD. (5) Next, as shown in FIG. 6, a second layer of high melting point metal film 6 and a second layer of aluminum film 7 are formed. (6) Next, as shown in FIG. 7, the second layer high melting point metal film 6 and the second layer aluminum film 7 are patterned. As a result, the upper electrode 6 is formed from the second layer of high melting point metal. (7) Next, as shown in FIG. 8, an interlayer insulating film 8 is formed.

【0015】その後、該層間絶縁膜8を選択的にエッチ
ングすることによりコンタクトホール9、10を形成し
、その後、アルミニウム膜をスパッタリングにより形成
し、しかる後、アルミニウム膜のパターニングにより配
線膜11、12を形成する。尚、層間絶縁膜8の選択的
エッチングの際に、アルミニウム膜7は薄い高融点金属
からなる上側電極6のエッチングを防止する保護膜(謂
わばエッチングストッパ)としての役割を果すこと前述
のとおりである。
Thereafter, contact holes 9 and 10 are formed by selectively etching the interlayer insulating film 8, and then an aluminum film is formed by sputtering, and then wiring films 11 and 12 are formed by patterning the aluminum film. form. As mentioned above, during the selective etching of the interlayer insulating film 8, the aluminum film 7 plays a role as a protective film (so-called etching stopper) to prevent etching of the upper electrode 6 made of a thin high-melting point metal. be.

【0016】[0016]

【発明の効果】本発明容量素子は、第1層目の高融点金
属膜の下側電極となる一部上に誘電体膜が形成され、上
記高融点金属膜の他部上に配線膜が形成され、上記誘電
体膜上に第2層目の高融点金属からなる上側電極が形成
されたことを特徴とするものである。従って、本発明容
量素子によれば、対向電極が従来のようなアルミニウム
膜ではなく高融点金属により形成されているので、対向
電極形成後の熱処理により該対向電極にヒロックあるい
はボイドが発生する虞れがない。従って、誘電体膜が薄
くても対向電極間の短絡事故が起きなくなる。従って、
誘電体膜を薄くすることができ、延いては容量素子の単
位占有面積当りの静電容量を大きくすることができ、容
量素子の小型化を図ることが可能となる。
Effects of the Invention In the capacitive element of the present invention, a dielectric film is formed on a part of the first layer of the high melting point metal film that will become the lower electrode, and a wiring film is formed on the other part of the high melting point metal film. A second layer of an upper electrode made of a high melting point metal is formed on the dielectric film. Therefore, according to the capacitive element of the present invention, since the counter electrode is formed of a high melting point metal instead of an aluminum film as in the conventional case, there is a risk that hillocks or voids may be generated in the counter electrode due to heat treatment after forming the counter electrode. There is no. Therefore, even if the dielectric film is thin, short circuit accidents between opposing electrodes will not occur. Therefore,
The dielectric film can be made thinner, and the electrostatic capacitance per unit occupied area of the capacitive element can be increased, and the capacitive element can be made smaller.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】(A)、(B)は本発明容量素子の一つの実施
例を示すもので、(A)は断面図、(B)は下側電極及
びそれに接続された配線膜を示す平面図である。
[Fig. 1] (A) and (B) show one embodiment of the capacitive element of the present invention, in which (A) is a cross-sectional view, and (B) is a plane showing a lower electrode and a wiring film connected thereto. It is a diagram.

【図2】図1に示す容量素子の製造方法の一例の第1の
工程を示す断面図である。
FIG. 2 is a cross-sectional view showing a first step of an example of a method for manufacturing the capacitive element shown in FIG. 1;

【図3】同じく第2の工程を示す断面図である。FIG. 3 is a cross-sectional view showing the second step.

【図4】同じく第3の工程を示す断面図である。FIG. 4 is a cross-sectional view showing the third step.

【図5】同じく第4の工程を示す断面図である。FIG. 5 is a cross-sectional view showing the fourth step.

【図6】同じく第5の工程を示す断面図である。FIG. 6 is a cross-sectional view showing the fifth step.

【図7】同じく第6の工程を示す断面図である。FIG. 7 is a cross-sectional view showing the sixth step.

【図8】同じく第7の工程を示す断面図である。FIG. 8 is a cross-sectional view showing the seventh step.

【図9】(A)、(B)は一つの従来例を示すもので、
(A)は断面図、(B)は等価回路図である。
[Fig. 9] (A) and (B) show one conventional example;
(A) is a cross-sectional view, and (B) is an equivalent circuit diagram.

【図10】他の従来例を示す断面図である。FIG. 10 is a sectional view showing another conventional example.

【符号の説明】[Explanation of symbols]

3  第1層目の高融点金属膜 3a  下側電極 3b  配線膜 4  配線膜 5  誘電体膜 3. First layer high melting point metal film 3a Lower electrode 3b Wiring film 4 Wiring film 5 Dielectric film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  第1層目の高融点金属膜の下側電極と
なる一部上に誘電体膜が形成され、上記高融点金属膜の
他部上に配線膜が形成され、上記誘電体膜上に第2層目
の高融点金属からなる上側電極が形成されたことを特徴
とする容量素子
1. A dielectric film is formed on a part of the first layer high melting point metal film that will become the lower electrode, a wiring film is formed on the other part of the high melting point metal film, and the dielectric film is formed on the other part of the high melting point metal film. A capacitive element characterized in that a second layer of an upper electrode made of a high melting point metal is formed on a film.
JP12240891A 1991-04-25 1991-04-25 Capacity element Pending JPH04326568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12240891A JPH04326568A (en) 1991-04-25 1991-04-25 Capacity element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12240891A JPH04326568A (en) 1991-04-25 1991-04-25 Capacity element

Publications (1)

Publication Number Publication Date
JPH04326568A true JPH04326568A (en) 1992-11-16

Family

ID=14835066

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12240891A Pending JPH04326568A (en) 1991-04-25 1991-04-25 Capacity element

Country Status (1)

Country Link
JP (1) JPH04326568A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267093B1 (en) * 1997-04-29 2000-10-02 윤종용 Thin-film capacitor and manufacturing method thereof
US6340832B2 (en) 2000-03-28 2002-01-22 Nec Corporation MIM capacitor having reduced capacitance error and phase rotation
KR100429122B1 (en) * 1999-12-14 2004-05-06 가부시끼가이샤 도시바 Metal insulator metal capacitor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100267093B1 (en) * 1997-04-29 2000-10-02 윤종용 Thin-film capacitor and manufacturing method thereof
KR100429122B1 (en) * 1999-12-14 2004-05-06 가부시끼가이샤 도시바 Metal insulator metal capacitor
US7045415B2 (en) 1999-12-14 2006-05-16 Kabushiki Kaisha Toshiba MIM capacitor having flat diffusion prevention films
US6340832B2 (en) 2000-03-28 2002-01-22 Nec Corporation MIM capacitor having reduced capacitance error and phase rotation

Similar Documents

Publication Publication Date Title
KR100306202B1 (en) Semiconductor device and manufacturing method thereof
JPH05274993A (en) Electrically programmable anti-fuse element
JP2007221161A (en) Capacitor used in semiconductor device and manufacturing method thereof
US20070202656A1 (en) Method of fabricating a semiconductor device
KR100564626B1 (en) Large capacity MIM capacitors and manufacturing method
KR100735521B1 (en) Semiconductor device and manufacturing method thereof
JPH03203261A (en) Semiconductor device
US5929505A (en) Inter-metal-wiring antifuse device provided by self-alignment
JP2001085630A (en) Semiconductor device and method of manufacturing semiconductor device
KR100280565B1 (en) Metal to Metal Capacitor Integration Process
JPH04326568A (en) Capacity element
JPH10144865A (en) Thin film capacitor and method of manufacturing the same
JP2809131B2 (en) Method for manufacturing semiconductor device
JP2001298154A (en) Semiconductor device and method of manufacturing the same
JP2003179163A (en) Semiconductor device and method of manufacturing the same
JP2809172B2 (en) Semiconductor device
JPH07107926B2 (en) Method for manufacturing semiconductor capacitive element
JPS62190850A (en) Semiconductor device
JPH08306878A (en) Method of fabricating semiconductor device
JP2005209788A (en) Semiconductor device
KR100358164B1 (en) Method for forming ferroelectric memory device
JP2000216244A (en) Semiconductor device and manufacturing method thereof
JPH04180227A (en) Semiconductor device
JP2000223570A (en) Semiconductor device and manufacturing method thereof
JPH1174270A (en) Semiconductor device and manufacturing method thereof