JPH0432814Y2 - - Google Patents
Info
- Publication number
- JPH0432814Y2 JPH0432814Y2 JP1986091211U JP9121186U JPH0432814Y2 JP H0432814 Y2 JPH0432814 Y2 JP H0432814Y2 JP 1986091211 U JP1986091211 U JP 1986091211U JP 9121186 U JP9121186 U JP 9121186U JP H0432814 Y2 JPH0432814 Y2 JP H0432814Y2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- differential amplifier
- input
- voltage
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000009499 grossing Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
この考案は電圧リミツタ回路に関するものであ
る。[Detailed description of the invention] [Field of industrial application] This invention relates to a voltage limiter circuit.
第３図は従来の電圧リミツタ回路を示し、１は
入力端子に一端が接続された抵抗、７は抵抗１の
他端と接地間に接続されたコンデンサである。
又、１２は反転増幅器で、電力増幅器１０の非反
転入力端に比較電圧Vrefを印加するとともに出
力端と反転入力端との間に抵抗３を接続し、かつ
反転入力端と抵抗１とコンデンサ７との接続部間
に抵抗２を接続して構成される。１３は電圧リミ
ツタ部で、差動増幅器１１の非反転入力端と電力
増幅器１０の出力端を接続するとともに、差動増
幅器１１の反転入力端に電源電圧Vccを抵抗４，
５で分圧したリミツタ基準電圧VLを入力し、差
動増幅器１１の出力端をダイオード９を介して抵
抗２，３の接続部に接続して構成する。
FIG. 3 shows a conventional voltage limiter circuit, in which 1 is a resistor whose one end is connected to the input terminal, and 7 is a capacitor connected between the other end of the resistor 1 and ground.
Further, 12 is an inverting amplifier, which applies a comparison voltage Vref to the non-inverting input terminal of the power amplifier 10, and connects a resistor 3 between the output terminal and the inverting input terminal, and connects the inverting input terminal, the resistor 1, and the capacitor 7. It is constructed by connecting a resistor 2 between the connecting portions. 13 is a voltage limiter section which connects the non-inverting input terminal of the differential amplifier 11 and the output terminal of the power amplifier 10, and connects the power supply voltage Vcc to the inverting input terminal of the differential amplifier 11 through a resistor 4,
A limiter reference voltage V L divided by 5 is input, and the output terminal of a differential amplifier 11 is connected to the connection between resistors 2 and 3 via a diode 9.
第２図は入力電圧Viと反転増幅器１２の出力
Voとの関係を示し、反転増幅器１２は、抵抗１
〜３の抵抗値をR1〜R3として、
Vo＝R3／R1＋R2Vi＋（１＋R3／R1＋R2）Vref
なる関係式で示される反転増幅動作を行う。この
動作が第２図の傾斜部で示され、出力電圧Voが
VLまで下がると差動増幅器１１の出力がＨから
Ｌに変化し、このため差動増幅器１１はダイオー
ド９を介して反転増幅器１２の入力を吸い込む。
従つて、出力電圧VoはVL以下に下がることがで
きず、Vo＝VL一定で安定する。 Figure 2 shows the input voltage Vi and the output of the inverting amplifier 12.
The relationship between the inverting amplifier 12 and the resistor 1 is shown.
-3 resistance values are set as R1 to R3 , and an inverting amplification operation is performed as shown by the relational expression Vo= R3 / R1 + R2Vi +(1+ R3 / R1 + R2 )Vref. This operation is shown by the slope in Figure 2, and the output voltage Vo is
When the voltage drops to V L , the output of the differential amplifier 11 changes from H to L, and therefore the differential amplifier 11 sucks the input of the inverting amplifier 12 through the diode 9.
Therefore, the output voltage Vo cannot fall below V L and is stabilized at a constant Vo=V L.
しかるに、上記した従来の電圧リミツタ回路で
は、差動増幅器１１が差動して反転増幅器１２の
入力へ帰還がかかつている動作領域において発振
が発生し、動作が不安定になるという問題点があ
つた。
However, the conventional voltage limiter circuit described above has the problem that oscillation occurs in the operating region where the differential amplifier 11 is differential and feedback is applied to the input of the inverting amplifier 12, making the operation unstable. Ta.
この考案は上記の問題点を解決するために成さ
れたものであり、発振を防止することができる電
圧リミツタ回路を得ることを目的とする。 This invention was made to solve the above-mentioned problems, and the object is to obtain a voltage limiter circuit that can prevent oscillation.
この考案に係る電圧リミツタ回路は、差動増幅
器の出力端と反転入力端との間にコンデンサと抵
抗の並列回路を接続したものである。
The voltage limiter circuit according to this invention has a parallel circuit of a capacitor and a resistor connected between the output terminal and the inverting input terminal of a differential amplifier.
この考案においては、差動増幅器の出力端と反
転入力端との間に接続した抵抗により電力増幅器
の帰還率βを下げ、またコンデンサを接続したこ
とにより帰還入力の位相をずらせる。
In this invention, a resistor connected between the output terminal and the inverting input terminal of the differential amplifier lowers the feedback factor β of the power amplifier, and a capacitor is connected to shift the phase of the feedback input.
以下、この考案の実施例を図面とともに説明す
る。第１図において、６，８は差動増幅器１１の
出力端と反転入力端との間に並列に接続された抵
抗とコンデンサであり、他の構成は従来と同様で
ある。
Examples of this invention will be described below with reference to the drawings. In FIG. 1, numerals 6 and 8 are a resistor and a capacitor connected in parallel between the output terminal and the inverting input terminal of the differential amplifier 11, and the other configurations are the same as the conventional one.
上記構成において、電力増幅器１０の帰還率β
は、抵抗４〜６の抵抗値をR4〜R6として、β＝
R6／R4R5となり、抵抗値R4〜R6により設定する
ことができ、差動増幅器１１のオープンループゲ
インＡより通常は非常に小さくすることができ
る。従つて、帰還率をＡに等しかつた従来回路よ
り小さくすることができる。又、コンデンサ８を
設けたことにより積分器の性格を持たせ、帰還入
力の位相をずらすことができる。このように、帰
還率を低下させ、帰還位相をずらすことにより、
電力増幅器１０の発振を防止することができる。
特に、電力増幅器１０の入力部に電圧平滑のため
のコンデンサ７を接続した場合、フイードバツク
ループの周波数補償だけではリミツタ時の動作が
不安定になり易く、抵抗６を設けた意義は増す。 In the above configuration, the feedback factor β of the power amplifier 10
The resistance values of resistors 4 to 6 are R 4 to R 6 , and β=
R6 / R4R5 , which can be set by the resistance values R4 to R6 , and can usually be made much smaller than the open loop gain A of the differential amplifier 11. Therefore, the feedback factor can be made smaller than that of the conventional circuit, which is equal to A. Further, by providing the capacitor 8, it is possible to provide the character of an integrator and shift the phase of the feedback input. In this way, by lowering the feedback rate and shifting the feedback phase,
Oscillation of the power amplifier 10 can be prevented.
In particular, when the capacitor 7 for voltage smoothing is connected to the input section of the power amplifier 10, frequency compensation of the feedback loop alone tends to make the operation of the limiter unstable, so the significance of providing the resistor 6 increases.
以上のようにこの考案によれば、差動増幅器の
出力端と反転入力端との間に抵抗とコンデンサの
辺列回路を接続したことにより、電力増幅器の帰
還率を小さくするとともに帰還位相をずらすこと
ができ、発振を防止することができ、安定した電
圧リミツタ回路を得ることができる。
As described above, according to this invention, by connecting a side series circuit of resistors and capacitors between the output end and the inverting input end of the differential amplifier, the feedback factor of the power amplifier can be reduced and the feedback phase can be shifted. oscillation can be prevented and a stable voltage limiter circuit can be obtained.
第１図はこの考案による電圧リミツタ回路の回
路図、第２図は電圧リミツタ回路の特性図、第３
図は従来の電圧リミツタ回路の回路図である。
４〜６……抵抗、８……コンデンサ、１０……
電力増幅器、１１……差動増幅器。尚、図中同一
符号は同一または相当部分を示す。
Figure 1 is a circuit diagram of the voltage limiter circuit according to this invention, Figure 2 is a characteristic diagram of the voltage limiter circuit, and Figure 3 is a diagram of the voltage limiter circuit.
The figure is a circuit diagram of a conventional voltage limiter circuit. 4 to 6...Resistor, 8...Capacitor, 10...
Power amplifier, 11...Differential amplifier. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
し、電力増幅器の出力端に差動増幅器の一方の入
力端を接続するとともに、差動増幅器の他方の入
力端にリミツタ基準電圧を供給し、この差動増幅
器の出力をダイオードを介して電力増幅器の入力
部に帰還した電圧リミツタ回路において、差動増
幅器の出力端と反転入力端との間にコンデンサと
抵抗の並列回路を接続したことを特徴とする電圧
リミツタ回路。 A smoothing capacitor is connected to the input of the power amplifier, one input of the differential amplifier is connected to the output of the power amplifier, and a limiter reference voltage is supplied to the other input of the differential amplifier. A voltage limiter circuit in which the output of a dynamic amplifier is fed back to the input section of a power amplifier via a diode, characterized in that a parallel circuit of a capacitor and a resistor is connected between the output terminal of the differential amplifier and the inverting input terminal. Voltage limiter circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986091211U JPH0432814Y2 (en) | 1986-06-12 | 1986-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986091211U JPH0432814Y2 (en) | 1986-06-12 | 1986-06-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62201519U JPS62201519U (en) | 1987-12-22 |
| JPH0432814Y2 true JPH0432814Y2 (en) | 1992-08-06 |
Family
ID=30951782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986091211U Expired JPH0432814Y2 (en) | 1986-06-12 | 1986-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0432814Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010068078A (en) * | 2008-09-09 | 2010-03-25 | Renesas Technology Corp | Rf power amplifier and operation method therefor |
| JP2016152583A (en) * | 2015-02-19 | 2016-08-22 | 旭化成エレクトロニクス株式会社 | Output amplifier and ic chip including the same |
-
1986
- 1986-06-12 JP JP1986091211U patent/JPH0432814Y2/ja not_active Expired
Non-Patent Citations (1)
| Title |
|---|
| ELECTRONIC DESIGN * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62201519U (en) | 1987-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5992361A (en) | Capacitive sensor linearization circuit | |
| JPH0432814Y2 (en) | ||
| JPS6218807A (en) | Current mirror circuit | |
| US4602224A (en) | Variable capacitance reactance circuit | |
| CN103683928A (en) | Leading phase compensating circuit integrated with switching regulator | |
| JPS6017955Y2 (en) | signal conversion circuit | |
| CN203813660U (en) | Leading phase compensating circuit for integrated switching voltage regulator | |
| JPS5934169Y2 (en) | amplifier circuit | |
| US4560958A (en) | State variable oscillator having improved rejection of leveler-induced distortion | |
| JPS6043681B2 (en) | Frequency multiplier circuit | |
| JPH05119856A (en) | Semiconductor constant voltage generator | |
| JPS6016099Y2 (en) | Twin T-shaped oscillator circuit | |
| JPH0129852Y2 (en) | ||
| JPH0640608B2 (en) | Automatic gain control circuit | |
| JPS63102326U (en) | ||
| JPH04266207A (en) | DC offset compensation circuit | |
| JPH0212732Y2 (en) | ||
| JPS6315917Y2 (en) | ||
| JPS5822889U (en) | High voltage stabilization circuit | |
| JP2513767B2 (en) | Voltage controlled oscillator | |
| JPS5914817Y2 (en) | Stabilized power supply circuit | |
| JPS635433Y2 (en) | ||
| JPS62171210A (en) | Variable crystal oscillation circuit | |
| JPH084730Y2 (en) | Negative feedback amplifier circuit | |
| JPS6216572B2 (en) |