JPH0432831Y2 - - Google Patents

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Publication number
JPH0432831Y2
JPH0432831Y2 JP1986015686U JP1568686U JPH0432831Y2 JP H0432831 Y2 JPH0432831 Y2 JP H0432831Y2 JP 1986015686 U JP1986015686 U JP 1986015686U JP 1568686 U JP1568686 U JP 1568686U JP H0432831 Y2 JPH0432831 Y2 JP H0432831Y2
Authority
JP
Japan
Prior art keywords
voltage controlled
diode
amplifier
controlled oscillator
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1986015686U
Other languages
Japanese (ja)
Other versions
JPS62129848U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986015686U priority Critical patent/JPH0432831Y2/ja
Publication of JPS62129848U publication Critical patent/JPS62129848U/ja
Application granted granted Critical
Publication of JPH0432831Y2 publication Critical patent/JPH0432831Y2/ja
Expired legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Transceivers (AREA)

Description

【考案の詳細な説明】 (技術分野) この考案は無線機等に使用する電圧制御発振器
(VCO)の改良に関するものである。(従来技術
とその問題点) 第2図は従来の実施例である。2は送信用の電
圧制御発振器(以下VCOと呼ぶ)、3は受信用の
VCO、1は2,3のVCOの入力制御端子、4,
5はVCO2,3の出力結合容量、8はエミツタ
フオロワーで形成するかん衝増幅器(トランジス
タ)、6,7は直流バイアス抵抗、9は結合容量、
14は増幅器(トランジスタ)、10、12は直
流バイアス抵抗、11,13は高周波バイパスコ
ンデンサ、15,16,17は出力整合回路素
子、18は出力端子、19,22は送信、受信切
換用スイツチングトランジスタ、20,21は直
流制限抵抗、24は19,22スイツチングのト
ランジスタの制御端子、23は電圧印加端子であ
る。
[Detailed description of the invention] (Technical field) This invention relates to the improvement of voltage controlled oscillators (VCOs) used in radio equipment and the like. (Prior art and its problems) FIG. 2 shows a conventional embodiment. 2 is a voltage controlled oscillator (hereinafter referred to as VCO) for transmission, and 3 is for reception.
VCO, 1 is the input control terminal for VCOs 2 and 3, 4,
5 is the output coupling capacitance of VCO2 and 3, 8 is a buffer amplifier (transistor) formed by an emitter follower, 6 and 7 are DC bias resistors, 9 is a coupling capacitor,
14 is an amplifier (transistor), 10 and 12 are DC bias resistors, 11 and 13 are high frequency bypass capacitors, 15, 16 and 17 are output matching circuit elements, 18 is an output terminal, 19 and 22 are switching for transmission and reception switching The transistors 20 and 21 are DC limiting resistors, 24 is a control terminal of a switching transistor 19 and 22, and 23 is a voltage application terminal.

第2図において動作例を示す。 An example of operation is shown in FIG.

今端子24をLOWレベルにすると、トランジ
スタ22は導通し、受信用VCO3に電圧が印加
される。この時トランジスタ19は非導通とな
り、送信用VCO2に電圧は印加されない。
Now, when the terminal 24 is set to LOW level, the transistor 22 becomes conductive and a voltage is applied to the receiving VCO 3. At this time, the transistor 19 becomes non-conductive, and no voltage is applied to the transmission VCO 2.

即ち受信用VCO3のみ動作し、その発振出力
は結合容量5を介してかん衝増幅器8を経由して
増幅器14に注入される、注入された発振出力は
増幅器14、出力整合素子15,16,17を通
つて出力端18にあらわれる。次に制御端子24
をHighレベルにするとトランジスタ22は非導
通、トランジスタ19は導通状態になる。受信用
VCO3の電圧は直流制限高抵抗20を介してい
るので非常に低く、VCO3は動作しない。前記
トランジスタ19を介してVCO2の電圧が印加
され、VCO2のみが動作する。その発振出力は
前記同様に出力端18にあらわれる。しかし従来
の技術ではトランジスタ8,14を各々独立して
直流バイアスを印加しているので消費電流が多
い。特に低消費電流化を要求される受信機等の受
信用VCOとしては致命的である。又トランジス
タ8,14の利得は送信時にも、受信時にもほぼ
一定であるため、出力端18にあらわれる出力レ
ベルは送信時、受信時ともほぼ同一レベルとな
り、一般的に送信時には出力レベルを大きく取り
たい場合の欠点となつていた。
That is, only the receiving VCO 3 operates, and its oscillation output is injected into the amplifier 14 via the coupling capacitor 5 and the buffer amplifier 8. It appears at the output end 18 through. Next, the control terminal 24
When the signal is set to High level, the transistor 22 becomes non-conductive and the transistor 19 becomes conductive. For reception
Since the voltage of VCO3 is passed through the DC limiting high resistance 20, it is very low and VCO3 does not operate. The voltage of VCO2 is applied through the transistor 19, and only VCO2 operates. The oscillation output appears at the output terminal 18 in the same manner as described above. However, in the conventional technology, a direct current bias is applied to each of the transistors 8 and 14 independently, resulting in a large amount of current consumption. This is especially fatal for receiving VCOs such as receivers that require low current consumption. Furthermore, since the gains of the transistors 8 and 14 are almost constant during transmission and reception, the output level appearing at the output terminal 18 is approximately the same level during transmission and reception, and generally the output level is set high during transmission. This has become a drawback if you want to.

(目的) この考案はこれらの欠点を解決するため、エミ
ツタフオロワかん衝増幅器と増幅器を直流的に縦
続接続して使用し、受信時の電圧制御発振回路部
の消費電流を低減することにある。また第2の目
的は送信時にのみ前記増幅器のベース電流を増加
せしめて、コレクタ電流を増加し、増幅器の高周
波利得をあげ、送信時の発振出力を受信時よりも
増加せしめることにある。
(Purpose) In order to solve these drawbacks, this invention uses an emitter follower amplifier and an amplifier in direct current cascade connection to reduce the current consumption of the voltage controlled oscillator circuit during reception. A second purpose is to increase the base current of the amplifier only during transmission, increase the collector current, increase the high frequency gain of the amplifier, and increase the oscillation output during transmission compared to during reception.

(実施例) 以下この考案の実施例を第1図により説明す
る。第1図において第2図と同一番号は同一機能
のものを示す。27は高周波バイパス容量、25
は直流制御抵抗、26はダイオードである。以下
この動作について説明する。制御端子24を
LOWレベルにするとトランジスタ22は導通し
受信用VCO3に電圧が印加され、VCOは動作す
る。VCO3の出力は結合コンデンサ5及びエミ
ツタフオロワかん衝増幅器8の結合コンデンサ9
を介して増幅器10の入力に注入され、増幅後、
出力端子18に受信用VCO出力が得られる。一
方19のトランジスタは非導通となり送信用
VCO2の電圧は6−2,6−1,25の直流制
御抵抗と、26のダイオードを介して印加される
が、2のVCOに印加される電圧は極めて低い電
圧のため2の送信用VCOは動作しない。ここで
8及び10のトランジスタの直流バイアスに注目
すると、トランジスタ8のベース電位V8bは V8b=(Vcc−V10b/r6-1+r6-2) ×(r6-1)+V10b (ここでVcc;23の電源電圧、V10b;受信用
VCO動作時のトランジスタ10のベース電位、
r6-1,r6-2;6−1,6−2の直流抵抗値を示す。
次に制御端子24がHighレベルのとき、トラ
ンジスタ19は導通し、送信用VCO2のみが動
作する。ここで前記同様トランジスタ8,10の
直流バイアスに注目すると、26のダイオードに
は逆バイアスがかかり非導通となる。トランジス
タ8のベース電位V′8bはV′8b=(Vcc−V′10b/r6-2
+r6-1)(r6-1)+V′10bであらわされる(ここで
V10b;送信用VCO動作時のトランジスタ10の
ベース電位を示す。)、両式の差(V′8b′−V8b)は V8b′−V8b=(V10b−V′10b/r6-1+r6-2)×(r6-1
)+(V′10b−V10b) =(V′10b−V10b)(1−r6-1/r6-1+r6-2)=(
V′10b−V10b)(r6-2/r6-1+r6-2)となる。
(Example) An example of this invention will be described below with reference to FIG. In FIG. 1, the same numbers as in FIG. 2 indicate the same functions. 27 is a high frequency bypass capacitor, 25
is a DC control resistor, and 26 is a diode. This operation will be explained below. Control terminal 24
When set to LOW level, the transistor 22 becomes conductive and a voltage is applied to the receiving VCO 3, so that the VCO operates. The output of VCO3 is the coupling capacitor 5 and the coupling capacitor 9 of the emitter follower amplifier 8.
is injected into the input of amplifier 10 via
A receiving VCO output is obtained at the output terminal 18. On the other hand, transistor 19 becomes non-conductive and is used for transmission.
The voltage of VCO2 is applied through the DC control resistors 6-2, 6-1, 25 and the diode 26, but since the voltage applied to VCO 2 is extremely low, the transmitting VCO 2 is Do not work. Now, focusing on the DC bias of transistors 8 and 10, the base potential V 8b of transistor 8 is V 8b = (Vcc - V 10b / r 6-1 + r 6-2 ) × (r 6-1 ) + V 10b ( where Vcc; 23 power supply voltage, V 10b ; for receiving
Base potential of transistor 10 during VCO operation,
r 6-1 , r 6-2 ; Indicates the DC resistance value of 6-1 and 6-2.
Next, when the control terminal 24 is at a high level, the transistor 19 becomes conductive and only the transmission VCO 2 operates. Here, similarly to the above, focusing on the DC bias of transistors 8 and 10, diode 26 is reverse biased and becomes non-conductive. The base potential V′ 8b of transistor 8 is V′ 8b = (Vcc−V′ 10b /r 6-2
+r 6-1 ) (r 6-1 )+V′ 10b (where
V 10b ; Indicates the base potential of the transistor 10 during transmission VCO operation. ), the difference between both equations (V′ 8b ′−V 8b ) is V 8b ′−V 8b = (V 10b −V′ 10b / r 6-1 + r 6-2 )×(r 6-1
) + (V′ 10b −V 10b ) = (V′ 10b −V 10b ) (1−r 6-1 / r 6-1 + r 6-2 ) = (
V′ 10b −V 10b ) (r 6-2 / r 6-1 + r 6-2 ).

ここでV′10b−V10b>0となるように抵抗値25
を設計するとV8b′>V8bとなる。即ち送信用VCO
動作時には、トランジスタ8及び10のベース電
流が増加、従つてコレクタ電流が増加し、トラン
ジスタ10の高周波利得が増加する。その結果送
信用VCO動作の方が受信用VCO動作に比して、
出力レベルが高くなる。
Here, the resistance value is set to 25 so that V′ 10b −V 10b > 0.
When designing, V 8b ′> V 8b . In other words, the transmitting VCO
In operation, the base currents of transistors 8 and 10 increase, and thus the collector currents increase, and the high frequency gain of transistor 10 increases. As a result, the transmission VCO operation is better than the reception VCO operation.
The output level becomes higher.

一方、直流電流に着目すると、逆に受信用
VCO動作時には送信用VCO動作時に比しトラン
ジスタのベース電位が低くなり、コレクタ電流が
小さくなる。且つ、2個のトランジスタを直流的
に縦続接続して使用しているので従来の回路方式
より電流は半減できる。
On the other hand, if we focus on direct current,
During VCO operation, the base potential of the transistor becomes lower than when transmitting VCO operates, and the collector current becomes smaller. In addition, since two transistors are used in a cascade connection using direct current, the current can be reduced by half compared to the conventional circuit system.

【図面の簡単な説明】[Brief explanation of the drawing]

第2図は従来の電圧制御発振(VCO)回路実
施例、第1図は本考案の実施例。 1……入力制御端子、2……送信用VCO、3
……受信用VCO、4,5,9……結合容量、6
−1,6−2,7,12,25……直流バイアス
抵抗、11,13,27……高周波バイパスコン
デンサ、16,17……整合素子容量、8,10
……高周波増幅用トランジスタ、15……整合素
子インダクタンス、19,22……スイツチング
トランジスタ、20,21……直流制限抵抗、2
3……電源端子、24……送,受切替端子、18
……出力端子。
Figure 2 shows an example of a conventional voltage controlled oscillator (VCO) circuit, and Figure 1 shows an example of the present invention. 1...Input control terminal, 2...VCO for transmission, 3
...Receiving VCO, 4, 5, 9...Coupling capacitance, 6
-1, 6-2, 7, 12, 25... DC bias resistance, 11, 13, 27... High frequency bypass capacitor, 16, 17... Matching element capacitance, 8, 10
... High frequency amplification transistor, 15 ... Matching element inductance, 19, 22 ... Switching transistor, 20, 21 ... DC limiting resistor, 2
3...Power terminal, 24...Transmission/reception switching terminal, 18
...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信用電圧制御発振器と受信用電圧制御発振器
の2個からなるシンセサイザ方式電子装置の、前
記電圧制御発振器の出力にエミツタフオロワーで
構成するかん衝増幅器と前記電圧制御発振器の出
力を増幅する高周波増幅器を直流的に継続接続し
て前記2個の増幅器のコレクタ電流を共用化せし
める回路において前記高周波増幅器のベースバイ
アス回路に固定バイアス抵抗と直列にダイオード
を挿入し、送信時には該ダイオードに逆バイアス
を印加して非導通として、前記かん衝増幅器と高
周波増幅器のベース固定バイアス抵抗値を小さく
してベース電流を増加ならしめて、コレクタ電流
を増加し、受信時には該ダイオードを順方向にバ
イアスして導通せしめて、前記増幅器のベース固
定バイアス抵抗値を大きくしてベース電流を小な
らしめて、コレクタ電流を減少せしめることを特
徴とした電圧制御発振装置。
A synthesizer-type electronic device consisting of two voltage controlled oscillators, a transmitting voltage controlled oscillator and a receiving voltage controlled oscillator, includes a high frequency amplifier for amplifying the output of the voltage controlled oscillator and an emitter follower for the output of the voltage controlled oscillator. In a circuit in which amplifiers are continuously connected in a DC manner to share the collector current of the two amplifiers, a diode is inserted in series with a fixed bias resistor in the base bias circuit of the high frequency amplifier, and the diode is reverse biased during transmission. The voltage is applied to make the diode non-conducting, and the base fixed bias resistance values of the amplifier and high-frequency amplifier are reduced to increase the base current, increasing the collector current, and during reception, the diode is biased in the forward direction to make the diode conductive. A voltage controlled oscillation device characterized in that the collector current is decreased by increasing the base fixed bias resistance value of the amplifier to decrease the base current.
JP1986015686U 1986-02-07 1986-02-07 Expired JPH0432831Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986015686U JPH0432831Y2 (en) 1986-02-07 1986-02-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986015686U JPH0432831Y2 (en) 1986-02-07 1986-02-07

Publications (2)

Publication Number Publication Date
JPS62129848U JPS62129848U (en) 1987-08-17
JPH0432831Y2 true JPH0432831Y2 (en) 1992-08-06

Family

ID=30806846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986015686U Expired JPH0432831Y2 (en) 1986-02-07 1986-02-07

Country Status (1)

Country Link
JP (1) JPH0432831Y2 (en)

Also Published As

Publication number Publication date
JPS62129848U (en) 1987-08-17

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